CN103515433A - NMOS transistor and formation method thereof, and SRAM memory cell circuit - Google Patents
NMOS transistor and formation method thereof, and SRAM memory cell circuit Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The invention relates to an NMOS transistor and a formation method thereof, and a static random access memory (SRAM) cell circuit. The NMOS transistor comprises a semiconductor substrate, a gate structure arranged at the bottom of the semiconductor substrate, a flank arranged at the side wall of the gate structure, a source region, a drain region, and a stretching stress layer arranged on the source region or the drain region, wherein the source region and the drain region are arranged in the semiconductor substrate at the two sides of the gate structure. Because the stretching stress layer is arranged on the source region or the drain region, tensile stress exerted on the channel region are uniform and asymmetrical, so that saturation source-leakage currents of the MOS transistor at different current directions are different. Moreover, the MOS transistor is used as a transmission transistor of the SRAM memory cell circuit, so that the writing margin of the SRAM memory unit is improved under the circumstances that the reading margin of the SRAM memory unit is not reduced and thus the reading-writing stability of the SRAM memory unit is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, relate in particular to the asymmetric nmos pass transistor of Yuan/ drain region stress and formation method, there is the SRAM storage unit circuit that height writes nargin.
Background technology
Static random access memory (Static RandomAccess Memory, SRAM) as a member in memory, there is high-speed, low-power consumption and the standard technology advantage such as compatibility mutually, be widely used in the fields such as PC, personal communication, consumption electronic product (smart card, digital camera, multimedia player).
Fig. 1 is the electrical block diagram of memory cell of the SRAM memory of existing 6T structure, and described memory cell comprises: a PMOS transistor P1, the 2nd PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4.
A described PMOS transistor P1, the 2nd PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2 form bistable circuit, and described bistable circuit forms a latch for latch data information.A described PMOS transistor P1 and the 2nd PMOS transistor P2 are for pulling up transistor; Described the first nmos pass transistor N1 and the second nmos pass transistor N2 are pull-down transistor.The 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 are transmission transistor.
The one grid of PMOS transistor P1,, the source electrode of the grid of the first nmos pass transistor N1, the 2nd drain electrode of PMOS transistor P2, the drain electrode of the second nmos pass transistor N2, the 4th nmos pass transistor N4 is electrically connected to, forms the first memory node 11; The 2nd grid of PMOS transistor P2,, the source electrode of the grid of the second nmos pass transistor N2, a drain electrode of PMOS transistor P1, the drain electrode of the first nmos pass transistor N1, the 3rd nmos pass transistor N3 is electrically connected to, forms the second memory node 12.
The grid of the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is electrically connected to word line WL; The drain electrode of the 3rd nmos pass transistor N3 is electrically connected to the first bit line BL, and the drain electrode of the 4th nmos pass transistor N4 is electrically connected to the second bit line (paratope line) BLB; The source electrode of the source electrode of the one PMOS transistor P1 and the 2nd PMOS transistor P2 is electrically connected to power line Vdd; The source electrode of the source electrode of the first nmos pass transistor N1 and the second nmos pass transistor N2 is electrically connected to ground wire Vss.
The operation principle of the memory cell of the SRAM memory of described 6T structure is:
During read operation, word line WL applies high level, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 conducting, the first bit line BL and the second bit line BLB apply high level, due to the first memory node 11 and the second memory node 12, one of them is low level, electric current is from the first bit line BL, the second bit line BLB flows to low level the first memory node 11 or the second memory node 12, the current potential of described the first bit line BL or the second bit line BLB reduces, between the first bit line BL and the second bit line BLB, current potential produces voltage difference, after reaching certain value, voltage difference opens sensitivity amplifier (not shown), voltage is amplified, deliver to again output circuit (not shown), sense data,
During write operation, word line WL applies high level, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 conducting, one that the first bit line BL and the second bit line BLB are corresponding applies high level, one applies low level, due to the first memory node 11 and the second memory node 12, one of them is high level, another is low level, when the data message of write operation is different with the data message of original storage, electric current flows to low level the first bit line BL or the second bit line BLB from the first memory node 11 or second memory node 12 of high level, the first memory node 11 of high level or the current potential of the second memory node 12 are reduced, the current potential of another low level second memory node 12 or the first memory node 11 improves, the data that SRAM memory cell stores is new.
But along with the process node of CMOS technique reduces, operating voltage reduces, random doping causes threshold voltage variation to increase, and brings challenges to the read stability of SRAM.In order to make SRAM memory stably work, need to improve the read margin of SRAM memory and write nargin, therefore how improving the read margin of SRAM memory and writing nargin just becomes one of those skilled in the art's problem demanding prompt solution.
More introductions about SRAM memory please refer to the United States Patent (USP) that publication number is US2007/0241411A1.
Summary of the invention
The problem that the present invention solves is to provide the asymmetric nmos pass transistor of one provenance/drain region stress and formation method, has the SRAM storage unit circuit that height writes nargin.
For addressing the above problem, technical solution of the present invention provides a kind of nmos pass transistor, comprising:
Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface, is positioned at Semiconductor substrate Nei source region and the drain region of described grid structure both sides, is positioned at the tension stress layer on described source region or drain region.
Optionally, the material of described tension stress layer be silicon nitride, doped with the silicon nitride of carbon, silica, carborundum or silicon oxynitride doped with carbon.
Optionally, the thickness range of described tension stress layer is 100 dust ~ 1000 dusts.
Optionally, also comprise: be positioned at the etching barrier layer on described source region, drain region and grid structure surface, described tension stress layer is positioned at the etching barrier layer surface on described source region or drain region.
Optionally, the material of described etching barrier layer is silica, silicon nitride or silicon oxynitride, and the material of described etching barrier layer is different with the material of tension stress layer.
Optionally, also comprise: be positioned at the stress material layer on described source region, drain region and grid structure surface, and the stress material layer that is only positioned at described source region or drain region top has tensile stress, described in there is tensile stress stress material layer as tension stress layer.
Technical solution of the present invention also provides a kind of formation method of nmos pass transistor, comprising: Semiconductor substrate is provided, at described semiconductor substrate surface, forms grid structure; In the Semiconductor substrate of described grid structure one side, form source region, in the Semiconductor substrate of described grid structure opposite side, form drain region; On described source region or drain region, form tension stress layer.
Optionally, the method that forms tension stress layer comprises: form behind source region and drain region, in described source region, drain region and grid structure surface form etching barrier layer; On described etching barrier layer surface, form stress material layer; Described stress material layer is carried out to stress processing; Described stress material layer is carried out to etching, and the etching barrier layer surface on described source region or drain region forms tension stress layer.
Optionally, the method that forms tension stress layer comprises: form behind source region and drain region, in described source region, drain region and grid structure surface form etching barrier layer; On described etching barrier layer surface, form stress material layer; Described stress material layer is carried out to stress processing; The stress material layer of the stress material layer on drain region or source region and part of grid pole body structure surface is injected to heavy ion, the stress that makes to be arranged in the stress material layer of stress material layer on drain region or source region and part of grid pole body structure surface is released, and the stress material layer on remaining described source region or drain region forms tension stress layer.
Optionally, the concrete technology that forms described etching barrier layer and stress material layer is plasma enhanced chemical vapor deposition technique, low-pressure chemical vapor deposition process or atom layer deposition process.
Optionally, the stress material layer of described formation has tensile stress.
Optionally, the thickness range of described stress material layer is 100 dust ~ 1000 dusts.
Optionally, the mode of described stress processing comprises ultraviolet irradiation, electron beam irradiation or Ear Mucosa Treated by He Ne Laser Irradiation.
Technical solution of the present invention also provides a kind of SRAM storage unit circuit, comprising: a PMOS transistor, the 2nd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor; The grid of the transistorized grid of the one PMOS, the first nmos pass transistor, the transistorized drain electrode of the 2nd PMOS, the drain electrode of the second nmos pass transistor,, the source electrode of the 4th nmos pass transistor is electrically connected to, form the second memory node; The grid of the transistorized grid of the 2nd PMOS, the second nmos pass transistor, the transistorized drain electrode of a PMOS, the drain electrode of the first nmos pass transistor,, the source electrode of the 3rd nmos pass transistor is electrically connected to, form the first memory node; The grid of the 3rd nmos pass transistor and the 4th nmos pass transistor is electrically connected to word line; The drain electrode of the 3rd nmos pass transistor is electrically connected to the first bit line, and the drain electrode of the 4th nmos pass transistor is electrically connected to the second bit line; The transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected to power end; The source electrode of the source electrode of the first nmos pass transistor and the second nmos pass transistor is electrically connected to earth terminal; Wherein, the source electrode of described the 3rd nmos pass transistor and the 4th nmos pass transistor does not have tension stress layer on corresponding source region, on the drain region of the drain electrode correspondence of described the 3rd nmos pass transistor and the 4th nmos pass transistor, has tension stress layer.
Optionally, the material of described tension stress layer be silicon nitride, doped with the silicon nitride of carbon, silica, carborundum or silicon oxynitride doped with carbon.
Optionally, the thickness range of described tension stress layer is 100 dust ~ 1000 dusts.
Compared with prior art, the present invention has the following advantages:
The nmos pass transistor of the embodiment of the present invention comprises: Semiconductor substrate, be positioned at the grid structure of described semiconductor substrate surface, be positioned at the side wall of described grid structure sidewall, the Semiconductor substrate Nei source region and the drain region that are positioned at described grid structure both sides, be positioned at the tension stress layer on described source region or drain region.Because described tension stress layer is positioned on source region or is positioned on drain region, the inhomogeneous symmetry of tensile stress that channel region is subject to, makes the saturated drain-source current of the different senses of current of described nmos pass transistor different.
In the SRAM of embodiment of the present invention storage unit circuit, the tensile stress being subject to as the 3rd nmos pass transistor of transmission transistor and the channel region of the 4th nmos pass transistor is asymmetric, can be when improving write operation in the saturated drain-source current of transmission transistor, the saturated drain-source current of transmission transistor while not reducing read operation, thereby when not reducing the read margin of SRAM memory cell, improve the nargin that writes of SRAM memory cell, thereby can improve the read-write stability of SRAM memory cell.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of memory cell of the SRAM memory of prior art;
Fig. 2 is the schematic flow sheet of formation method of the nmos pass transistor of the embodiment of the present invention;
Fig. 3 to Fig. 8 is the cross-sectional view of forming process of the nmos pass transistor of the embodiment of the present invention;
Fig. 9 is the stress envelope of the channel region of the nmos pass transistor of the embodiment of the present invention and the nmos pass transistor of prior art;
Figure 10 is the structural representation of the SRAM storage unit circuit of the embodiment of the present invention.
Embodiment
The read-write stability of SRAM memory is mainly by read margin with write these two parameters of nargin and weigh, the maximum noise voltage that when read margin is read operation, SRAM memory can tolerate under the prerequisite that does not change store status, the maximum noise voltage that when writing nargin and being write operation, SRAM memory can tolerate under the prerequisite that does not change store status.Read margin and to write nargin higher, the read-write stability of SRAM memory is better.Wherein, read margin is relevant to the ratio between the transistorized saturated drain-source current value of pull-down NMOS and the saturated drain-source current value of transmission nmos pass transistor; Write nargin and transmit the saturated drain-source current value of nmos pass transistor and above draw the ratio between the transistorized saturated drain-source current value of PMOS relevant.
In order to improve read margin, while drawing PMOS transistor and the transistorized structure of pull-down NMOS not to change on described, need to reduce transmission nmos pass transistor from the saturated drain-source current value of drain-to-source; In order improving, to write nargin, while drawing PMOS transistor and the transistorized structure of pull-down NMOS not to change on described, to need to improve the saturated drain-source current value of transmission nmos pass transistor from source electrode to drain electrode.In the prior art, because the source electrode of described transmission nmos pass transistor (the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4) and drain electrode are symmetrical, therefore, the saturated drain-source current value of transmission nmos pass transistor from source electrode to drain electrode is consistent with the saturated drain-source current value from drain-to-source, therefore utilize transmission nmos pass transistor to improve to write nargin and read margin is contradiction simultaneously, when improving the read margin of transmission nmos pass transistor, will inevitably reduce and write nargin, vice versa.
For this reason, inventor is through research, proposed the asymmetric nmos pass transistor of one provenance/drain region stress and formation method and utilized described nmos pass transistor as the SRAM storage unit circuit of transmission transistor, on the source region of described nmos pass transistor or drain region, having there is tension stress layer.When described nmos pass transistor is in saturation region, when source-drain voltage is more than or equal to saturated source-drain voltage, channel region is by pinch off, channel region only at raceway groove pinch-off point be applied with between low level source region or drain region, so the saturated migration rate of the charge carrier of nmos pass transistor depends on the saturated migration rate of the charge carrier in the close channel region that is applied with low level source region or drain region.Due to described tension stress layer can be corresponding in the channel region near described source region or drain region, form tensile stress, therefore when channel region is formed with the source region of tension stress layer or drain region near described surface, the saturated migration rate of the charge carrier of channel region can become greatly, and the saturated drain-source current of the different senses of current of nmos pass transistor is varied in size.And utilize the nmos pass transistor varying in size of saturated drain-source current of the described different senses of current as the transmission transistor of SRAM storage unit circuit, can improve the nargin that writes of SRAM memory cell.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
First the embodiment of the present invention provides a kind of formation method of nmos pass transistor, please refer to Fig. 2, and the schematic flow sheet for the formation method of the nmos pass transistor of the embodiment of the present invention, specifically comprises:
Step S101, provides Semiconductor substrate, at described semiconductor substrate surface, forms grid structure;
Step S102 forms the first light doping section and the second light doping section in the Semiconductor substrate of described grid structure both sides;
Step S103, in described grid structure sidewall surfaces, form side wall, in the Semiconductor substrate of described grid structure and side wall both sides, form the first heavily doped region and the second heavily doped region, described the first light doping section and the first heavily doped region form source electrode, described the second light doping section and the second formation drain region, heavily doped region;
Step S104, in described source region, drain region and grid structure surface forms etching barrier layer;
Step S105, the etching barrier layer surface above described source region or drain region forms tension stress layer.
Fig. 3 to Fig. 8 is the cross-sectional view of forming process of the nmos pass transistor of the embodiment of the present invention.
Concrete, please refer to Fig. 3, Semiconductor substrate 200 is provided, on described Semiconductor substrate 200 surfaces, form grid structure 210.
The material of described Semiconductor substrate 200 is wherein a kind of of monocrystalline substrate, monocrystalline germanium substrate, germanium silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator.In described Semiconductor substrate 200, be also formed with fleet plough groove isolation structure (not indicating), described fleet plough groove isolation structure, between adjacent device, makes adjacent device electricity isolation.
Described grid structure 210 comprises the gate dielectric layer 211 that is positioned at described Semiconductor substrate 200 surfaces and the gate electrode 212 that is positioned at described gate dielectric layer 211 surfaces.The material of described gate dielectric layer 211 is silica or high-K gate dielectric material, such as hafnium oxide, zirconia etc.Described gate electrode 212 is polygate electrodes or metal gate electrode.In embodiments of the present invention, described gate dielectric layer 211 is silicon oxide layer, and described gate electrode 212 is polygate electrodes.In other embodiments, on described grid structure surface, form silicon oxide layer, utilize described silicon oxide layer can prevent that in follow-up ion implantation technology, foreign ion is injected in gate oxide or gate electrode, affect the electric property of described grid structure.Owing to forming the known technology that the technique of grid structure is those skilled in the art, at this, be not described further.
Please refer to Fig. 4, Semiconductor substrate 200 interior formation the first light doping section 221 and the second light doping section 231 in described grid structure 210 both sides.The technique that forms described the first light doping section 221 and the second light doping section 231 is ion implantation technology, the MOS transistor forming due to the embodiment of the present invention is nmos pass transistor, and the ion that described the first light doping section 221 and the second light doping section 231 are injected is N-type foreign ion.
Please refer to Fig. 5, in described grid structure 210 sidewall surfaces, form side wall 240, in the Semiconductor substrate of described grid structure 210 and side wall both sides, form the first heavily doped region 222 and the second heavily doped region 232, described the first light doping section 221 and the first heavily doped region 222 form source electrode 220, and described the second light doping section 231 and the second heavily doped region 232 form drain region 230.The technique that forms described the first heavily doped region 222 and the second heavily doped region 232 is ion implantation technology, the MOS transistor forming due to the embodiment of the present invention is nmos pass transistor, and the ion that described the first heavily doped region 222 and the second heavily doped region 232 are injected is N-type foreign ion.
In other embodiments, can also carry out Implantation formation bag-like region in described the first light doping section near channel region and the second light doping section one side, described bag-like region can be alleviated short-channel effect.
In other embodiments, the formation technique in described source region and drain region can also be: in the Semiconductor substrate of described grid structure both sides, form groove, in described groove, form silicon carbide layer, in described silicon carbide layer, doped with foreign ion, the described silicon carbide layer doped with foreign ion forms source region and the drain region of nmos pass transistor.
Please refer to Fig. 6, on described grid structure 210 top surfaces, side wall 240 surfaces and Semiconductor substrate 200 surfaces, form etching barrier layer 250, on described etching barrier layer 250 surfaces, form stress material layer 260.
The material of described etching barrier layer 250 and described stress material layer by layer 260 material are different, utilize the material of described etching barrier layer 250 different with the etching selection ratio of the material of stress material layer 260, described etching barrier layer 250 when follow-up remove portion tension stress layer as etch stop layer.
The material of described etching barrier layer 250 can be silica, silicon nitride, silicon oxynitride etc., and the material of described stress material layer 260 can be for silicon nitride, doped with the silicon nitride of carbon, silica, carborundum or silicon oxynitride etc. doped with carbon.The concrete technology that forms described etching barrier layer 250 and stress material layer 260 is plasma enhanced chemical vapor deposition technique, low-pressure chemical vapor deposition process or atom layer deposition process etc.In embodiments of the present invention, the material of described etching barrier layer 250 is silica, the material of described stress material layer 260 is silicon nitride, the thickness range of described etching barrier layer 250 is 50 dust ~ 500 dusts, the thickness range of described stress material layer 260 is 100 dust ~ 1000 dusts, and the technique that forms described silicon oxide layer, silicon nitride layer is plasma enhanced chemical vapor deposition technique.
In other embodiments, before forming described etching barrier layer, on described grid structure top surface, source region and surface, drain region, form metal silicide, be conducive to reduce the metal interconnect structure of follow-up formation and the contact resistance in grid structure, source region and drain region.
Please refer to Fig. 7, described stress material layer 260 is carried out to stress processing.
Described stress is processed and is comprised that counter stress material layer 260 carries out ultraviolet irradiation, electron beam irradiation or Ear Mucosa Treated by He Ne Laser Irradiation etc., and making does not originally have the stress material layer 260 of effect of stress to have tensile stress.In the present embodiment, the stress processing mode adopting is that ultraviolet ray is irradiated, and ultraviolet energy scope is 300 watts every square metre ~ 2000 watts every square metre, and Semiconductor substrate temperature range is 50 ℃ ~ 550 ℃, processing time scope is 2 minutes ~ 120 minutes, and following gas is helium, argon or hydrogen.
In other embodiments, by adjusting the parameter of depositing operation, can also directly utilize depositing operation to form the stress material layer with tensile stress.Therein in an embodiment, when utilizing plasma enhanced chemical vapor deposition technique to form silicon nitride layer, when Semiconductor substrate temperature is 400 ℃, the pressure of reaction chamber is 4.5 holders, radio-frequency power is 500 watts, when reacting gas is ammonia and silane, the silicon nitride layer of formation has tensile stress.Follow-up can also continuation carries out stress processing to having the stress material layer of tensile stress, can further improve the stress of the tension stress layer of final formation.
Please refer to Fig. 8, the stress material layer 260(that removes 220 tops, source region please refer to Fig. 7) and the stress material layer 260 on part of grid pole structure 210 surfaces, above described drain region 230, form tension stress layer 261.
The concrete steps of removing described part stress material layer 260 comprise: at described stress material layer 260(, please refer to Fig. 7) surface formation photoresist mask layer (not shown), described photoresist mask layer exposes the part stress material layer 260 of 220 tops, source region and the stress material layer 260 on part of grid pole structure 210 surfaces, take described photoresist mask layer as mask, the stress material layer 260 exposing is carried out to etching, until expose described etching barrier layer 250, making does not have tension stress layer on the source region 220 of the final nmos pass transistor forming, and on drain region 230, there is tension stress layer 261, 261 pairs of effects that produce tensile stress near 230 channel region, drain region of tension stress layer on described drain region 230, and can not there is tensile stress or there is very little tensile stress near 220 channel region, source region.
In other embodiments, also can not form etching barrier layer, described stress material layer is carried out after stress processing, the stress material layer of top, Hai Dui source region and the stress material layer of part of grid pole body structure surface inject germanium, arsenic, indium, the heavy ions such as antimony, the silazine link that makes to have stress is destroyed, the stress that is arranged in the stress material layer of top, source region and the stress material layer of part of grid pole body structure surface is released, stress material layer on remaining described drain region forms tension stress layer, tension stress layer on described drain region produces the effect of tensile stress to the channel region near drain region, and can not there is tensile stress or there is very little tensile stress near the channel region in source region.
In other embodiments, described tension stress layer also can only form on source region, on drain region, be not formed with tension stress layer, the tension stress layer of top, described source region produces the effect of tensile stress to the channel region near source region, and can not have tensile stress or have very little tensile stress near the channel region in drain region.
After forming tension stress layer 261, can also remove the etching barrier layer 250 exposing, follow-up at described Semiconductor substrate 200 and tension stress layer 261 surface formation interlayer dielectric layers (not shown).
According to above-mentioned nmos pass transistor formation method, the embodiment of the present invention also provides a kind of nmos pass transistor, please refer to Fig. 8, cross-sectional view for the MOS transistor of the embodiment of the present invention, specifically comprise: Semiconductor substrate 200, be positioned at the grid structure 210 on Semiconductor substrate 200 surfaces, be positioned at the side wall 240 of described grid structure 210 sidewall surfaces, be positioned at the Semiconductor substrate 200Nei source region 220 and the Semiconductor substrate 200Nei drain region 230 that is positioned at described grid structure 210 opposite sides of described grid structure 210 1 sides, described source region 220 comprises the first light doping section 221 and the first heavily doped region 222, described the first light doping section 221 and the first heavily doped region 222 are interior doped with N-type foreign ion, described drain region 230 comprises the second light doping section 231 and the second heavily doped region 232, described the second light doping section 231 and the second heavily doped region 232 are doped with N-type foreign ion, be positioned at described source region 220, the etching barrier layer 250 on drain region 230 and grid structure 210 surfaces, be positioned at the tension stress layer 261 on etching barrier layer 250 surfaces of described drain region 230 and part of grid pole structure 210 tops.
The material of described etching barrier layer 250 can be silica, silicon nitride, silicon oxynitride etc., the material of described tension stress layer 261 can be for silicon nitride, doped with the silicon nitride of carbon, silica doped with carbon, carborundum, silicon oxynitride etc., and the material of described etching barrier layer 250 is different from the material of described tension stress layer 261.The thickness range of described etching barrier layer 250 is 50 dust ~ 500 dusts, and the thickness range of described tension stress layer 261 is 100 dust ~ 1000 dusts.
In other embodiments, the material in described source region and drain region is carborundum, can improve the migration rate of the charge carrier of channel region.
In other embodiments, described tension stress layer can also only be positioned at the etching barrier layer surface of described source region and part of grid pole superstructure, is not positioned at the etching barrier layer surface of top, described drain region.
In other embodiments, described nmos pass transistor can also not comprise described etching barrier layer, in described source region, drain region and grid structure surface be formed with stress material layer, and the stress material layer that is only positioned at described source region or top, drain region has tensile stress, forms tension stress layer.
In the present embodiment, because tension stress layer 261 is positioned at etching barrier layer 250 surfaces of described drain region 230 and part of grid pole structure 210 tops, 261 pairs of effects that produce tensile stress near 230 channel region, drain region of tension stress layer of 230 tops, described drain region, and can not there is tensile stress or there is very little tensile stress near 220 channel region, source region, therefore, from 230Dao source region, drain region 220, the size of the tensile stress of described channel region from big to small, because described MOS transistor is nmos pass transistor, from 230Dao source region, drain region 220, the saturated migration rate of the charge carrier of described channel region from big to small.
When nmos pass transistor is in saturation region, when source-drain voltage is more than or equal to saturated source-drain voltage, channel region is by pinch off, described channel region is only present in raceway groove pinch-off point and is applied with between low level source region or drain region, so the saturated migration rate of the charge carrier of nmos pass transistor depends near the saturated migration rate that is applied with the charge carrier in the channel region in low level source region or drain region.Because described nmos pass transistor has different tensile stress sizes near the channel region in source region or drain region, make on the different senses of current the saturated migration rate of charge carrier in channel region different, thereby make the saturated drain-source current of MOS transistor on the different senses of current different.
In the present embodiment, because described MOS transistor is nmos pass transistor, 230 tops, described drain region have tension stress layer, when high level is applied to source region 220, when low level is applied to drain region 230, electric current 220 flows to drain region 230 from source region, saturated drain-source current is larger than the saturated drain-source current of the nmos pass transistor of prior art, and work as high level, be applied to drain region 230, when low level is applied to source region 220, electric current 230 flows to source region 220 from drain region, saturated drain-source current is more or less the same than the saturated drain-source current of the nmos pass transistor of prior art, thereby make the saturated drain-source current of nmos pass transistor on the different senses of current different.
Transmission transistor using the nmos pass transistor of the embodiment of the present invention as SRAM memory cell, therein on a sense of current, saturated drain-source current by described transmission transistor becomes large, on another sense of current, saturated drain-source current by described transmission transistor is substantially constant, just can in the read margin that does not reduce SRAM memory cell, improve the nargin that writes of SRAM memory cell.
Please refer to Fig. 9, for the nmos pass transistor of the embodiment of the present invention and prior art source region and top, drain region all have the stress envelope of channel region of the nmos pass transistor of tension stress layer.Wherein, abscissa be measurement point apart from the distance of channel region central point, the size of the effect of stress that described ordinate is subject to for the measurement point apart from gate oxide 1nm channel region.Wherein, the first curve corresponds to the lateral tensile stress that source region and drain region top all has the nmos pass transistor of tension stress layer, and the top, drain region of only having that the second curve corresponds to the embodiment of the present invention has the lateral tensile stress of the nmos pass transistor of tension stress layer.Wherein, described horizontal Wei Cong source region is to the direction of the parallel and semiconductor substrate surface in drain region.From Fig. 9, can find out easily, because only having top, drain region, the nmos pass transistor of the embodiment of the present invention there is tension stress layer, the size of the stress of channel region is asymmetric, and the tensile stress that the channel region in close drain region is subject to is larger, and the tensile stress that the channel region in close source region is subject to is less.
The embodiment of the present invention also provides a kind of and has utilized described nmos pass transistor as the SRAM storage unit circuit of transmission transistor, please refer to Figure 10, and the structural representation for a kind of SRAM storage unit circuit of the embodiment of the present invention, specifically comprises:
The one PMOS transistor 111, the 2nd PM OS transistor 112, the first nmos pass transistor 121, the second nmos pass transistor 122, the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124;
The source electrode of the drain electrode of the drain electrode of the grid of the grid of the one PMOS transistor 111, the first nmos pass transistor 121, the 2nd PMOS transistor 112, the second nmos pass transistor 122, the 4th nmos pass transistor 124 is electrically connected to, and forms the second memory node 142, the grid of the 2nd PMOS transistor 112, the grid of the second nmos pass transistor 122, the drain electrode of the one PMOS transistor 111, the drain electrode of the first nmos pass transistor 121, the source electrode of the 3rd nmos pass transistor 123 is electrically connected to, form the first memory node 141, a described PMOS transistor 111, the 2nd PMOS transistor 112, the first nmos pass transistor 121, the second nmos pass transistor 122 forms bistable circuit, a described PMOS transistor 111, the 2nd PMOS transistor 112 is for pulling up transistor, described the first nmos pass transistor 121, the second nmos pass transistor 122 is pull-down transistor,
The 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124, as transmission transistor, are connected the first bit line BL, the second bit line BLB with bistable circuit; The grid of described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124 is electrically connected to word line WL, and the drain electrode of the 3rd nmos pass transistor 123 is electrically connected to the first bit line BL, and the drain electrode of the 4th nmos pass transistor 124 is electrically connected to the second bit line (paratope line) BLB; The source electrode of the source electrode of the one PMOS transistor 111 and the 2nd PMOS transistor 112 is electrically connected to power end 151; The source electrode of the source electrode of the first nmos pass transistor 121 and the second nmos pass transistor 122 is electrically connected to earth terminal 152;
The source electrode of described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124 does not have tension stress layer on corresponding source region, on the drain region of the drain electrode correspondence of described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124, has tension stress layer.
Concrete, the device architecture of a described PMOS transistor 111, the 2nd PMOS transistor 112 is identical, the device architecture of described the first nmos pass transistor 121, the second nmos pass transistor 122 is identical, and described the 3rd nmos pass transistor 123 is identical with the device architecture of the 4th nmos pass transistor 124.
The source electrode of described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124 does not have tension stress layer on corresponding source region, on the drain region of the drain electrode correspondence of described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124, there is tension stress layer, can improve the tensile stress near the channel region in drain region.
When SRAM memory is when carrying out write operation, there is electric current to flow to low level the first bit line BL or the second bit line BLB from the first memory node 141 or second memory node 142 of high level.Electric current when described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124 channel regions is saturated drain-source current, be that described the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124 are when saturation region, channel region is by pinch off, channel region is only at raceway groove pinch-off point and be applied with between low level source region or drain region, and the 3rd nmos pass transistor 123 during write operation and the 4th nmos pass transistor 124 saturated drain-source currents depend on the saturated migration rate of charge carrier in channel region.Because write operation Shi channel region is near drain region, stress types near drain region is tensile stress, described transmission transistor is nmos pass transistor, therefore the saturated drain-source current that, the 3rd nmos pass transistor 123 during described write operation and the 4th nmos pass transistor 124 saturated drain-source currents are greater than MOS transistor of the prior art.And the saturated drain-source current value that writes nargin and transmission nmos pass transistor (i.e. the 3rd nmos pass transistor 123 and the 4th nmos pass transistor 124) of SRAM memory cell and above draw the ratio between the saturated drain-source current value of PMOS transistor (i.e. a PMOS transistor 111 and the 2nd PMOS transistor 112) relevant, because the saturated drain-source current value of the transmission nmos pass transistor of the embodiment of the present invention becomes large, the nargin that writes of SRAM memory cell becomes large, makes SRAM memory cell write fashionable stability and uprises.
And because SRAM memory is when carrying out read operation, it is upper that high level is applied to the first bit line BL, the second bit line BLB, made electric current flow to low level the first memory node 141 or the second memory node 142 from the first bit line BL, the second bit line BLB.Because the described channel region with effect of stress is near source region, described transmission transistor is nmos pass transistor, and the channel region near source region only has a little tensile stress or does not have tensile stress, therefore, the 3rd nmos pass transistor 123 during read operation and the 4th nmos pass transistor 124 saturated drain-source currents and the saturated drain-source current of nmos pass transistor of the prior art equate or are slightly larger than the saturated drain-source current of nmos pass transistor of the prior art, make the SRAM memory cell of the embodiment of the present invention can be when not reducing the read margin of SRAM memory cell, improve the nargin that writes of SRAM memory cell.
To sum up, the nmos pass transistor of the embodiment of the present invention comprises: Semiconductor substrate, be positioned at the grid structure of described semiconductor substrate surface, be positioned at the side wall of described grid structure sidewall, the Semiconductor substrate Nei source region and the drain region that are positioned at described grid structure both sides, be positioned at the tension stress layer on described source region or drain region.Because described tension stress layer is positioned on source region or is positioned on drain region, the inhomogeneous symmetry of tensile stress that channel region is subject to, makes the saturated drain-source current of the different senses of current of described nmos pass transistor different.
In the SRAM of embodiment of the present invention storage unit circuit, the tensile stress being subject to as the 3rd nmos pass transistor of transmission transistor and the channel region of the 4th nmos pass transistor is asymmetric, can be when improving write operation in the saturated drain-source current of transmission transistor, the saturated drain-source current of transmission transistor while not reducing read operation, thereby when not reducing the read margin of SRAM memory cell, improve the nargin that writes of SRAM memory cell, thereby can improve the read-write stability of SRAM memory cell.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (16)
1. a nmos pass transistor, is characterized in that, comprising:
Semiconductor substrate, is positioned at the grid structure of described semiconductor substrate surface, is positioned at Semiconductor substrate Nei source region and the drain region of described grid structure both sides, is positioned at the tension stress layer on described source region or drain region.
2. MOS transistor as claimed in claim 1, is characterized in that, the material of described tension stress layer is silicon nitride, doped with the silicon nitride of carbon, silica, carborundum or silicon oxynitride doped with carbon.
3. MOS transistor as claimed in claim 1, is characterized in that, the thickness range of described tension stress layer is 100 dust ~ 1000 dusts.
4. MOS transistor as claimed in claim 1, is characterized in that, also comprises: be positioned at the etching barrier layer on described source region, drain region and grid structure surface, described tension stress layer is positioned at the etching barrier layer surface on described source region or drain region.
5. MOS transistor as claimed in claim 4, is characterized in that, the material of described etching barrier layer is silica, silicon nitride or silicon oxynitride, and the material of described etching barrier layer is different with the material of tension stress layer.
6. MOS transistor as claimed in claim 1, it is characterized in that, also comprise: the stress material layer that is positioned at described source region, drain region and grid structure surface, and the stress material layer that is only positioned at described source region or drain region top has tensile stress, described in there is tensile stress stress material layer as tension stress layer.
7. a formation method for nmos pass transistor, is characterized in that, comprising:
Semiconductor substrate is provided, at described semiconductor substrate surface, forms grid structure;
In the Semiconductor substrate of described grid structure one side, form source region, in the Semiconductor substrate of described grid structure opposite side, form drain region;
On described source region or drain region, form tension stress layer.
8. the formation method of MOS transistor as claimed in claim 7, is characterized in that, the method that forms tension stress layer comprises:
Form behind source region and drain region, in described source region, drain region and grid structure surface form etching barrier layer;
On described etching barrier layer surface, form stress material layer;
Described stress material layer is carried out to stress processing;
Described stress material layer is carried out to etching, and the etching barrier layer surface on described source region or drain region forms tension stress layer.
9. the formation method of MOS transistor as claimed in claim 7, is characterized in that, the method that forms tension stress layer comprises:
Form behind source region and drain region, in described source region, drain region and grid structure surface form etching barrier layer;
On described etching barrier layer surface, form stress material layer;
Described stress material layer is carried out to stress processing;
The stress material layer of the stress material layer on drain region or source region and part of grid pole body structure surface is injected to heavy ion, the stress that makes to be arranged in the stress material layer of stress material layer on drain region or source region and part of grid pole body structure surface is released, and the stress material layer on remaining described source region or drain region forms tension stress layer.
10. the formation method of MOS transistor as claimed in claim 8 or 9, it is characterized in that, the concrete technology that forms described etching barrier layer and stress material layer is plasma enhanced chemical vapor deposition technique, low-pressure chemical vapor deposition process or atom layer deposition process.
The formation method of 11. MOS transistor as claimed in claim 10, is characterized in that, the stress material layer of described formation has tensile stress.
The 12. formation methods of MOS transistor as claimed in claim 8 or 9, is characterized in that, the thickness range of described stress material layer is 100 dust ~ 1000 dusts.
The 13. formation methods of MOS transistor as claimed in claim 8 or 9, is characterized in that, the mode that described stress is processed comprises ultraviolet irradiation, electron beam irradiation or Ear Mucosa Treated by He Ne Laser Irradiation.
14. 1 kinds of SRAM storage unit circuits, is characterized in that, comprising:
The one PMOS transistor, the 2nd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor;
The grid of the transistorized grid of the one PMOS, the first nmos pass transistor, the transistorized drain electrode of the 2nd PMOS, the drain electrode of the second nmos pass transistor,, the source electrode of the 4th nmos pass transistor is electrically connected to, form the second memory node; The grid of the transistorized grid of the 2nd PMOS, the second nmos pass transistor, the transistorized drain electrode of a PMOS, the drain electrode of the first nmos pass transistor,, the source electrode of the 3rd nmos pass transistor is electrically connected to, form the first memory node;
The grid of the 3rd nmos pass transistor and the 4th nmos pass transistor is electrically connected to word line; The drain electrode of the 3rd nmos pass transistor is electrically connected to the first bit line, and the drain electrode of the 4th nmos pass transistor is electrically connected to the second bit line; The transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected to power end; The source electrode of the source electrode of the first nmos pass transistor and the second nmos pass transistor is electrically connected to earth terminal;
Wherein, the source electrode of described the 3rd nmos pass transistor and the 4th nmos pass transistor does not have tension stress layer on corresponding source region, on the drain region of the drain electrode correspondence of described the 3rd nmos pass transistor and the 4th nmos pass transistor, has tension stress layer.
15. SRAM storage unit circuits as claimed in claim 14, is characterized in that, the material of described tension stress layer is silicon nitride, doped with the silicon nitride of carbon, silica, carborundum or silicon oxynitride doped with carbon.
16. SRAM storage unit circuits as claimed in claim 14, is characterized in that, the thickness range of described tension stress layer is 100 dust ~ 1000 dusts.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302000A (en) * | 2016-04-14 | 2017-10-27 | 中芯国际集成电路制造(上海)有限公司 | Sram memory and forming method thereof |
| CN112103332A (en) * | 2020-11-09 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Static random access memory and manufacturing method thereof |
| CN116437657A (en) * | 2023-06-14 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Method for preparing static random access memory unit |
| CN116631472A (en) * | 2023-07-18 | 2023-08-22 | 全芯智造技术有限公司 | Semiconductor device, method for manufacturing the same, and method for optimizing parameters |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050218455A1 (en) * | 2004-03-30 | 2005-10-06 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device, layout and manufacturing method |
| US20100171181A1 (en) * | 2009-01-07 | 2010-07-08 | Samsung Electronics Co., Ltd. | Method of forming a semiconductor device having an epitaxial source/drain |
| CN102376577A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating damage to etching barrier layer and method for implementing stress memory technology |
-
2012
- 2012-06-26 CN CN201210214126.XA patent/CN103515433B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050218455A1 (en) * | 2004-03-30 | 2005-10-06 | Samsung Electronics Co., Ltd. | Low noise and high performance LSI device, layout and manufacturing method |
| US20100171181A1 (en) * | 2009-01-07 | 2010-07-08 | Samsung Electronics Co., Ltd. | Method of forming a semiconductor device having an epitaxial source/drain |
| CN102376577A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating damage to etching barrier layer and method for implementing stress memory technology |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107302000A (en) * | 2016-04-14 | 2017-10-27 | 中芯国际集成电路制造(上海)有限公司 | Sram memory and forming method thereof |
| CN107302000B (en) * | 2016-04-14 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | SRAM memory and forming method thereof |
| CN112103332A (en) * | 2020-11-09 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Static random access memory and manufacturing method thereof |
| CN116437657A (en) * | 2023-06-14 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Method for preparing static random access memory unit |
| CN116437657B (en) * | 2023-06-14 | 2023-09-08 | 合肥晶合集成电路股份有限公司 | Method for preparing static random access memory unit |
| CN116631472A (en) * | 2023-07-18 | 2023-08-22 | 全芯智造技术有限公司 | Semiconductor device, method for manufacturing the same, and method for optimizing parameters |
| CN116631472B (en) * | 2023-07-18 | 2023-10-20 | 全芯智造技术有限公司 | Semiconductor device, method for manufacturing the same, and method for optimizing parameters |
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