CN102801921A - Bayonet camera - Google Patents
Bayonet camera Download PDFInfo
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- CN102801921A CN102801921A CN2012102920593A CN201210292059A CN102801921A CN 102801921 A CN102801921 A CN 102801921A CN 2012102920593 A CN2012102920593 A CN 2012102920593A CN 201210292059 A CN201210292059 A CN 201210292059A CN 102801921 A CN102801921 A CN 102801921A
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Abstract
The invention provides a bayonet camera which comprises a rectifier unit, a synchronous control unit and a sensitization control unit, wherein the rectifier unit is used for generating a power frequency square wave according to an electric supply alternating current; the synchronous control unit is used for generating a synchronous control signal in a power frequency square wave period needing to generate the synchronous control signal, wherein the rising edge of the synchronous control signal is less than the rising edge in the power frequency square wave period by one preset time difference; and the sensitization control unit is used for generating a sensitization device time sequence control signal according to the synchronous control signal output by the synchronous control unit and outputting the sensitization device time sequence control signal to a sensitization device. Compared with the prior art, the bayonet camera has the advantages that a phaselocked loop frequency multiplier circuit is avoided, possible synchronization of a power frequency alternating current time domain and a bayonet direct current clock domain is realized inside an FPGA (Field Programmable Gate Array), a veneer circuit is simple in design; the step length is more accurately regulated in an exposure time point and has the order of magnitude of reaching an ns level.
Description
Technical field
The present invention relates to security and guard technology, relate in particular to and a kind ofly can simply efficiently carry out the synchronous bayonet socket video camera of power frequency.
Background technology
Traffic block port adopts technology such as advanced photoelectricity, computer, image processing, pattern recognition, remote data access usually, and car lane, the bicycle lane of monitoring the highway section carried out all-weather real-time monitoring and record associated picture data.Front-end processing system is analyzed captured image, therefrom obtains the data such as the time of passing through, place, travel direction, brand number, number plate color, body color of vehicle automatically.And the information that gets access to is transferred to through computer network in the database of bayonet system control centre and carries out storage, inquiry, handle than equity; When finding hit-and-run, violation or suspect vehicle, system can send alarm signal from trend intercepting system and related personnel.The bayonet socket video camera has progressively obtained popularization at intelligent transportation field now.The bayonet socket video camera is erected at gateways such as road, building usually, to vehicle carry out passing record, traffic statistics, vehicle speed measurement, make a dash across the red light the evidence obtaining etc.
The traffic block port video camera needs to consider " power frequency is synchronous " problem when taking traffic lights.Please refer to Fig. 1, China's line voltage is expressed as: U=UmSin (2 π ft+ ψ).Wherein U is an instantaneous voltage; Um is a crest voltage; 2 π f are angular frequency, and
is first phase.The time dependent speed of angular frequency 2 π f reflection alternating current, wherein f is called power frequency, and the power frequency of China's civil power is 50Hz, and promptly the period of change of instantaneous voltage is 20ms.Please refer to Fig. 2; Under the situation of using civil power, the traffic lights light energy can be expressed as: P=|PmSin (2 π ft+ ψ) |, wherein P is a traffic lights light instantaneous energy; Pm is a traffic lights light energy peak value; The period of change of instantaneous energy is 10ms, and Fig. 1 and Fig. 2 only are principle examples, wherein show the first phase factor.
Suppose that aperture time remains unchanged, during bayonet socket video camera sampling traffic light signal picture, if the time for exposure point drops near the signal energy peak Pm, traffic lights are brighter in the image that then collects; If yet time for exposure point drop near the energy trough, traffic lights are darker in the picture, even can't identification.In actual engineering, if the time for exposure of bayonet socket video camera point is not controlled, be easy to cause continuous picture traffic lights flickering, and think that traffic lights do not work by mistake when causing easily capturing evidence obtaining.
So-called exposure power frequency its principle synchronously is: control bayonet socket video camera time for exposure point; Making this time point can follow the traffic lights light energy changes; So that each time for exposure point can both drop near the high-energy value; Preferably drop near the energy peak, make that traffic lights are the brightest in the consecutive image, and flicker is minimum.Please refer to Fig. 3, wherein showed several kinds of power frequency synchronous situation.
The power frequency synchronizer mainly comprises AC power input module, power zero-crossing detection circuit, frequency multiplication of phase locked loop module, phase-detection and signal output function module in the prior art.Please refer to the power frequency synchronizing process of Fig. 4.The main effect of AC power input module and power zero-crossing detection circuit module is the square-wave signal that the AC power frequency conversion of signals of 50Hz is become 100Hz (perhaps 50Hz); Make this square-wave signal be equivalent to a shaping circuit that makes sinusoidal signal change square-wave signal, makes high-amplitude signal step-down amplitude signal by the identification of frequency multiplication of phase locked loop module.360 times of the square-wave signal frequencys multiplication that the frequency multiplication of phase locked loop module obtains shaping, in said time for exposure of control preamble during point, adjustment time for exposure point step size precision can be controlled at (10/360) ms (square wave with 100Hz is an example) like this.Phase detecting circuit realizes in that logical device is inner, and its square wave after to frequency multiplication is counted, and count down to when setting the pairing count value of phase place, and control signal is captured in output.Thus, video camera is captured between control signal and the alternating current and can be fixed on certain phase difference, realizes that camera candid photograph power frequency is synchronous, and can realize capturing the light and shade of traffic lights through adjusting phase difference.Frequency multiplication of phase locked loop module of the prior art plays a part very key to the detection of the phase place in later stage, and its design idea is also obvious, comes with some shortcomings yet introduce the frequency multiplication of phase locked loop module:
Therefore 1) 100Hz will consider modeling scheme usually as the input of phase-locked loop, need on circuit board, increase extra analog phase-locked look circuit, complexity and cost that this will corresponding increase circuit board.Even can adopt digital phase-locked loop scheme (being difficult to find digital scheme usually), remain overhead to hardware resource.
2) phase-locked loop with 360 times of power frequency square wave frequencys multiplication after; Time for exposure point adjustment step value accounts for 1/360 of whole traffic lights energy cycle; The order of magnitude is a us level (1/360 * 10ms) on time; The frequency of phase-locked loop receives certain limitation usually in addition, so the change of time for exposure point adjustment step value receives certain limitation.
Summary of the invention
In view of this, the present invention provides a kind of bayonet socket video camera, comprises rectification unit, synchronous control unit and photosensitive control unit; Wherein,
Rectification unit is used for generating the power frequency square wave according to the civil power alternating current;
Synchronous control unit is used for producing synchronous control signal in the power frequency square-wave cycle of needs generation synchronous control signal, and wherein the rising edge of synchronous control signal is later than the preset time difference of rising edge in this power frequency square-wave cycle;
The photosensitive control unit is used for generating the sensor devices timing control signal according to the synchronous control signal of synchronous control unit output, and outputs to sensor devices.
Compared to prior art, this programme has been avoided the frequency multiplication of phase locked loop circuit, realizes the synchronous as far as possible of " industrial frequency AC clock zone " and " bayonet socket direct current clock zone " in FPGA inside, and the veneer circuit design is simple; Time for exposure point adjustment step-length is more meticulous, and its order of magnitude can reach the ns level.
Description of drawings
Fig. 1 is a line voltage change curve sketch map.
Fig. 2 is a traffic lights light energy change curve sketch map.
Fig. 3 is three kinds of exposure power frequency synchronous situation sketch mapes.
Fig. 4 realizes the synchronous process chart of power frequency in the prior art.
Fig. 5 is the building-block of logic of bayonet socket video camera in one embodiment of the present invention.
Fig. 6 is a sequential sketch map in one embodiment of the present invention.
Fig. 7 is the state diagram that produces VD in one embodiment of the present invention.
Fig. 8 is the comparison diagram of various signals on sequential in one embodiment of the present invention.
Embodiment
In bayonet socket video camera design, adopt the CCD sensor devices usually, for the CMOS sensor devices, CCD has low according to effective, and supports advantage such as overall situation exposure, and when capturing the fast running vehicle, vehicle forms images not yielding; Certainly the CMOS sensor devices also has good application in the part occasion.Below be that example is set forth synchronously to solve CCD bayonet socket exposure power frequency, the scheme that the present invention solves the prior art problem is equally applicable to adopt the bayonet socket video camera of CMOS sensor devices scheme.
Please refer to Fig. 5, in one embodiment, the present invention provides a kind of bayonet socket video camera, is used to gather the picture signal of the presumptive area that comprises traffic lights, and wherein this device comprises rectification unit, photosensitive control unit and synchronous control unit; In preferred embodiment, synchronous control unit is to adopt logical device (realizing such as FPGA), and the photosensitive control unit can be the AFE device of CCD.
Under the prerequisite that aperture time remains unchanged; Guarantee to use the not serious flicker of bayonet socket video camera of CCD sensor devices; Then need appropriate control bayonet socket time for exposure point, make this time point depend on the traffic lights light energy and change, each time for exposure point can both be dropped near the fixed energies value.As previously mentioned; The traffic lights energy variation is followed formula P=|PmSin (2 π ft+ ψ) |, f=50Hz, promptly the period of change of P is 10ms; So; Control the integral multiple (like 20ms, 30ms, 40ms, 50ms etc.) that adjacent time for exposure point differs 10ms, then each time for exposure, corresponding P was a basically identical, just can guarantee that so serious flicker does not take place consecutive image.
The bayonet socket video camera has self direct current clock zone usually; CCD and the peripheral devices of being responsible for the IMAQ image are usually operated under the DC power supply; There is the clock zone of self this direct current system inside; CCD time for exposure point is limited by this direct current clock zone, and the CCD time for exposure is according to the every integral multiple at a distance from 10ms of direct current clock zone " exposure is once.And the industrial frequency AC clock zone: the traffic lights working power is the AC power of power frequency 50Hz, can regard one as and exchange clock zone, and the variation of traffic lights light energy is limited by this interchange clock zone, and the energy variation cycle is 10ms.
Because have frequency deviation between the integral multiple of the 10ms under the bayonet socket direct current clock zone and the 10ms under the industrial frequency AC clock zone, As time goes on, As time goes on the time will produce deviation to two clock zones.The traffic lights light energy changes fully and alternating voltage changes synchronously, and the change frequency that the old friend flows voltage can be used as " canonical reference clock ", and CCD internal work clock needs to carry out synchronously to the canonical reference clock.Below introducing the present invention is how to realize this synchronizing process.
Step 10, rectification unit converts the alternating voltage of traffic lights into power frequency square wave that the cycle is 10ms through the rectification circuit of self.
Step 11, synchronous control unit is gathered the power frequency square wave, and carries out exposure simultaneous operation;
Step 12, the synchronous control unit synchronous control signal that will make public outputs to the photosensitive control unit;
Synchronous control signal after step 13, photosensitive control unit receive synchronously produces corresponding sensor devices work schedule signal;
After step 14, sensor devices receive the work schedule signal that comprises the power frequency synchronizing information, accomplish exposure according to configuration.
In this execution mode, synchronous control unit adopts FPGA to realize.Said power frequency square wave is appreciated that and is " can be used for extracting the square wave of power frequency synchronizing information ", is about to the ac sine signal and changes into the cycle and be square wave of 1/2 itself.At this moment, the power frequency square wave is complete and the variation of traffic lights light energy is synchronous, and in this execution mode, requires the level standard of this power frequency square wave to meet FPGA pin level standard, can be gathered by FPGA.
Before describing FPGA generation exposure synchronous control signal, introduce the vertical driving signal (VD signal) and the horizontal drive signals (HD signal) of photosensitive control unit (being the AFE device in this execution mode) and the output of AFE device earlier.Each CCD sensor devices usually all can supporting a AFE device, and the AFE device is used for producing CCD work schedule signal, and when CCD makes public receives CCD work schedule signal controlling, and CCD work schedule signal receives VD and HD signal controlling; Wherein CCD time for exposure point mainly receives VD signal (just aforementioned synchronous control signal) control; Do not relate to the special processing of HD signal among the present invention, this part can be with reference to existing techniques in realizing.The AFE device generally has two kinds of mode of operations: holotype and from pattern.When AFE is operated in holotype following time, VD and HD signal are to produce by AFE is inner; When AFE was operated in from pattern following time, VD and HD signal can be imported by the outside.Among the present invention; AFE is configured under pattern and works; And coexist (also being appreciated that in the same clock zone) under the reference clock with FPGA, in preferred embodiment, the work clock CLK of FPGA can be by AFE with road clock (like the crystal oscillator among Fig. 6).
Please further with reference to figure 8; CCD is after the VD rising edge produces; Usually can begin exposure through the exposure time-delay (being assumed to be time b) of a regular length; Length of exposure is assumed to be time c, and wherein time b and time c are generally the time span that configures, and the two is all fixed value before configuration does not change; Therefore confirm that exposure output time point (just producing the time point of VD rising edge) is the key point of control; Suppose that power frequency square wave rising edge is time a to the time of VD rising edge, the groundwork of FPGA is exactly how to have managed time a to make exposure synchronously and in the energy position of accord with expectation.Please refer to Fig. 8, but because time b and time c are fixed configurations, therefore will guarantee not squint with respect to the power frequency square wave between exposure region, need only when satisfying exposure at every turn, time a is constant to get final product.
Please refer to Fig. 7, among the present invention, be built-in with a timer A_cnt among the FPGA, A_cnt will count the FPGA clock cycle, and counting rule is following: at each CLK rising edge, A_cnt will do " adding 1 " perhaps " zero clearing " operation; When the CLK rising edge, if do not detect power frequency square wave rising edge, A_cnt does " adding 1 " operation; If detect power frequency square wave rising edge, A_cnt does " zero clearing " operation (just resetting); The clear operation purpose is to eliminate " industrial frequency AC clock zone " to accumulate with the deviation of " bayonet socket direct current clock zone "; If because there is not clear operation; In case small deviation takes place in each power frequency square-wave cycle; The problem of image flicker appears in these deviation accumulations serious skew of time started point that can cause making public after some cycles.In preferred embodiment, the count value of A_cnt is represented a time span, and the time step that each counting increases representative can be the cycle of a FPGA reference clock, just the Cycle Length of CLK.Because when " time a " was set, its time step was a FPGA clock cycle, i.e. the bayonet socket video camera exposure time started time step of some adjustment is a FPGA clock cycle.The clock of FPGA is provided by AFE as previously mentioned, and this clock frequency is generally between 10MHz～100MHz, so time for exposure point adjustment step-length is generally between 10ns～100ns, and the flexibility ratio of adjustment is very high.
When the CLK rising edge, if do not detect power frequency square wave rising edge, A_cnt does " adding 1 " operation as previously mentioned, and when " time a " arrived in the A_cnt timing, whether FPGA also need judge in this power frequency square-wave cycle will produce the VD pulse; If need exposure in this square-wave cycle, generate a VD pulse so, if do not need exposure in this square-wave cycle, need not generate the VD pulse so.The foundation that whether need make public mainly is the reference field synchronizing signal; Perhaps with reference to current frame per second; Such as frame per second is 25; Each 40 milliseconds just need exposure once so, are not all need make public in each power frequency square-wave cycle therefore, and FPGA can concern to confirm whether needs produce the VD signal in the current power frequency square-wave cycle according to both multiples.No matter whether need produce the VD signal; A_cnt can carry out above-mentioned " zero clearing " operation in each power frequency square-wave cycle; Please be simultaneously with reference to figure 6 and Fig. 8; Because the clear operation in each power frequency square-wave cycle, this just makes bayonet socket video camera direct current clock zone and industrial frequency AC clock zone issuable deviation in each power frequency square-wave cycle just can not accumulate, and that is to say; Time difference between each VD rising edge and the power frequency square wave rising edge, (just the time a) was all fixed, so the traffic lights that photograph tangible flicker can not take place.And because FPGA can be through setting " time a " preset value; Length such as N CLK; The numerical value of adjustment time a can make exposure begin be seated the very big zone of traffic lights light energy to finishing (time c just); Such as the peak value that covers the traffic lights energy, make the traffic lights of shooting very bright like this, can be not dim.
Suppose that FPGA does not carry out the synchronous processing of above-mentioned power frequency, if bayonet socket video camera every " 10ms integral multiple " exposure once, FPGA every " 10ms integral multiple " produces a VD pulse so; This VD pulse is reference with FPGA internal clocking CLK; If the slow 1ns of clock information that the FPGA internal clocking comprises at 1ms internal ratio power frequency square wave, behind the 1s, VD is with respect to power frequency square wave skew 1ms so; Behind the 10s, skew 10ms.Because traffic lights light energy period of change is 10ms, thus the very dark picture of a width of cloth traffic lights must appear in the 10s, thus cause the consecutive image flicker.The clock information deviation that actual FPGA internal clocking CLK and power frequency square wave comprise is less than 1ns, but can know through above-mentioned analysis, and it can not guarantee that still the bayonet socket video camera takes traffic lights for a long time and do not glimmer.As a same reason, if capture the single width picture, can not guarantee to capture that traffic lights must become clear in the picture.
When the present invention can guarantee to guarantee that the bayonet socket video camera is taken power frequency lighting apparatus such as traffic lights continuously, the lighting apparatus not serious flicker that forms images; Secondly for capturing the single width picture, perhaps a few width of cloth pictures can guarantee to avoid traffic lights light energy trough near zone, near the energy crest district of traffic lights light, so just can reduce to make a dash across the red light and fail to judge as far as possible.Compared to prior art, this programme has been avoided the frequency multiplication of phase locked loop circuit, realizes the synchronous as far as possible of " industrial frequency AC clock zone " and " bayonet socket direct current clock zone " in FPGA inside, and the veneer circuit design is simple; Time for exposure point adjustment step-length is more meticulous, and its order of magnitude can reach the ns level.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (9)
1. a bayonet socket video camera comprises rectification unit, synchronous control unit and photosensitive control unit; It is characterized in that,
Rectification unit is used for generating the power frequency square wave according to the civil power alternating current;
Synchronous control unit is used for producing synchronous control signal in the power frequency square-wave cycle of needs generation synchronous control signal, and wherein the rising edge of synchronous control signal is later than the preset time difference of rising edge in this power frequency square-wave cycle;
The photosensitive control unit is used for generating the sensor devices timing control signal according to the synchronous control signal of synchronous control unit output, and outputs to sensor devices.
2. bayonet socket video camera as claimed in claim 1 is characterized in that, wherein should be N times of Preset Time step-length the preset time difference; Said synchronous control unit is further used for when the rising edge of each power frequency square-wave cycle arrives, will presetting counter O reset; Whenever count value is added 1 then at a distance from a time step; When the count value of counter arrives N; Judge in the current power frequency square-wave cycle whether need produce synchronous control signal, if then produce synchronous control signal.
3. bayonet socket video camera as claimed in claim 2 is characterized in that, the reference clock of said synchronous control unit usability light control unit is as the reference clock of self.
4. bayonet socket video camera as claimed in claim 3 is characterized in that, said time step is said reference clock cycle.
5. bayonet socket video camera as claimed in claim 2; It is characterized in that; The cycle of said synchronous control signal be the power frequency square-wave cycle positive integer doubly, said synchronous control unit is further used for confirming whether needs generation synchronous control signal of current power frequency square-wave cycle according to the relation of the multiple between synchronous control signal cycle and the power frequency square-wave cycle.
6. bayonet socket video camera as claimed in claim 1 is characterized in that, wherein said photosensitive control unit comprises holotype and from two kinds of mode of operations of pattern, wherein the photosensitive control unit is configured to from pattern to receive the synchronous control signal of outside input.
7. bayonet socket video camera as claimed in claim 1 is characterized in that, the cycle of said power frequency square wave is 10 milliseconds.
8. bayonet socket video camera as claimed in claim 1 is characterized in that, wherein said synchronous control unit is the FPGA device.
9. bayonet socket video camera as claimed in claim 1 is characterized in that, said photosensitive control unit is the AFE device, and said sensor devices is the CCD device.
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| CN104506779A (en) * | 2014-12-24 | 2015-04-08 | 浙江宇视科技有限公司 | Traffic lamp color correcting method and image pickup equipment |
| CN109727460A (en) * | 2019-03-19 | 2019-05-07 | 浙江芯源交通电子有限公司 | Capturing system based on traffic lights |
| CN109756650A (en) * | 2018-12-19 | 2019-05-14 | 刘咏晨 | Smart city camera frame synchornization method based on network wave triggering |
| CN113409602A (en) * | 2020-03-17 | 2021-09-17 | 云南金隆伟业电子有限公司 | Variable-frequency display road traffic signal lamp |
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