CN102792419B - The technique that high temperature selective fusion engages and structure - Google Patents

The technique that high temperature selective fusion engages and structure Download PDF

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Publication number
CN102792419B
CN102792419B CN201180007649.0A CN201180007649A CN102792419B CN 102792419 B CN102792419 B CN 102792419B CN 201180007649 A CN201180007649 A CN 201180007649A CN 102792419 B CN102792419 B CN 102792419B
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silicon nitride
silicon
recess
nitride layer
wafer
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CN102792419A (en
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P.阿鲁纳萨拉姆
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Microstaq Inc
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0002—Arrangements for avoiding sticking of the flexible or moving parts
    • B81B3/001—Structures having a reduced contact area, e.g. with bumps or with a textured surface
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/036—Fusion bonding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Abstract

One prevents in MEMS devices, more particularly, prevent have in micrometer range or in the recess of less (that is being less than about 10 microns) be movably configured in joint technology during in by be engaged to immodestly non-athletic structure method.The method is included in structure aspect and chemical aspect and carries out surface preparation to silicon, with help prevent kinematic configuration (be included in high strength, high-temperature merge between joint aging time) between joint aging time in be engaged to adjacent surface.

Description

The technique that high temperature selective fusion engages and structure
Technical field
Present invention relates in general to valve and semiconductor electromechanical devices, more specifically, relate to the micro Process assembly being bonded together formed by the wafer of the semi-conducting material of such as silicon.
Background technology
To be the little and size of its feature or clearance (clearance) of entity (that is be less than about 10 microns at micrometer range or less hierarchical system to MEMS (micro electro mechanical system) (MEMS); As known, micron (micron) is the another kind of saying of micron (micrometer), and it is equal the long measure of 0.001 millimeter).These systems have electrically and mechanical component." micro Process (micro machining) " word means three-dimensional structure and the moving component of production MEMS devices usually.MEMS (micro electro mechanical system) initially uses integrated circuit (i.e. computer chip) manufacturing technology (such as chemical etching) and material (such as silicon semiconductor material) revised, with these very little mechanical devices of micro Process.Technology and the material of many more microfabrication can be used now.The application may use " MEMS devices " word, and its size meaning to comprise feature or clearance is at the device of the micro Process assembly of micrometer range or less (that is being less than about 10 microns).It should be noted, if include the assembly beyond micro Process assembly in MEMS devices, then these other assemblies can be micro Process assembly or standard size (that is larger) assembly.Similarly, the application may use " micro-valve " word, and its size meaning to have feature or clearance is at the valve of micrometer range or less (that is being less than about 10 microns), and according to definition, this valve at least local is formed by micro Process.The application may use " microvalve device " word, and it means the device including micro-valve, and this device can comprise other assemblies.It should be noted, if include the assembly beyond micro-valve in microvalve device, then these other assemblies can be micro Process assembly or standard size (that is larger) assembly.
Many MEMS devices can be made up of multiple wafers (or plate) of certain material; Before multiple wafer set is synthesized completed microelectromechanicdevices devices, this material can by micro Process to form the assembly of microelectromechanicdevices devices.Suitable MEMS (micro electro mechanical system) manufacturing technology such as can be used to manufacture this MEMS devices, and this manufacturing technology is US Patent No. 6,761,420 such as; US Patent No. 7,367,359; Klassen, E.H. wait people (1995) institute show " Silicon Fusion Bonding and Deep Reactive Ion Etching:A NewTechnology for Microstructures(silicon fusion joint and deep reactive ion etch: the new technology for micro-structure); Proc.Transducers 95 Stockholm Sweden, 556-559 page; And Petersen, K.E. wait people (in June, 1991) institute show " Surface Micromachined StructuresFabricated with Silicon Fusion Bonding(with silicon merge engage and manufacture surface micro-fabrication construct) ", Proc.Transducers 91, these disclosures are now incorporated in this by manufacturing technology disclosed in 397-399 page as a reference.
Summary of the invention
The present invention relates to a kind of prevent in MEMS devices be movably configured in joint technology during in be engaged to immodestly non-athletic structure method.The method comprises the surface preparation of silicon, in (being included in high strength, high-temperature merges between joint aging time) between the joint aging time on other surfaces, helps prevent movable structure to be engaged to adjacent surface.
Those skilled in the art, coordinates accompanying drawing and reads from hereafter detailed description of the preferred embodiment, easily can understand each aspect of the present invention.
Accompanying drawing explanation
Figure l is the non-pro rata viewgraph of cross-section of MEMS devices.
Fig. 2 is flow chart, and it illustrates the surperficial selective property of preparation and merges the method engaged.
Fig. 3 is flow chart, and it provides the step details of the method for Fig. 2.
Embodiment
First should note some used term here, such as " on ", D score, " centre ", " upwards ", " downwards ", " top ", " bottom ", " above ", " rear (back of the body) face " and " side " its for helping description the preferred embodiments of the present invention.Unless the interior literary composition discussed separately indicates or make it obvious especially, otherwise should explain these terms with reference to accompanying drawing under discussion.These terms are not intended to limit the orientation that assembly of the present invention uses.
With reference now to accompanying drawing, figure l illustrates the part of the first assembly (representing with 10 generally).Assembly 10 is a kind of MEMS devices, and it has relative to other standing parts and the part of move (actuating), such as, can see in micro-valve, micromachined transducer or micro Process optical switch.In illustrative embodiment, become assembly 10 by three of monocrystalline silicon wafer-shapeds, these three wafers comprise (as shown in Figure 1) upper wafer 12, middle wafer 14 and lower wafer 16.
Upper wafer 12 has the recess 12a be formed in its lower surface 12b.Thermal silicon dioxide layer 18 is fixed to lower surface 12b (comprising the upper surface of recess 12a).As hereafter by what explain further, silicon nitride layer 20 is deposited on the thermal silicon dioxide layer 18 in recess 12a, and silicon nitride layer 20 is preferably plasma enhanced chemical vapor deposition (PECVD).As hereafter will explained further, PECVD silicon nitride layer 20 is non-uniform Distribution in recess 12a, and because following reason, (sufficiently coarse fusion with silicon assembly to prevent Studies On Contacts of Rough Surfaces silicon assembly engages preferably to have relatively high surface roughness.In a preferred embodiment, the surface roughness of the silicon nitride layer 20 in recess 12a can be greater than 3 dust RMS).The lands of lower surface 12b is engaged to the part of the upper surface 14a of middle wafer 14 via silicon dioxide layer 18.Recess 12a is arranged to contiguous middle wafer 14.
Similarly, lower wafer 16 has the recess 16a be formed thereon in surperficial 16b.Second thermal silicon dioxide layer 22 is fixed to upper surface 16b (comprising the lower surface of recess 16a).As hereafter by what explain further, the 2nd PECVD silicon nitride layer 24 is deposited on the thermal silicon dioxide layer 22 in recess 16a.As hereafter will explained further, PECVD silicon nitride layer 24 is non-uniform Distribution in recess 16a, and because following reason, preferably be formed as that there is relatively high surface roughness (the application surface with " relatively high surface roughness " used, be defined as enough coarse surface, engage to prevent the fusion contacted between the silicon assembly of rough surface and rough surface substantially).In a preferred embodiment, the rms surface roughness of the silicon nitride layer 24 in recess 16a can be greater than 3 dusts.The lands of upper surface 16b is engaged to the part of the lower surface 14b of middle wafer 14 via the second silicon dioxide layer 22.Recess 16a is arranged to contiguous middle wafer 14.
Middle wafer 14 has standing part 14c and 14d, and these standing parts can not move relative to upper wafer 12 or lower wafer 16.Middle wafer 14 also has one or more otch 14e, and this otch of micro Process passes middle wafer 14, to be defined in the region between recess 12a and recess 16a by the moving part 14f of middle wafer 14.When above moving part 14f and moving part 14f and when the material of below (also instant heating dioxide layer 18 and be fixed to the PECVD silicon nitride layer 20 of upper wafer 12 and hot dioxide layer 22 and be fixed to the PECVD silicon nitride layer 24 of lower wafer 16) separates, moving part 14f can move relative to standing part 14c, the 14d of middle wafer 14, upper wafer 12 and lower wafer 16.(conformal) thin silicon dioxide layer 15 of each conformal is formed on moving part 14f.
During the fusion joint technology of upper wafer 12, middle wafer 14 and lower wafer 16, can apply pressure with heat to these wafers, to promote the joint forming high bond strength, technique can bring out stress in wafer.Moving part 14f can be made by the stress set up to move and to leave the plane of middle wafer 14, and the silicon nitride layer 20 of contact in the bottom of recess 12a or the silicon nitride layer 24 of contact in the bottom of recess 16a.If the silicon nitride layer in the bottom of recess 12a, 16a 20,24 and moving part 14f smooth enough, when then heating during joint technology, moving part 14f contacts the part of the bottom of recess 12a, 16a, can be formed engage at the point contacted with the bottom of recess 12a, 16a.But as mentioned above, deposition PECVD silicon nitride layer 20,24, the surface of PECVD silicon nitride layer 20,24 is made to have relatively high surface roughness, that is it is enough coarse, can not occur to merge between any point contacted with PECVD silicon nitride layer 20,24 to make moving part 14f and moving part 14f and engage (its usually require unusual light, smooth surface closely contact each other, to produce joint).
Moreover such as, may there is residual stress after joint technology, it may, such as upon engagement after high-temperature annealing step, force moving part 14f to leave the plane of middle wafer 14.After engaging, high annealing may wish to improve the bond strength between each wafer, therefore makes fluidic microelectromechanical system (MEMS) device such as can bear the internal pressure of increase.Recess 12a, 16a can allow moving part 14f to leave a little motion of plane, but do not wish moving part 14f and directly over moving part 14f and immediately below assembly between leave large clearance.This kind of example is fluidic microelectromechanical system (MEMS) device of such as micro-valve, wherein, moving part 14f and directly over and immediately below non-athletic assembly between excessive clearance can cause excessive leaking through airtight valve.
In order to prevent excessive clearance, during architectural component 10, a kind of preferred constructing method is etched recess portion 16a deeply in dark etched recess portion 12a and lower wafer 16 upper wafer 12 in, then recess 12a, l6a is filled with its respective silicon dioxide layer 18,22, then PECVD silicon nitride layer 20,24 is set up, to produce the clearance expected between moving part 14f.
But because relatively little clearance, so engage at assembly 10 and to anneal and after cool, the residual stress in assembly 10 can stay and make moving part 14f contact PECVD silicon nitride layer 20,24.But the upper and lower surface of moving part 14f is smooth in a preferred embodiment; and coarse PECVD silicon nitride layer 20,24 is relatively hard and resistance to wear, usually can ride in swimmingly on the height point of coarse PECVD silicon nitride layer 20,24 to make moving part 14f.Moving part 14f and these high point cantact, and almost there is no resistance to sliding.
Hereinafter with reference Fig. 2 and Fig. 3 describes the method for optimizing according to closing for selective blending splice grafting, prepares the surface of wafer 12,14,16 and forms the general step of assembly 10.Provide various temperature, time durations etc. in following description, these should be considered to the value of starting point.Apprehensible as those skilled in the art, based on the experience in special production line, may need to adjust hereafter shown for the beginning point value during temperature and time, to tackle various environmental factor and material quality etc.
In first step 101, remove the organic substance on surface.First step 101 comprises the first sub-step.First sub-step uses NH 4oH:H 2o 2: H 2o is the first clean solution of 1:4:20 (water of the ammonium hydroxide of 1 part, 4 parts of hydrogen peroxide and 20 parts), reaches about 10 minutes, to help to remove organic substance about 70 ° of C clean surfaces.Because different organic materials has different reactions for substituted solution, so should understand, can use and there is the constitutional chemistry material of other ratio and the substituted solution of in fact different chemical substances, to promote to remove organic substance.
First step 101 also comprises the second sub-step, and it uses deionization (DI) water cleaning (preferably with dumping flushing (dump rinse)) surface to reach about 10 minutes.
In second step 102, remove natural oxide from the surface of assembly 10.In the first sub-step of step 102, use the second clean solution HF:H 2o be 1: 100 second clean solution of the water of 100 parts (hydrogen fluoride of 1 part and), about 25 ° of C clean surfaces about 5 minutes, in order to removing natural oxide.Should consider to use and there is the constitutional chemistry material of other ratio and the substituted solution of in fact different chemical substances, to promote to remove natural oxide.
In the second sub-step of step 102, it uses deionization (DI) water cleaning (preferably with dumping flushing (dump rinse)) surface to reach about 10 minutes.
In the 3rd sub-step of step 102, these surfaces are immersed in fresh isopropyl alcohol (IPA) and reach about 5 minutes.
In the 4th sub-step of step 102, make these dry tack frees reach about 15 minutes in room temperature, or make assembly 10 reach about 6 minutes in the furnace dried of about 56 ° of C.
In third step 103, oxide skin(coating) 15,18,22 is formed on a surface of the wafer, to promote the joint during merging joint technology after a while.The type of oxide skin(coating) to be formed depends on the type of the wafer that this oxide skin(coating) is formed thereon.With regard to cover piece wafer (upper wafer 12 and lower wafer 16), use the thermal silicon dioxide layer 18,22 of general 2000 to 3000 dusts of oxidation furnace (not shown) growth thickness.With regard to middle wafer 14 (it is naked silicon wafer), use nitric acid (HNO 3) growth conformal thin silicon dioxide layer 15, with the formation of accelerating oxidation thing individual layer (monolayer).The thin silicon dioxide layer 15 of conformal can be considered to oxide mono usually
Third step 103 will first describe the process of middle wafer 14: in the first sub-step of third step 103, applies the nitric acid (HNO of about 70 ° of C to about 110 ° of C 3) reach about 15 minutes, to promote the oxide of moisture chemical substance, the thin silicon dioxide layer 15 of conformal.
In the second sub-step of step 103, deionization (DI) water cleaning (preferably with dumping flushing (dump rinse)) surface is used to reach about 10 minutes.
In the 3rd sub-step of step 103, these surfaces are immersed in fresh isopropyl alcohol (IPA) and reach about 5 minutes.
In the 4th sub-step of step 103, make the dry tack free of wafer 14 reach about 15 minutes in room temperature, or make assembly 10 reach about 6 minutes in the furnace dried of about 56 ° of C.
Below, about the process of cover piece layer 12,16, third step 103 is only included in growth (possible thickness 2000 to 3000 dust) thermal silicon dioxide layer 18,22 in oxidation furnace.Thermal silicon dioxide layer 18,22 grows the upper surface 16b of lower surface 12b at upper wafer 12 and lower wafer 16 respectively.
Attention: and not all step all needs whole parts of assembly 10.Middle wafer 14 (being called mechanical wafer, because moving part 14f is formed in middle wafer 14) formed by naked silicon wafer (before fusion engages generation, it does not have oxide skin(coating) on the surface).About naked silicon wafer (such as middle wafer 14), perform first step 101, second step 102 and third step 103, to prepare the joint interface surface of wafer for merging joint.
But, only need to perform first step 101 and third step 103, just the silicon wafer surface of oxidation can be prepared for merging joint (such as found on the surface at the joint interface of upper wafer 12 and lower wafer 16, particularly to go up the lower surface 12b of the wafer 12 and upper surface 16b of lower wafer 16).
Also oxygen plasma can be used to promote the hydrophily of wafer surface.But use the toolroom of oxygen plasma not pollute completely.
In the 4th step 104, wafer 12 and lower wafer 16 in process, to produce optionally engaging zones.
Fig. 3 is the 4th step of observing in more detail shown in Fig. 2.The shadow mask used in sub-step 104A, usually produces the shadow mask (shadow mask) that can re-use at the initial stage of actual process, because may use in advance when manufacturing other assembly 10.Suppose previously to have produced suitable shadow mask, then the first sub-step 104B of step 104 can comprise the upper wafer 12 of aligning and corresponding first shadow mask and guarantee that they are under this condition of aiming at; And aligning lower wafer 16 and corresponding second shadow mask can be comprised further and guarantee that they are under this condition of aiming at.Preferred method uses fixture (fixture) to aim at shadow mask and wafer 12,16, and use fixture (clamp) shadow mask to be fixed to silicon wafer 12,16.Certainly can in advance by silicon wafer 12,16 micro Process with morphogenesis characters, such as recess 12a, 16a.In another embodiment, shadow mask attachment method can comprise use mechanical fastening system or fixture, utilizes photoresist as adhesive layer, utilize heat lag band (thermally retardant tape) etc.
Notice that each shadow mask is made up of 8 inch silicon wafer in a preferred embodiment, its size is preferably identical with upper wafer 12 and lower wafer 16, so that aim at.But the size of shadow mask, upper wafer 12 and lower wafer 16 can be made into other situation.In fact, as the advanced situation of laboratory technique, preference may change.Moreover, although the disclosure only discusses an assembly 10, should be appreciated that, preferably can by the assembly of each wafer 12,14,16 manufacture for multiple assembly 10.Shadow mask preferably becomes perforation with laser or chemical etching through-silicon or metal and makes.
Preferably apply shadow mask in advance with PECVD silicon nitride, engage during aiming to avoid cover piece wafer and shadow mask wafer.PECVD silicon nitride coating thickness on shadow mask, is preferably at 500 dusts (50 nanometer) in the scope of 1000 dusts (100 nanometer).Also such as can produce shadow mask by low-pressure chemical vapor deposition (LPCVD) nitride wafers, this wafer is own by hexamethyldisiloxane (HMDS) furnaceman skill.
In fig. 2, the second sub-step of step 104 is the non-shaded areas on the surface of process cover piece wafer 12,16, is engaged to processed surface to prevent from merging.Any applicable process can be utilized.Compared to silica surface, such as silicon nitride is more difficult surface of merging joint for silicon component (the moving part 14f of such as middle wafer 14); And therefore compared to silica surface, silicon nitride surface can be considered to anti-cement.Therefore, apply silicon nitride to non-shaded areas, can be considered to process non-shaded areas to prevent from engaging.The hereafter another kind of process of more detailed description, it can make non-shaded areas enough coarse, engages to prevent from merging.
In the 3rd sub-step 104C of the 4th step 104, setting up silicon dioxide layer 18 or 22 and after shadow mask is relative to cover piece wafer 12,16 stationary positioned, the part of silicon dioxide layer 18 or 22 in recess 12a or 16a of this cover piece wafer 12 or 16, can by intentionally roughening and be used as a kind of process, to reduce the possibility merging joint inside recess 12a or 16a respectively.Preferably through etching (such as passing through the dry-etching method based on radio frequency (RF) or reactive ion etching), make silicon dioxide layer 18 or 22 roughening.
Sub-step 104D shown in Fig. 3 is deposition sub-step, it comprise cover piece wafer (upper wafer 12 and lower wafer 16) and relevant aligning and fixing shadow mask inserted PECVD nitride instrument (technological temperature is about 300 ° of C-350 ° of C) interior and on the surface of non-crested (that is in recess 12a, 16a) deposit PECVD silicon nitride.Typical nitride target thickness is 2000 dust-3000 dusts.Deposition PECVD silicon nitride preferably changes as follows with the speed forming silicon nitride layer 20,24: time initial, in sub-step 104D, the speed of deposition should be that relatively low deposition rate (is per minutely less than about 25 dusts, and be preferably per minutely less than 20 dusts), to obtain the thin of non-shaded areas but coating complete substantially.In the second deposition step (sub-step 104E), relatively fast deposition rate is preferably utilized (to be per minutely more than or equal to about 25 dusts, and be preferably about 50 dusts per minute), complete PECVD silicon nitride layer 20,24 and be deposited in recess 12a, 16a.Use this relatively fast deposition rate, to obtain the versus rough surfaces on the result nitride layer 20,24 in non-shaded areas.The change deposition rate of silicon nitride layer 20,24, can obtain the surface roughness of good covering on silicon nitride layer 20,24 and change.The thickness of silicon nitride layer 20,24 is determined by final required hole clearance required between required sandwich structure (that is between mobile component 14f of the surface of silicon nitride layer 20,24 and adjacent middle wafer 14).As mentioned above, when heated chip 12,14,16 is bonded together to be merged by these wafers, if this assembly contacts with this rough surface, the value of roughness is enough to prevent from merging with silicon assembly (the moving part 14f of such as middle wafer 14) engaging.In a preferred embodiment, the rms surface roughness of the silicon nitride layer 20,24 in each recess 12a, 16a can be greater than 3 dusts.In addition, preferably by uneven distribution patterns deposited silicon nitride layer 20,24.Hole clearance needed for this pattern should obtain at the thick of silicon nitride layer 20,24.But uneven distribution patterns should cause silicon nitride layer 20,24 thinner at the thick place away from silicon nitride layer 20,24, to make the minimise friction between the moving part 14f of middle wafer 14 and silicon nitride layer 20,24.As shown in Figure 1, in one embodiment, silicon nitride layer 20,24 is roughly thicker at the middle body of recess 12a, 16a, and thinner in other places.
When the degree of depth of recess 12a, 16a removes the combination thickness of (deducting) silicon nitride layer 20,24 and oxide skin(coating) (silicon dioxide layer 18,22) and provides required hole clearance, stop deposition PECVD silicon nitride.When adjacent component be arranged on recess 12a, 16a upper and support by the lands of the silicon face (12b, 16b) of formation recess 12a, 16a of wafer 12,16 time, hole clearance is the clearance from silicon nitride layer 20,24 to adjacent component (such as middle wafer 14, particularly moving part 14f).
In the last sub-step 104F of step 104: after deposition step (the sub-step 104D of step 104,104E), remove shadow mask from cover piece wafer (wafer 12,16).Preferably before splicing, should clean wafer 12,14,16, such as with deionization (DI) water in spin washer dryer or other suitable methods clean.
After completing steps 104, with suitable order and azimuth configuration wafer 12,14,16, and heat these wafers and make it be under pressure, merge to make this wafer and be bonded together, and this joint occurs in the silicon dioxide layer 18,22 and middle wafer contact position set up in third step 103, and each silicon nitride layer 20,24 place be plugged between silicon dioxide layer 18,22 and middle wafer 14 does not engage, particularly when silicon nitride layer 20,24 has relatively high surface roughness.
Total, all surfaces that Fig. 1 shows the MEMS devices combined by multi-wafer forms, and these wafers of construction are used for optionally merging joint during manufacture MEMS devices.MEMS devices comprises the first silicon wafer of general planar, and it has the silicon dioxide layer be formed thereon.The silicon dioxide layer of part has the silicon nitride layer be deposited thereon.MEMS devices comprises the second silicon wafer of general planar in addition.This second silicon wafer of micro Process is to form moving part and standing part; This standing part is engaged to the silicon dioxide layer of the first silicon wafer; This moving part can move relative to standing part, and is arranged at contiguous silicon nitride layer, makes perpendicular to the first and second wafers and by the line of moving part, also can pass through silicon nitride layer.Fig. 2 and Fig. 3 illustrates the technique obtaining the structure shown in Fig. 1.First the adjacently situated surfaces of clean wafer 12,14,16, particularly removes organic substance.Then, natural oxide is removed from the adjacently situated surfaces of wafer 12,14,16.Then, in (being included in recess 12a, 16a) formation oxide skin(coating) (preferably thermal silicon dioxide layer 18,22) on the surface of middle wafer 14 of wafer 12,16.Then, the etch process of such as reactive ion etching or the dry-etching method based on radio frequency can be used, make the silicon dioxide layer roughening in recess 12a, 16a.Then, utilize reusable shadow mask to cover the region not needing to apply coarse silicon nitride, PECVD silicon nitride layer 20,24 is deposited on silicon cover piece wafer recess 12a, 16a, keep to make the region of crested adapting to merge engaging.
Preferably, time initial, with low deposition rate, PECVD silicon nitride layer 20,24 deposition is entered in recess 12a, 16a.In sub-step 104D, preferably use final high deposition rate, complete and PECVD silicon nitride layer 20,24 deposition is entered in recess 12a, 16a.The change deposition rate of silicon nitride layer 20,24, rugosity is rented on the surface that can obtain good covering on silicon nitride layer 20,24 and change.
The thickness of silicon nitride layer 20,24 is determined by final hole clearance required between sandwich structure (that is between mobile component 14f of the surface of silicon nitride layer 20,24 and adjacent middle wafer 14).When completing the process of non-shaded areas, final sub-step 104E comprises and removes shadow mask from wafer surface.Preferably before splicing, should clean wafer 12,14,16, such as with deionization (D1) water in spin washer dryer or other suitable methods clean.
Once be put together by wafer 12,14,16 for merging joint, the chemical property of silicon nitride layer 20,24 and the surface roughness of silicon nitride layer 20,24 can suppress middle wafer 14 to be engaged to cover piece wafer (upper wafer 12, lower wafer 16).In addition as shown in Figure 1, preferably by uneven distribution patterns deposited silicon nitride layer 20,24, the gross thickness of silicon nitride layer 20,24 (that is ignoring the change that surface roughness causes) is changed along with diverse location.Hole clearance needed for this pattern should obtain at the thick of silicon nitride layer 20,24.But distribution patterns should cause silicon nitride layer 20,24 thinner at the thick place away from silicon nitride layer 20,24, to make the minimise friction between the moving part 14f of middle wafer 14 and silicon nitride layer 20,24.Then, after fusion engages, wafer can be annealed safely (such as in the temperature of 1000 ° of below C for high bond strength), and the own treatment surface deterioration contributing to engaging middle wafer 14 can not be made.In testing, successfully implement this technique, to obtain the hole clearance from 2000 dusts (200 nanometer) to 2 microns.
The optionally fusion that the innovative combination of above-mentioned technique can allow implementer not only obtain relative smooth wafer engages, and the selective blending splice grafting obtaining the wafer of the feature with relatively high and even uneven depth-to-width ratio (aspect ratio) closes.Believe that the technique of such as institute's teaching above allows the surface of the wafer forming MEMS devices parts to engage, in this surface, oneself etching has the recess of the varying depth of relatively dark (being greater than 2 microns); These techniques have been used to merge joint wafer, and these wafers are combined into MEMS devices, by the various cavity depth of etching in these wafers, such as, comprise the recess of recess to 150 micron dimension with the 2 micron dimension degree of depth.In typical wet chemical etching technique, must revolve turn coating photoresist over the entire surface of the wafer protective layer, be exposed to light to make patterning photoresist, by development of photoresist to remove photoresist in not protected region, etch not protected region, then to remove remaining photoresist.On the whole wafer of many etch configuration with different form ratios (aspect ratio), rotary coating photoresist is very difficult equably.Namely allow to this rotary coating (its be still leave a question open), also must implement many steps to etch each wafer.By contrast, innovative technology as described herein uses hard mask (shadow mask), to protect not by the region of etching roughening.The smooth surface be separated forming mask and wafer to be etched and mask is mechanically aimed at, is relatively flat-footed technique, easier than painting photoresist on the whole wafer of multiple etching structure with different form ratios.In addition, shadow mask is reusable on multiple wafer, and must difficulty not apply to sacrifice photoresist protective layer to guide the etching of each wafer to be etched.
Oneself illustrates and illustrates principle and the pattern of operation of the present invention in a preferred embodiment.But, must understand, the present invention can be implemented by other modes beyond clearly stating and illustrating, and can not the spirit and scope of the present invention be departed from.

Claims (22)

1., for the preparation of the method on surface optionally merging joint, comprising:
A) alignment surface and shadow mask, to produce the crested region on this surface and non-shaded areas;
B) process this non-shaded areas on this surface, engage to prevent from merging; And
C) in step b) in process after, remove this shadow mask from this surface,
Wherein
This surface is silicon face; And
Step b) be included in this silicon face this non-shaded areas on deposited silicon nitride layer.
2. the method for claim 1, wherein this silicon face is silicon dioxide layer, and wherein in step b) before, deliberately make this silicon dioxide layer roughening.
3. method as claimed in claim 2, wherein uses one of radio frequency etching and reactive ion etching, by this silicon dioxide layer roughening.
4. the method for claim 1, wherein in step b) in, initially apply silicon nitride with the first deposition rate, then apply silicon nitride with the second deposition rate being greater than this first deposition rate.
5. method as claimed in claim 4, wherein this first deposition rate is for being less than 25 dusts per minute.
6. method as claimed in claim 4, wherein this second deposition rate is for being equal to or greater than 25 dusts per minute.
7. the method for claim 1, wherein uses plasma enhanced chemical vapor deposition (PECVD) to apply silicon nitride.
8. the method for claim 1, wherein in step b) in, deposited silicon nitride unevenly, changes along with the diverse location in the region of this silicon nitride of deposition to make the gross thickness of this silicon nitride layer.
9. method as claimed in claim 8, wherein deposits this silicon nitride to form this silicon nitride layer, make this silicon nitride layer thicker in the middle body of recess, and other places is thinner.
10. the method for claim 1, in the preliminary step wherein before step a), removes natural oxide.
11. methods as claimed in claim 10, wherein
After this preliminary step and before step a), this silicon face forms oxide skin(coating).
12. methods as claimed in claim 11, wherein in step b) before, make this oxide skin(coating) roughening.
13. the method for claim 1, wherein before step a), in this surface, form recess, this non-shaded portions on this surface is arranged in this recess.
14. methods as claimed in claim 13, wherein before step a), in this recess, are included in going up at least partially of this non-shaded areas, form oxide skin(coating).
15. methods as claimed in claim 14, wherein
This surface is silicon face;
Step b) be included in this silicon face in this recess this non-shaded areas on deposited silicon nitride layer; And
When the degree of depth of this recess deducts in step b) in the combination thickness of this silicon nitride layer of being formed and this oxide skin(coating) when being provided to the required clearance of adjacent component, terminate in step b) in deposited silicon nitride, this clearance be when this adjacent component to be arranged on this recess and support by the lands of this silicon face time clearance.
16. the method for claim 1, wherein
Recess is formed in this surface, and this non-shaded portions on this surface is arranged in this recess;
Step b) be included in this surface in this recess this non-shaded areas on deposited silicon nitride layer; And
When the degree of depth of this recess deducts in step b) in the thickness of this silicon nitride layer that formed when being provided to the required clearance of adjacent component, terminate in step b) in deposited silicon nitride, this clearance be when this adjacent component to be arranged on this recess and support by the lands on this surface time clearance.
17. 1 kinds of MEMS devices, comprising:
The first smooth silicon wafer, has the silicon dioxide layer be formed thereon, and a part for this silicon dioxide layer has the silicon nitride layer be deposited thereon; And
The second smooth silicon wafer, by micro Process to form moving part and standing part, this standing part is engaged to this silicon dioxide layer of this first silicon wafer, this moving part can be configured to adjacent to this silicon nitride layer relative to the motion of this standing part, to make perpendicular to this first silicon wafer and this second silicon wafer and also can by this silicon nitride layer by the line of this moving part.
18. MEMS devices as claimed in claim 17, wherein this silicon nitride layer is arranged in recess, and this recess is formed in the surface of this first silicon wafer, and this standing part of this second silicon wafer is engaged to the non-sunk part on this surface.
19. MEMS devices as claimed in claim 17, wherein this silicon nitride layer has relatively high surface roughness, thus the surface of this silicon nitride layer is sufficiently coarse to prevent the fusion contacted between the silicon assembly of rough surface and this surface from engaging.
20. MEMS devices as claimed in claim 19, wherein this silicon nitride layer has the rms surface roughness more than 3 dusts.
21. MEMS devices as claimed in claim 17, wherein the gross thickness of this silicon nitride layer changes along with the diverse location in the region of nitride deposition.
22. MEMS devices as claimed in claim 18, wherein this silicon nitride layer is thicker at the middle body of this recess, and thinner in other parts.
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