CN102792410A - Chip fuse - Google Patents
Chip fuse Download PDFInfo
- Publication number
- CN102792410A CN102792410A CN2011800127789A CN201180012778A CN102792410A CN 102792410 A CN102792410 A CN 102792410A CN 2011800127789 A CN2011800127789 A CN 2011800127789A CN 201180012778 A CN201180012778 A CN 201180012778A CN 102792410 A CN102792410 A CN 102792410A
- Authority
- CN
- China
- Prior art keywords
- plating layer
- plating
- fuse
- substrate
- chip fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/0411—Miniature fuses
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C19/00—Alloys based on nickel or cobalt
- C22C19/03—Alloys based on nickel or cobalt based on nickel
-
- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C19/00—Alloys based on nickel or cobalt
- C22C19/03—Alloys based on nickel or cobalt based on nickel
- C22C19/05—Alloys based on nickel or cobalt based on nickel with chromium
- C22C19/058—Alloys based on nickel or cobalt based on nickel with chromium without Mo and W
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/48—After-treatment of electroplated surfaces
- C25D5/50—After-treatment of electroplated surfaces by heat-treatment
- C25D5/505—After-treatment of electroplated surfaces by heat-treatment of electroplated tin coatings, e.g. by melting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/046—Fuses formed as printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/05—Component parts thereof
- H01H85/055—Fusible members
- H01H85/06—Fusible members characterised by the fusible material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
- H01H85/02—Details
- H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
- H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
- H01H85/0411—Miniature fuses
- H01H2085/0414—Surface mounted fuses
Abstract
Provided is a chip fuse which includes a fuse element that can be fused at a low temperature without fail. Surface electrodes are formed on a surface of an insulating substrate (1), and an Ni-P-Fe layer (15) is formed by plating so as to overlap the surface electrodes (3). An Sn layer (17) is formed by plating on the Ni-P-Fe layer (15). The Sn layer (17) is coated with an overcoat constituted of an insulating resin material.
Description
Technical field
The present invention relates to chip fuse.
Background technology
Special public clear 55-5847 communique (patent documentation 1) and spy open the existing example that flat 7-122406 communique (patent documentation 2) discloses the chip fuse that on insulated substrate, passes through the deposited Ni-P-Fe of formation of electroless plating film.
The prior art document
Patent documentation
Patent documentation 1: special public clear 55-5847 communique
Patent documentation 2: the spy opens flat 7-122406 communique
Summary of the invention
The problem that the present invention will solve
The melt temperature of Ni-P-Fe film is about 800 ℃～1000 ℃, very high temperature.Therefore, in the circuit protecting element of patent documentation 1 record, there is the problem that is difficult to set the fuse blows condition in the little current value Ni-P-Fe film (fuse element) that can not fuse.In addition, the circuit protecting element of record in the patent documentation 2, through in the Ni-P-Fe film, adding the tungsten or the molybdenum of trace, the stress of plating epithelium raises, and easy generation of plating epithelium broken.But, when adopting the circuit protecting element of patent documentation 2,, Ni-P-Fe film (fuse element) do not introduce the situation of necessary abundant fracture when taking place, and the problem that then exists is the not fracture positively of Ni-P-Fe film.
The purpose of this invention is to provide: in the chip fuse that adopts the Ni-P-Fe plating layer, than the existing chip fuse of fusing more really.
Other purpose of the present invention provides: in the chip fuse that adopts the Ni-P-Fe plating layer, use the chip fuse with the fuse element that fuses than existing little electric current.
Be used to solve the means of problem
Chip fuse of the present invention has: insulated substrate, a pair of surface electrode, Ni-P-Fe plating layer, Sn plating layer and the external coating that form at the two ends of the substrate surface of insulated substrate.The Ni-P-Fe plating layer forms through the electroless plating method of applying on substrate surface with the mode of crossing between a pair of surface electrode.The tin plating layer is on the Ni-P-Fe plating layer, to adopt electrolysis plating method to form.In the present invention, constitute fuse element through Ni-P-Fe plating layer and Sn plating layer.The Ni-P-Fe plating layer, for enabling to fuse separately, essential heating is to quite high temperature.At this, in the present invention,, utilize the fusing-off temperature ratio of the fuse element of Ni-P-Fe plating layer to have now lower through on the Ni-P-Fe plating layer, forming the Sn plating layer.The principle that fusing-off temperature reduces imperfectly understands, and can infer; The Ni-P-Fe plating layer is because resistance value is than Sn plating floor height, so the temperature of Ni-P-Fe plating layer raises; The heat that in the Ni-P-Fe plating layer, takes place makes Sn plating layer generation fusion at first, fusion the Sn plating layer; Through with the Ni-P-Fe plating layer in Ni and Fe contact, particularly contact the about 500 ℃ alloy of formation fusing point through Fe and Sn.Thus, can make separately in the just fusing-off temperature of the Ni-P-Fe plating layer of fusion reduction more than 1000 ℃.External coating is formed by dielectric resin material such as epoxy, silicone lining Sn plating layer.
Concrete is, the thickness of Ni-P-Fe plating layer is 0.4～0.8 μ m, and the thickness of Sn plating layer is 1.0～5.0 μ m, and the Ni-P-Fe plating layer is that the composition of Ni is preferred with Fe:11～13 weight %, P:7～13 weight %, surplus.
When adopting such formation; For example; The chip fuse of 1005 sizes of rated current 0.35A, maximum internal resistance 650m Ω, rated voltage 24VDC, breaking current 35A, length 1.0mm, width 0.5mm, fusing performance are that 200% and fusing time of rated current is in 5 seconds.Should be pointed out that chip fuse of the present invention, be not limited to above-mentioned specification, for example, resistance value scope 300～1000m Ω, rated current 0.3～0.5A, rated voltage 24VCD, breaking current are 35A.Should be pointed out that the size of chip fuse, can be 1608 sizes of length 1.6mm, width 0.8mm.
Description of drawings
Fig. 1 is the sectional drawing of the chip fuse of embodiment of the present invention.
Embodiment
Below, with reference to accompanying drawing, embodiment of the present invention are explained.Fig. 1 is the sectional drawing of one of embodiment of chip fuse of the present invention example.Should be pointed out that the gauge of each several part is all drawn large among Fig. 1 for ease of understanding.As shown in Figure 1, this chip fuse 20 has approximate rectangular insulated substrate 1.In this embodiment, the insulated substrate 1 of shaped like chips is formed by aluminium base (ceramic substrate).
On the substrate surface 1a of insulated substrate 1, adopt that the mixing Ag of going into sticks with paste with the formed Ag-Pd glaze that contains of the powder of Pd in the glass paste, along insulated substrate 1 vertically, formation width dimensions a pair of surface electrode 3,3 about equally.In this example, adopt to contain Ag-Pd glaze paste, form the surface electrode 3,3 of the about 8 μ m of thickness through silk screen printing.The sintering temperature that contains Ag-Pd glaze paste is about 850 ℃.
On the substrate back 1b of insulated substrate 1, adopt to contain the Ag glaze and stick with paste, along insulated substrate 1 vertically, form width dimensions a pair of surface electrode 5,5 about equally.The inside electrode 5,5 adopts silk screen printing to form, and thickness is identical with surface electrode, is about 8 μ m.The sintering temperature that contains Ag glaze paste is about 850 ℃.
Side electrode the 7, the 7th, a part and the part of backplate 5,5 of lining surface electrode 3,3, and cross over surface electrode 3,3 and backplate 5,5 and form.Consequently, vertical both ends of the surface 1c of insulated substrate 1 is also by side electrode 7,7 linings.Side electrode 7,7 adopts the nickel-chromium alloy film of nickeliferous-evanohm and copper film to form.This film adopts sputtering method to form.But also available Ag resin paste (about 200 ℃ of sintering) forms side electrode 7,7.
Side electrode 7,7, as shown in Figure 1, the part of the part of surface electrode 3,3 and backplate 5, the 5 nickel plating layer (inner plating) 9 that all is covered.Therefore, nickel plating layer 9 all is covered by Sn plating layer 11 (outside plating).
Formed the plating layer 15 that comprises Ni-P-Fe on the substrate surface 1a.Ni-P-Fe has high bonding property.Therefore, when using Ni-P-Fe, can obtain the high chip fuse of paired pulses property as fuse element.The plating layer 15 that comprises Ni-P-Fe adopts electroless plating to apply the thickness that method forms 0.4～0.8 μ m.In the present embodiment, the composition of Ni-P-Fe: Fe:11～13 weight %, P:7～13 weight %, surplus are Ni.Should be pointed out that the thickness and the composition of Ni-P-Fe plating layer 15, be not limited to these, when the ratio of components of Fe was high, it is big that resistance value becomes, and simultaneously, the plating epithelium becomes and is easy to oxidation.When the oxidation of plating epithelium, the mask closing force of subsequent processing worsens, and then is accompanied by the instabilityization of Sn tunicle, produces mask and peels off inadequate problem.In addition, when the ratio of components of Fe hangs down, can not get sufficient operating chacteristics.Therefore, the ratio of components of Fe and resistance value must transfer to suitable scope.The plating layer 15 that comprises Ni-P-Fe after the employing electroless plating method of applying forms, is heat-treated in 270 ℃～310 ℃.
On Ni-P-Fe plating layer 15, form the plating layer 17 that comprises Sn.Sn plating layer 17 adopts electrolysis plating method to form the thickness of 1.0～2.0 μ m.Should be pointed out that before forming Sn plating layer 17, it is preferred forming masking film on the marginal portion of chip fuse Unit 20.Through mask, can prevent to produce on the marginal portion Sn tunicle.When the marginal portion produces the Sn tunicle, then on conductor, adhere to Sn.Therefore, when adverse current, break off conductor.Through applying mask, can prevent its disconnection.
In the present invention, the plating layer 15 by Ni-P-Fe constitutes fuse element 18 with Sn plating layer 17.When at surface electrode 3, when applying voltage between 3, at Ni-P-Fe plating layer 15 and Sn plating layer 17 both inflow currents.Ni-P-Fe plating layer 15 for carrying out fusion individually, must reach 1000 ℃.Ni-P-Fe plating layer 15, resistance value are than Sn plating layer 17 height, so the temperature of Ni-P-Fe plating layer 15 raises, the heat that takes place in the Ni-P-Fe plating layer 15 is sent to Sn plating layer 17.Because fusion takes place at about about 230 ℃ in Sn plating layer 17, so pass through the heat generation fusion that Ni-P-Fe plating layer 15 transmits.Fusion Sn plating layer 17, when contacting with Ni-P-Fe plating layer 15, stripping takes place in Ni and Fe.Particularly can infer,, can form the about 500 ℃ alloy of fusing point through mixing of Fe and Sn.Therefore, in this embodiment, separately just in the Ni-P-Fe of 1000 ℃ of fusions plating layer 15, at about 500 ℃ fusion takes place.Therefore, the fuse element 18 of this embodiment fuses at about 500 ℃.
Particularly in this embodiment, the thickness of Ni-P-Fe plating layer 15 is 0.4～0.8 μ m, and the thickness of Sn plating layer 17 is 1.0～5.0 μ m.In addition, the consist of Fe:11～13 weight %, P:7～13 weight %, surplus of Ni-P-Fe plating layer 15 are Ni.Therefore; When the chip fuse of this embodiment is 1005 sizes of rated current 0.35A, maximum internal resistance 650m Ω, rated voltage 24VDC, breaking current 35A, length 1.0mm, width 0.5mm; Fusing performance is a rated current 200%, and fusing time is in 5 seconds.Should be pointed out that chip fuse of the present invention, be not limited to above-mentioned specification, for example, can be: resistance value scope 300～1000m Ω, rated current 0.3～0.5A, rated voltage 24VDC, breaking current 35A.In addition, the size of chip fuse also can be length 1.6mm, 1608 sizes of width 0.8mm.
On the Sn plating layer 17 that adopts electrolysis plating method to form, form external coating 19.In this embodiment, adopting sintering temperature is epoxy resin than the low dielectric resin material of heat treatment temperature that the employing electroless plating applies the Ni-P-Fe plating layer 15 of method formation, forms external coating 19.The sintering temperature of the epoxy resin that uses is about 200 ℃.External coating 19 also can carry out sintering, formation after silk screen printing.
The chip fuse 20 of above-mentioned embodiment is preferably pressed the following order manufacturing.At first, at the substrate surface of insulated substrate 1 and the two ends at the back side, form a pair of surface electrode 3,3 and a pair of backplate 5,5.Secondly, form side electrode 7,7.Once more; On a pair of surface electrode 3,3 and a pair of surface electrode 3, substrate surface between 3; For making the plating layer that adopts the electroless plating method of applying to form carry out tunicle, a pair of surface electrode on the substrate surface 3, between 3, form non-electrolysis tunicle and use substrate.Non-electrolysis tunicle is as the deposited substrate performance function of carrying out tunicle of electroless plating, to form through sintering with silk screen printing with substrate.Non-electrolysis tunicle is arbitrarily with the material of substrate, in this example, forms by sticking with paste material (ヘ °-ス of キ ヤ タ ト) as the glaze that contains Pd of conducting objects.Sticking with paste non-electrolysis tunicle that material constitutes by the glaze that contains Pd, to use the sintering temperature of substrate be about 600 ℃.Non-electrolysis tunicle is used substrate, after forming a pair of surface electrode 3,3, forms on 3,3 whole ground of surface electrode.Should be pointed out that non-electrolysis tunicle uses substrate, in the completion article of chip fuse of the present invention, on ceramic substrate, intersperse and cambium layer not with the Pd trace below the 0.1 μ m.
Secondly, a pair of surface electrode 3,3 and glaze on the substrate surface are pasted over, adopt electroless plating to apply method, form Ni-P-Fe plating layer 15.Once more, the plating layer 15 of Ni-P-Fe is heat-treated.Secondly, mask to print carries out sintering after sticking with paste.Then, on Ni-P-Fe plating layer 15, adopt electrolysis plating method, form Sn plating layer 17.Afterwards, remove mask.And, in order to obtain necessary resistance value, finely tune as required.Should be pointed out that fine setting may not be necessary.At last, adopt dielectric resin material, form the external coating 19 of lining Sn plating layer 17.And, after forming external coating 19, cross over side electrode 7,7 and surface electrode 3,3 and backplate 5,5 formation plating layers 9,11.
In this embodiment, insulated substrate is made up of ceramic substrate, and external coating is formed by epoxy resin, and priming coat uses the metal glaze that contains Pd to stick with paste, and is suitable for baseplate material, top layer material and priming coat that the present invention uses, is not limited to these materials.
Utilize possibility on the industry
According to the present invention, fuse element is positively to fuse than existing low temperature.
Symbol description
1 insulated substrate
3 surface electrodes
5 backplates
7 side electrodes
9 inner platings
11 outside platings
The 15Ni-P-Fe plating layer
The 17Sn plating layer
18 fuse elements
19 external coatings
20 chip fuses
Claims (3)
1. chip fuse, it has:
Insulated substrate,
The a pair of surface electrode that forms at the two ends of the substrate surface of above-mentioned insulated substrate,
The Ni-P-Fe plating layer that on the aforesaid substrate surface, forms with the mode of crossing between above-mentioned a pair of surface electrode,
The Sn plating layer that on above-mentioned Ni-P-Fe plating layer, forms and
The external coating that constitutes by dielectric resin material that on above-mentioned Sn plating layer, forms.
2. according to the described chip fuse of claim 1, wherein, the thickness of above-mentioned Ni-P-Fe plating layer is 0.4～0.8 μ m, and the thickness of above-mentioned Sn plating layer is 1.0～2.0 μ m.
3. according to claim 1 or 2 described chip fuses, wherein, the consist of Fe:11～13 weight %, P:7～13 weight %, surplus of above-mentioned Ni-P-Fe plating layer are Ni.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-051975 | 2010-03-09 | ||
| JP2010051975 | 2010-03-09 | ||
| PCT/JP2011/055370 WO2011111700A1 (en) | 2010-03-09 | 2011-03-08 | Chip fuse |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102792410A true CN102792410A (en) | 2012-11-21 |
| CN102792410B CN102792410B (en) | 2015-11-25 |
Family
ID=44563500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180012778.9A Active CN102792410B (en) | 2010-03-09 | 2011-03-08 | Chip fuse |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5711212B2 (en) |
| CN (1) | CN102792410B (en) |
| WO (1) | WO2011111700A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104871283A (en) * | 2012-12-28 | 2015-08-26 | 泰科电子日本合同会社 | Protective element |
| WO2021195871A1 (en) * | 2020-03-30 | 2021-10-07 | 华为技术有限公司 | Embedded substrate, circuit board assembly, and electronic device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623271B (en) * | 2012-03-31 | 2014-09-10 | Aem科技(苏州)股份有限公司 | Thin film type fuse and production method |
| WO2023090320A1 (en) * | 2021-11-16 | 2023-05-25 | 北陸電気工業株式会社 | Chip fuse |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS555847B2 (en) * | 1974-07-29 | 1980-02-12 | ||
| JPH07122406A (en) * | 1993-10-22 | 1995-05-12 | Hokuriku Electric Ind Co Ltd | Chip-shaped fuse resistor and manufacture thereof |
| JP2002279883A (en) * | 2001-03-19 | 2002-09-27 | Koa Corp | Chip type fuse resistor and manufacturing method of same |
| JP2006164639A (en) * | 2004-12-03 | 2006-06-22 | Mitsubishi Materials Corp | Chip type fuse and its manufacturing method |
| CN1848351A (en) * | 2005-02-24 | 2006-10-18 | 库帕技术公司 | Low resistance polymer matrix fuse apparatus and method |
-
2011
- 2011-03-08 CN CN201180012778.9A patent/CN102792410B/en active Active
- 2011-03-08 WO PCT/JP2011/055370 patent/WO2011111700A1/en active Application Filing
- 2011-03-08 JP JP2012504474A patent/JP5711212B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS555847B2 (en) * | 1974-07-29 | 1980-02-12 | ||
| JPH07122406A (en) * | 1993-10-22 | 1995-05-12 | Hokuriku Electric Ind Co Ltd | Chip-shaped fuse resistor and manufacture thereof |
| JP2002279883A (en) * | 2001-03-19 | 2002-09-27 | Koa Corp | Chip type fuse resistor and manufacturing method of same |
| JP2006164639A (en) * | 2004-12-03 | 2006-06-22 | Mitsubishi Materials Corp | Chip type fuse and its manufacturing method |
| CN1848351A (en) * | 2005-02-24 | 2006-10-18 | 库帕技术公司 | Low resistance polymer matrix fuse apparatus and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104871283A (en) * | 2012-12-28 | 2015-08-26 | 泰科电子日本合同会社 | Protective element |
| WO2021195871A1 (en) * | 2020-03-30 | 2021-10-07 | 华为技术有限公司 | Embedded substrate, circuit board assembly, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5711212B2 (en) | 2015-04-30 |
| CN102792410B (en) | 2015-11-25 |
| WO2011111700A1 (en) | 2011-09-15 |
| JPWO2011111700A1 (en) | 2013-06-27 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |