CN102790602A - Three-value low power consumption domino JKL trigger - Google Patents

Three-value low power consumption domino JKL trigger Download PDF

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Publication number
CN102790602A
CN102790602A CN2012102475646A CN201210247564A CN102790602A CN 102790602 A CN102790602 A CN 102790602A CN 2012102475646 A CN2012102475646 A CN 2012102475646A CN 201210247564 A CN201210247564 A CN 201210247564A CN 102790602 A CN102790602 A CN 102790602A
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nmos pipe
pipe
grid
drain electrode
source electrode
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CN102790602B (en
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汪鹏君
杨乾坤
郑雪松
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Hangzhou Maen Science & Technology Co ltd
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Ningbo University
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Abstract

The invention discloses a three-value low power consumption domino JKL trigger. The three-value low power consumption domino JKL trigger consists of a first three-value heat-insulating domino character operational circuit, a second three-value heat-insulating domino character operational circuit, a third three-value heat-insulating domino character operational circuit, a fourth three-value heat-insulating domino character operational circuit and a three-value JKL trigger basic circuit, wherein a heat-insulating logic, a multi-value logic and a domino circuit are combined together by the first three-value heat-insulating domino character operational circuit, the second three-value heat-insulating domino character operational circuit, the third three-value heat-insulating domino character operational circuit and the fourth three-value heat-insulating domino character operational circuit. The three-value low power consumption domino JKL trigger has the advantages that the circuit integration level and information density of the JKL trigger are improved; and compared with a conventional three-value domino JKL trigger, the three-value low power consumption domino JKL trigger disclosed by the invention has the characteristic that energy consumption is saved by 69 percent.

Description

A kind of three value low-power consumption domino JKL triggers
Technical field
The present invention relates to a kind of JKL trigger, especially relate to a kind of three value low-power consumption domino JKL triggers.
Background technology
Trigger is the important component part of Clock Subsystem in the sequence circuit, is widely used in adopting in the very lagre scale integrated circuit (VLSIC) of high-performance clock.Research shows that the power consumption of Clock Subsystem is about the 30-50% of circuit total power consumption, so the research of low-power consumption trigger has crucial meaning for the power consumption that reduces Clock Subsystem and the total power consumption of circuit.Adopt the adiabatic trigger of alternating-current pulse power supply, changed the irreversible power conversion mode of traditional circuit from the electric energy to heat energy, fully charge stored in the recovery circuit internal node realizes the recycling of energy, thereby has reduced the power consumption of circuit.
Along with the continuous progress of semiconductor technology, the needed area ratio of wiring is increasing on the silicon chip, thereby has limited the further raising of integrated level and information density.Adopt multi valued logic can improve the amount of information that every connecting line carries, significantly reduce the quantity of connecting line in the circuit, thereby reduce area of chip, strengthen data-handling capacity.The good characteristic that domino circuit is fast with its speed, area is little is widely used in the high-speed computation circuit and critical path in processor, register, the buffer, therefore multi valued logic is combined with domino circuit and can improve circuit level and information density to a greater extent.Reflect this, adiabatic logic, multi valued logic and domino circuit are applied in the design of trigger and have realistic meaning.
Summary of the invention
Technical problem to be solved by this invention provides a kind of guaranteeing to have under the prerequisite of correct logic functions, can improve three value low-power consumption domino JKL triggers of circuit level and information density.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of three value low-power consumption domino JKL triggers; By the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; The 3rd tri-valued, thermal-insulating domino literal computing circuit; The 4th tri-valued, thermal-insulating domino literal computing circuit; Three value JKL trigger basic circuits and adiabatic domino buffer are formed; The described first tri-valued, thermal-insulating domino literal computing circuit; The described second tri-valued, thermal-insulating domino literal computing circuit; Described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with first clock signal input terminal and second clock signal input part; Described three value JKL trigger basic circuits are provided with first clock signal input terminal; The second clock signal input part; The 3rd clock signal input terminal; First signal input part; The secondary signal input; The 3rd signal input part and the 4th signal input part; The signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit is connected with first signal input part of described three value JKL trigger basic circuits; The signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits; The signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits; The signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits; The signal output part of described three value JKL trigger basic circuits is connected with the signal input part of described adiabatic domino buffer; The signal output part of described adiabatic domino buffer is connected with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of the described first tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of the described second tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be first clock signal input terminal of three value low-power consumption domino JKL triggers; The second clock signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers; The 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers; This three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal; Described first clock signal input terminal inserts first clock signal of amplitude level counterlogic 2; Described second clock signal input part inserts the second clock signal of amplitude level counterlogic 2; Described the 3rd clock signal input terminal inserts the 3rd clock signal of amplitude level counterlogic 1; Described the 4th clock signal input terminal inserts the 4th clock signal of amplitude level counterlogic 1; Described first clock signal is identical with described the 4th clock signal phase; Described second clock signal is identical with described the 3rd clock signal phase, and described first clock signal and described second clock signal phase differ 180 degree.
The described first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module; Described literal computing module is managed by a PMOS; The 2nd PMOS pipe; The 3rd PMOS pipe; The 4th PMOS pipe; The 5th PMOS pipe; The 6th PMOS pipe; The one NMOS pipe; The 2nd NMOS pipe; The 3rd NMOS pipe; The 4th NMOS pipe; The 5th NMOS pipe; The 6th NMOS pipe and the 7th NMOS pipe are formed; The grid of the grid of described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of described NMOS pipe; The grid of the source electrode of described PMOS pipe and described the 3rd PMOS pipe also connects; The source electrode of described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe; The source electrode of described the 3rd PMOS pipe; The drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th PMOS pipe; The drain electrode of described the 4th NMOS pipe; The grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe; The drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects; The grid of described PMOS pipe; The drain electrode of described the 2nd PMOS pipe; The grid of described the 4th PMOS pipe; The drain electrode of described the 5th PMOS pipe; The grid of described the 2nd NMOS pipe; The source electrode of described the 3rd NMOS pipe; The source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to first clock signal input terminal; The drain electrode of described PMOS pipe; The grid of described the 2nd PMOS pipe; The drain electrode of described the 4th PMOS pipe; The grid of described the 5th PMOS pipe; The source electrode of described the 2nd NMOS pipe; The grid of described the 3rd NMOS pipe; The grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part; Described waveform transformation module is managed by the 8th NMOS; The 9th NMOS pipe; The tenth NMOS pipe; The 11 NMOS pipe; The 12 NMOS pipe and the 13 NMOS pipe are formed; The drain electrode of described the 8th NMOS pipe is connected with the drain electrode of described NMOS pipe; The source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe; The drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe; The source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe; The drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe; The source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe; The grid of described the 8th NMOS pipe; The grid of the grid of described the tenth NMOS pipe and described the 12 NMOS pipe is connected to first clock signal input terminal; The source electrode of described the 9th NMOS pipe; The source electrode of the source electrode of described the 11 NMOS pipe and described the 13 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th NMOS pipe is first signal output part; The drain electrode of described the 11 NMOS pipe is the secondary signal output; The drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of the described second tri-valued, thermal-insulating domino literal computing circuit; The circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with the described first tri-valued, thermal-insulating domino literal computing circuit.
Described three value JKL trigger basic circuits comprise first control signal generation circuit; Second control signal generation circuit and next state signal generating circuit; Described first control signal generation circuit is managed by the 7th PMOS; The 14 NMOS pipe; The 15 NMOS pipe; The 16 NMOS pipe; The 17 NMOS pipe; The 18 NMOS pipe; The 19 NMOS pipe and the 20 NMOS pipe are formed; The source electrode of described the 7th PMOS pipe; The drain electrode of described the 14 NMOS pipe; The drain electrode of the drain electrode of described the 16 NMOS pipe and described the 18 NMOS pipe and connect and itself and to connect end be first control signal output ends; The source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe; The source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe; The source electrode of described the 15 NMOS pipe; The source electrode of described the 17 NMOS pipe; The source electrode of described the 19 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; Described second control signal generation circuit is managed by the 8th PMOS; The 21 NMOS pipe; The 22 NMOS pipe; The 23 NMOS pipe; The 24 NMOS pipe; The 25 NMOS pipe; The 26 NMOS pipe and the 27 NMOS pipe are formed; The source electrode of described the 8th PMOS pipe; The drain electrode of described the 21 NMOS pipe; The drain electrode of the drain electrode of described the 23 NMOS pipe and described the 25 NMOS pipe and connect and itself and to connect end be second control signal output ends; The source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe; The source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe; The source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe; The source electrode of described the 22 NMOS pipe; The source electrode of described the 24 NMOS pipe; The source electrode of described the 26 NMOS pipe is connected with the drain electrode of described the 27 NMOS pipe; Described next state signal generating circuit is managed by the 9th PMOS; The tenth PMOS pipe and the 28 NMOS pipe are formed; The grid of described the 9th PMOS pipe is connected with described first control signal output ends; The grid of described the tenth PMOS pipe is connected with described second control signal output ends; The source electrode of described the 9th PMOS pipe; The drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end and be signal output part; The grid of described the 14 NMOS pipe is connected with the secondary signal output of the described first tri-valued, thermal-insulating domino literal computing circuit; The grid of the 15 NMOS pipe all is connected with first signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 22 NMOS pipe; The grid of described the 16 NMOS pipe is connected with first signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 17 NMOS pipe all is connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 24 NMOS pipe; The grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 19 NMOS pipe all is connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 26 NMOS pipe; The grid of described the 21 NMOS pipe is connected with the 3rd signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 23 NMOS pipe is connected with the secondary signal output of the described second tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 25 NMOS pipe is connected with first signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The drain electrode of described the 7th PMOS pipe; The drain electrode of described the 8th PMOS pipe; The source electrode of described the 20 NMOS pipe; The grid of the source electrode of described the 27 NMOS pipe and described the 28 NMOS pipe is connected to first clock signal input terminal; The grid of described the 7th PMOS pipe; The grid of described the 8th PMOS pipe; The drain electrode of described the tenth PMOS pipe; The grid of described the 20 NMOS pipe; The grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.
Described adiabatic domino buffer is managed by the 11 PMOS; The 12 PMOS pipe; The 13 PMOS pipe; The 14 PMOS pipe; The 15 PMOS pipe; The 16 PMOS pipe; The 29 NMOS pipe; The 30 NMOS pipe; The 31 NMOS pipe; The 32 NMOS pipe; The 33 NMOS pipe; The 34 NMOS pipe; The 35 NMOS pipe; The 36 NMOS pipe; The 37 NMOS pipe; The 38 NMOS pipe and the 39 NMOS pipe are formed; The source electrode of described the 11 PMOS pipe; The grid of described the 13 PMOS pipe is connected with the drain electrode of described the 29 NMOS pipe; The source electrode of described the 29 NMOS pipe is connected with the drain electrode of described the 30 NMOS pipe; The source electrode of described the 12 PMOS pipe is connected with the drain electrode of described the 13 PMOS pipe; The source electrode of described the 13 PMOS pipe; The drain electrode of described the 31 NMOS pipe is connected with the drain electrode of described the 35 NMOS pipe; The source electrode of described the 14 PMOS pipe; The grid of described the 16 PMOS pipe; The drain electrode of described the 32 NMOS pipe is connected with the grid of described the 35 NMOS pipe; The source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe; The source electrode of described the 15 PMOS pipe is connected with the drain electrode of described the 16 PMOS pipe; The drain electrode of described the 16 PMOS pipe; The drain electrode of described the 34 NMOS pipe is connected with the drain electrode of described the 38 NMOS pipe; The drain electrode of described the 35 NMOS pipe is connected with the drain electrode of described the 36 NMOS pipe; The source electrode of described the 36 NMOS pipe is connected with the grid of described the 37 NMOS pipe; The source electrode of described the 38 NMOS pipe is connected with the grid of described the 39 NMOS pipe; The grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end and be signal output part; The drain electrode of described the 11 PMOS pipe; The grid of described the 12 PMOS pipe; The drain electrode of described the 14 PMOS pipe; The grid of described the 15 PMOS pipe; The source electrode of described the 30 NMOS pipe; The grid of described the 31 NMOS pipe; The source electrode of described the 33 NMOS pipe; The source electrode of the grid of described the 34 NMOS pipe and described the 39 NMOS pipe and connect and itself and to connect end be first clock signal input terminal; The grid of described the 11 PMOS pipe; The drain electrode of described the 12 PMOS pipe; The grid of described the 14 PMOS pipe; The drain electrode of described the 15 PMOS pipe; The grid of described the 30 NMOS pipe; The source electrode of described the 31 NMOS pipe; The grid of described the 33 NMOS pipe; The source electrode of described the 34 NMOS pipe; The grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end and be the second clock signal input part; The source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal; The output signal of described adiabatic domino buffer is identical with its input signal; And its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half; First clock signal input terminal of described adiabatic domino buffer is connected with first clock signal input terminal of the described first tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.
Compared with prior art; The invention has the advantages that the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit and three value JKL trigger basic circuits through being provided with; Adiabatic logic, multi valued logic and domino circuit are applied in the design of JKL trigger; The circuit level and the information density of JKL trigger have been improved; Compare with conventional three value domino JKL triggers, energy consumption saves about 69%.
Description of drawings
Fig. 1 (a) is a circuit diagram of the present invention;
Fig. 1 (b) circuit symbol figure of the present invention;
Fig. 2 (a) is the circuit diagram of literal computing module of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;
Fig. 2 (b) is the waveform transformation module circuit diagram of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;
Fig. 2 (c) is the circuit symbol figure of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;
Fig. 3 (a) is the circuit diagram of first control signal generation circuit in the three value JKL trigger basic circuits of embodiment;
Fig. 3 (b) is the circuit diagram of second control signal generation circuit in the three value JKL trigger basic circuits of embodiment;
Fig. 3 (c) is the circuit diagram of next state control signal generation circuit in the three value JKL trigger basic circuits of embodiment;
Fig. 3 (d) is the circuit symbol figure of the three value JKL trigger basic circuits of embodiment;
Fig. 4 is the clock signal oscillogram;
Fig. 5 (a) is the circuit diagram of adiabatic domino buffer;
Fig. 5 (b) is the circuit symbol figure of adiabatic domino buffer;
Fig. 6 is the analog waveform figure of embodiments of the invention;
Fig. 7 is the power consumption comparison diagram of the present invention and the conventional domino JKL trigger of three values.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
Design principle of the present invention is: three value JKL trigger truth tables are as shown in table 1, wherein J, K, LBe input signal, QWith Q' be respectively existing attitude of trigger and next state, dFor arbitrary value and d∈ 0,1,2}.Can know the next state of trigger through truth table Q' depend on input signal J, K, LWith existing attitude Q, so trigger is the sharp type circuit of typical rice, attitude at present QNeed through behind the buffer circuits as the input signal of next working stage.
Table 1 three value JKL trigger truth tables
Figure 2012102475646100002DEST_PATH_IMAGE001
Owing to generally have only NMOS pipe or PMOS pipe in the evaluation circuit of domino circuit, can't directly differentiate the logical one signal, so the input signal of three value JKL triggers at first will pass through tri-valued, thermal-insulating domino literal computing circuit.If input signal J, K, LAnd the existing attitude of trigger QOutput signal through behind the tri-valued, thermal-insulating domino literal computing circuit does 0 J 0, 1 J 1, 2 J 2, 0 K 0, 1 K 1, 2 K 2, 0 L 0, 1 L 1, 2 L 2, 0 Q 0, 1 Q 1, 2 Q 2, first clock signal Clk, the second clock signal
Figure 438020DEST_PATH_IMAGE002
Amplitude level counterlogic 2, the three clock signals
Figure 2012102475646100002DEST_PATH_IMAGE003
Amplitude level counterlogic 1, the second clock signal
Figure 960137DEST_PATH_IMAGE002
With the 3rd clock signal Homophase, first clock signal ClkWith the above two anti-phases (being 180 degree of phasic difference mutually),, can derive the circuit structure formula of three value JKL trigger basic circuits according to the truth table of switch-signal theory and three value JKL triggers.
Example One: Figure 1 (a) and Fig 1 (b) shows a three-value low-power domino JKL trigger, the first three-value operation circuit insulation domino words, the value of second and third insulating text operation domino circuit, the third three adiabatic domino text value calculation circuit, the fourth three-valued adiabatic domino text arithmetic circuit, three values of the basic circuitry and insulation JKL trigger domino buffers, the first three values text adiabatic operation domino circuit, a second three-valued domino text adiabatic operation circuit, a third insulating domino three-value calculation circuit and the fourth text three-value calculation circuit insulation domino text is provided with a first clock signal input terminal and a second clock signal input terminal, the three values of the basic circuit arrangement of flip-flop JKL a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first signal input terminal, a second signal input terminal, a third signal input terminal and a fourth signal input terminal, a first three-value Adiabatic domino text signal arithmetic circuit output terminal of the flip-flop JKL basic circuit ternary signal input terminal connected to a first, second and third insulating domino text value calculating circuit and the signal output terminal of flip-flop ternary basic circuit JKL second signal input terminal, a third insulating domino text three-value calculation circuit and the signal output terminal of flip-flop JKL basic circuit ternary signal input terminal connected to a third, a fourth three-value calculating circuit insulation domino text signal output terminal of the three-value JKL a fourth basic circuit trigger signal input terminal, the three value JKL trigger signal output terminal of the basic circuit and the adiabatic Domino signal input terminal connected to the buffer, the buffer insulating domino signal output terminal and the fourth three-value text insulating domino arithmetic circuit connected to the signal input terminal, a first insulating domino text three-value calculating circuit a first clock signal input terminal, a second insulating domino text three-value calculating circuit a first clock signal input terminal, a third three-value text adiabatic operation domino a first clock signal circuit input terminal, a fourth three-value calculating circuit insulation text domino first clock signal input terminal and the three values of the basic circuit JKL first flip-flop clock signal input terminal and connected with its end connected to the three-value and Domino JKL low power flip-flop a first clock signal input terminal, a first insulating domino text three-value calculating circuit a second clock signal input terminal, a second insulating domino text three-value calculating circuit a second clock signal input terminal, the first thirty-three domino text insulation value calculating circuit a second clock signal input terminal, a fourth three-value calculating circuit insulation domino text input terminal and the second clock signal of the three values of the flip-flop of the basic circuit JKL second clock signal input terminal and connected and whose end is connected to three-value and low power trigger domino JKL second clock signal input terminal, the three values of the basic circuit JKL third flip-flop clock signal input terminal for the three values of low power trigger domino JKL a third clock signal input terminal, the three-valued low-power trigger is also provided with domino JKL fourth clock signal input terminal, a first clock signal input terminal connected amplitude level corresponding to a first clock signal Logic 2
Figure 2012102475646100002DEST_PATH_IMAGE005
, the second the clock signal input terminal connected amplitude level corresponding to the logic of the second clock signal 2
Figure 705556DEST_PATH_IMAGE006
, the third clock signal input amplitude level corresponding to the logical access a third clock signal
Figure 2012102475646100002DEST_PATH_IMAGE007
, the fourth clock signal input amplitude access level corresponds to logic 1, the fourth clock signal
Figure 390484DEST_PATH_IMAGE008
, the first clock signal
Figure 99814DEST_PATH_IMAGE005
and the fourth clock signal
Figure 50453DEST_PATH_IMAGE008
the same phase, a second clock signal
Figure 122838DEST_PATH_IMAGE006
and the third clock signal phase
Figure 475322DEST_PATH_IMAGE007
the same as the first clock signal
Figure 355554DEST_PATH_IMAGE005
and the second clock signal
Figure 793488DEST_PATH_IMAGE006
phase difference of 180 degrees, the first a clock signal
Figure 401056DEST_PATH_IMAGE005
, a second clock signal
Figure 873626DEST_PATH_IMAGE006
, the third clock signal
Figure 924758DEST_PATH_IMAGE007
and the fourth clock signal
Figure 849989DEST_PATH_IMAGE008
The waveform shown in Figure 4.
In the present embodiment, the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module.Shown in Fig. 2 (a); Described literal computing module is by PMOS pipe P1; The 2nd PMOS manages P2; The 3rd PMOS manages P3; The 4th PMOS manages P4; The 5th PMOS manages P5; The 6th PMOS manages P6; The one NMOS manages N1; The 2nd NMOS manages N2; The 3rd NMOS manages N3; The 4th NMOS manages N4; The 5th NMOS manages N5; The 6th NMOS pipe N6 and the 7th NMOS pipe N7 form; The grid of the grid of the one NMOS pipe N1 and the 4th NMOS pipe N4 and connect and itself and connect end and be signal input part; The drain electrode of the one NMOS pipe N1; The grid of the source electrode of the one PMOS pipe P1 and the 3rd PMOS pipe P3 also connects; The source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2; The source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3; The source electrode of the 3rd PMOS pipe P3; The drain electrode of the drain electrode of the 3rd NMOS pipe N3 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th PMOS pipe P4; The drain electrode of the 4th NMOS pipe N4; The grid of the grid of the 6th PMOS pipe P6 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5; The source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6; The drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 also connects; The grid of the one PMOS pipe P1; The drain electrode of the 2nd PMOS pipe P2; The grid of the 4th PMOS pipe P4; The drain electrode of the 5th PMOS pipe P5; The grid of the 2nd NMOS pipe N2; The source electrode of the 3rd NMOS pipe N3; The source electrode of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to first clock signal input terminal, the drain electrode of PMOS pipe P1; The grid of the 2nd PMOS pipe P2; The drain electrode of the 4th PMOS pipe P4; The grid of the 5th PMOS pipe P5; The source electrode of the 2nd NMOS pipe N2; The grid of the 3rd NMOS pipe N3; The grid of the source electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the second clock signal input part; Shown in Fig. 2 (b); The waveform transformation module is by the 8th NMOS pipe N8; The 9th NMOS manages N9; The tenth NMOS manages N10; The 11 NMOS manages N11; The 12 NMOS pipe N12 and the 13 NMOS pipe N13 form; The drain electrode of the 8th NMOS pipe N8 is connected with the drain electrode of NMOS pipe N1; The source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9; The drain electrode of the tenth NMOS pipe N10 is connected with the source electrode of the 7th NMOS pipe N7; The source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11; The drain electrode of the 12 NMOS pipe N12 is connected with the source electrode of the 6th PMOS pipe P6; The source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13; The grid of the 8th NMOS pipe N8; The grid of the grid of the tenth NMOS pipe N10 and the 12 NMOS pipe N12 is connected to first clock signal input terminal, inserts first clock signal
Figure 261248DEST_PATH_IMAGE005
, the source electrode of the source electrode of the 9th NMOS pipe N9, the 11 NMOS pipe N11 and the source electrode of the 13 NMOS pipe N13 are connected to the second clock signal input part, insert the second clock signal
Figure DEST_PATH_IMAGE009
, the drain electrode of the 9th NMOS pipe N9 is first signal output part, and the drain electrode of the 11 NMOS pipe N11 is the secondary signal output, and the drain electrode of the 13 NMOS pipe N13 is the 3rd signal output part; The circuit structure of the circuit structure of the circuit structure of the second tri-valued, thermal-insulating domino literal computing circuit, the 3rd tri-valued, thermal-insulating domino literal computing circuit, the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with the first tri-valued, thermal-insulating domino literal computing circuit; Wherein, the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit inserts first input signal J, the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is exported first input signal JThree corresponding literal computing signals, promptly the first signal output part output logic value is 0 the first literal computing signal
Figure 260428DEST_PATH_IMAGE010
, secondary signal output output logic value is 1 the second literal computing signal
Figure DEST_PATH_IMAGE011
, the 3rd signal output part output logic value is 2 the 3rd literal computing signal
Figure 731729DEST_PATH_IMAGE012
, the signal input part of the second tri-valued, thermal-insulating domino literal computing circuit inserts second input signal K, the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is exported second input signal KThree corresponding literal computing signals
Figure DEST_PATH_IMAGE013
,
Figure 81939DEST_PATH_IMAGE014
With
Figure DEST_PATH_IMAGE015
, the signal input part of the 3rd tri-valued, thermal-insulating domino literal computing circuit inserts the 3rd input signal L, the signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit is exported the 3rd input signal LThree corresponding literal computing signals ,
Figure DEST_PATH_IMAGE017
With
Figure 419084DEST_PATH_IMAGE018
, the signal input part of the 4th tri-valued, thermal-insulating domino literal computing circuit inserts the output signal of three value JKL trigger basic circuits Q, the signal output part output signal of the 4th tri-valued, thermal-insulating domino literal computing circuit QThree corresponding literal computing signals ,
Figure 795708DEST_PATH_IMAGE020
With
Figure DEST_PATH_IMAGE021
In the present embodiment, three value JKL trigger basic circuits comprise first control signal generation circuit, second control signal generation circuit and next state signal generating circuit.Shown in Fig. 3 (a); First control signal produces circuit and is made up of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16, the 17 NMOS pipe N17, the 18 NMOS pipe N18, the 19 NMOS pipe N19 and the 20 NMOS pipe N20; The drain electrode of the drain electrode of the drain electrode of the source electrode of the 7th PMOS pipe P7, the 14 NMOS pipe N14, the 16 NMOS pipe N16 and the 18 NMOS pipe N18 and connect and itself and to connect end be the first control signal output; The control signal
Figure 633214DEST_PATH_IMAGE022
of the first control signal output output logic, 1 signal; The source electrode of the 14 NMOS pipe N14 is connected with the drain electrode of the 15 NMOS pipe N15; The source electrode of the 16 NMOS pipe N16 is connected with the drain electrode of the 17 NMOS pipe N17; The source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 19 NMOS pipe N19; The source electrode of the source electrode of the source electrode of the 15 NMOS pipe N15, the 17 NMOS pipe N17, the 19 NMOS pipe N19 is connected with the drain electrode of the 20 NMOS pipe N20; Shown in Fig. 3 (b); Second control signal produces circuit and is made up of the 8th PMOS pipe P8, the 21 NMOS pipe N21, the 22 NMOS pipe N22, the 23 NMOS pipe N23, the 24 NMOS pipe N24, the 25 NMOS pipe N25, the 26 NMOS pipe N26 and the 27 NMOS pipe N27; The drain electrode of the drain electrode of the drain electrode of the source electrode of the 8th PMOS pipe P8, the 21 NMOS pipe N21, the 23 NMOS pipe N23 and the 25 NMOS pipe N25 and connect and itself and to connect end be the second control signal output; The source electrode of the 21 NMOS pipe N21 is connected with the drain electrode of the 22 NMOS pipe N22; The source electrode of the 23 NMOS pipe N23 is connected with the drain electrode of the 24 NMOS pipe N24; The source electrode of the 25 NMOS pipe N25 is connected with the drain electrode of the 26 NMOS pipe N26; The source electrode of the source electrode of the source electrode of the 22 NMOS pipe N22, the 24 NMOS pipe N24, the 26 NMOS pipe N26 is connected with the drain electrode of the 27 NMOS pipe N27; Shown in Fig. 3 (c); The next state signal generating circuit is made up of the 9th PMOS pipe P9, the tenth PMOS pipe P10 and the 28 NMOS pipe N28; The grid of the 9th PMOS pipe P9 is connected with the first control signal output; The grid of the tenth PMOS pipe P10 is connected with the second control signal output; The control signal
Figure DEST_PATH_IMAGE023
of the second control signal output output logic, 2 signals; The drain electrode of the source electrode of the source electrode of the 9th PMOS pipe P9, the tenth PMOS pipe P10 and the 28 NMOS pipe N28 and connect and itself and connect end and be signal output part; The grid of the 14 NMOS pipe N14 is connected with the secondary signal output of the first tri-valued, thermal-insulating domino literal computing circuit; The grid of the 15 NMOS pipe N15 all is connected with first signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 22 NMOS pipe N22; The grid of the 16 NMOS pipe N16 is connected with first signal output part of the second tri-valued, thermal-insulating domino literal computing circuit; The grid of the 17 NMOS pipe N17 all is connected with the secondary signal output of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 24 NMOS pipe N24; The grid of the 18 NMOS pipe N18 is connected with the 3rd signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit; The grid of the 19 NMOS pipe N19 all is connected with the 3rd signal output part of the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of the 26 NMOS pipe N26; The grid of the 21 NMOS pipe N21 is connected with the 3rd signal output part of the first tri-valued, thermal-insulating domino literal computing circuit; The grid of the 23 NMOS pipe N23 is connected with the secondary signal output of the second tri-valued, thermal-insulating domino literal computing circuit; The grid of the 25 NMOS pipe N25 is connected with first signal output part of the 3rd tri-valued, thermal-insulating domino literal computing circuit; The grid of the source electrode of the source electrode of the drain electrode of the drain electrode of the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 20 NMOS pipe N20, the 27 NMOS pipe N27 and the 28 NMOS pipe N28 is connected to first clock signal input terminal; The grid of the grid of the drain electrode of the grid of the grid of the 7th PMOS pipe P7, the 8th PMOS pipe P8, the tenth PMOS pipe P10, the 20 NMOS pipe N20, the 27 NMOS pipe N27 and the 28 NMOS pipe N28 source electrode are connected to the second clock signal input part, and the drain electrode of the 9th PMOS pipe P9 is the 3rd clock signal input terminal; The circuit symbol of three value JKL trigger basic circuits is shown in Fig. 3 (d).
In the present embodiment, the design principle of adiabatic domino buffer is identical with the first tri-valued, thermal-insulating domino literal computing circuit.Figure 5 (a), the insulation from the eleventh PMOS transistor domino buffer P11, twelfth PMOS transistor P12, PMOS transistor thirteenth P13, fourteenth PMOS transistors P14, fifteenth PMOS transistor P15, the first sixteen PMOS transistor P16, the twenty-ninth NMOS transistors N29, thirtieth NMOS transistor N30, the thirty-first NMOS transistor N31, thirty second NMOS transistor N32, the thirty-third NMOS transistor N33, the thirty-fourth NMOS tube N34, thirty-fifth NMOS transistor N35, the thirty-sixth NMOS transistors N36, thirty-seventh NMOS transistor N37, the thirty-eighth and thirty-ninth NMOS transistors N38 NMOS transistors N39 composed eleventh PMOS transistor P11 The source electrode, the gate of the thirteenth PMOS transistor P13 and 29, connected to the drain NMOS transistor N29, 29 and NMOS transistor N29 and the source electrode of the thirty-drain of NMOS transistor N30 connected to the tenth two PMOS transistor P12, the source electrode and the drain of the thirteenth PMOS transistor P13 connected to the thirteenth source of PMOS transistor P13, the thirty-drain of NMOS transistor N31 and the thirty-fifth drain of NMOS transistor N35 connection, XIV PMOS transistor P14, the source electrode, the gate of the sixteenth PMOS transistor P16, NMOS transistor N32 of the thirty-second and thirty-fifth drain of NMOS transistor N35 connected to the gate, the thirty-second NMOS tube N32 and 33 of the source electrode of the NMOS transistor N33 connected to the drain, the fifteenth PMOS transistor P15 and 16, the source electrode connected to the drain PMOS transistor P16, the sixteenth drain of PMOS transistor P16, the first thirty-four drain of NMOS transistor N34 and the thirty-eighth NMOS transistor N38 connected to the drain of the thirty-fifth drain of NMOS transistor N35 and 36 connected to the drain of NMOS transistor N36, thirty-sixth NMOS N36 tube source and a thirty-seventh NMOS transistor N37 connected to the gate of the thirty-eighth NMOS transistor N38 and 39 of the source electrode connected to the gate NMOS transistor N39, 29 and the gate NMOS transistor N29 and thirty-second electrode of NMOS transistor N32 and the gate and connected and whose end is connected to the signal input terminal, the thirty-seventh drain of NMOS transistor N37 and 39 of the NMOS transistor N39 and whose drain and connected and signal output terminal is connected to the eleventh drain of PMOS transistor P11, PMOS transistor P12 gate of the twelfth, fourteenth drain of PMOS transistor P14, the fifteenth gate of PMOS transistor P15, thirty a source NMOS transistor N30, N31 XXXI gate of NMOS transistor, thirty-third NMOS transistor N33 of the source electrode, the thirty-fourth gate of NMOS transistor N34 and 39 of the source electrode of NMOS transistor N39 and connected with its end and connected to a first clock signal input terminal, the eleventh gate of PMOS transistor P11, PMOS transistor P12, the twelfth drain, the fourteenth gate of PMOS transistor P14, PMOS transistor fifteenth The drain of P15, N30 thirty gate of NMOS transistor, thirty source NMOS transistor N31, thirty-third gate of NMOS transistor N33, the thirty-fourth NMOS transistor N34 of the source electrode, the third the gate of the NMOS transistor N36 sixteen and thirty-eighth NMOS transistor N38 and the gate and connected to its end and then a second clock signal input terminal, the thirty-seventh source of NMOS transistor N37 is extremely third clock signal input terminal adiabatic domino its input buffer output signal is the same signal, and the output signal of the buffer insulating domino than its input signal delayed by half a clock cycle, a first insulating domino buffer clock signal input terminal and the first three-value text insulating domino a first arithmetic circuit connected to the clock signal input terminal, the access level for the logical amplitude of the first clock signal 2
Figure 386275DEST_PATH_IMAGE005
, insulating domino second clock signal buffer and the first input terminal of three-value calculating circuit insulating second domino text the clock signal input terminal connecting to the access logic amplitude level corresponding to a second clock signal 2
Figure 687943DEST_PATH_IMAGE006
, a third insulating domino buffer clock signal input terminal and the fourth clock signal input terminal, an access amplitude level corresponding to a logic 1 fourth clock signal
Figure 986200DEST_PATH_IMAGE024
, the circuit symbol shown in Figure 5 (b) in Fig.
Utilize Spice software, under TSMC 0.25 μ m CMOS technological parameter, three value low-power consumption domino JKL triggers are simulated, waveform as shown in Figure 6.Wherein logical value 0,1,2 corresponding level are respectively 0V, 1.25V, 2.5V; Clk 1,
Figure 373319DEST_PATH_IMAGE003
, Clk,
Figure 743121DEST_PATH_IMAGE006
Amplitude be respectively 1.25 V, 1.25 V, 2.5 V, 2.5 V, frequency all is 20 MHz; The NMOS breadth length ratio is all got 0.36 μ m/0.24 μ m, and the PMOS breadth length ratio is all got 0.72 μ m/0.24 μ m; Load capacitance is 10 fF; J, K, LBe input signal, QBe the output signal.Analysis chart 6 can know, the logic function of this circuit and three value JKL trigger truth tables are consistent, prove to design the circuit logic function correct.
Under identical parameters, tri-valued, thermal-insulating domino JKL trigger and the conventional domino JKL trigger of three values that adopts DC power supply are carried out power consumption relatively, as shown in Figure 7.Charge stored is recovered to power clock in the concave bottom proof circuit node among the figure in the tri-valued, thermal-insulating domino JKL trigger power consumption curve, thereby reduces circuit power consumption effectively.Through analyzing, this tri-valued, thermal-insulating domino JKL trigger is with respect to the conventional domino JKL trigger of three values that adopts DC power supply, and Power Cutback is about 69%, prove to design circuit low-power consumption characteristic obvious.

Claims (4)

1. one kind three is worth low-power consumption domino JKL trigger; It is characterized in that by the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; The 3rd tri-valued, thermal-insulating domino literal computing circuit; The 4th tri-valued, thermal-insulating domino literal computing circuit; Three value JKL trigger basic circuits and adiabatic domino buffer are formed; The described first tri-valued, thermal-insulating domino literal computing circuit; The described second tri-valued, thermal-insulating domino literal computing circuit; Described the 3rd tri-valued, thermal-insulating domino literal computing circuit and described the 4th tri-valued, thermal-insulating domino literal computing circuit are provided with first clock signal input terminal and second clock signal input part; Described three value JKL trigger basic circuits are provided with first clock signal input terminal; The second clock signal input part; The 3rd clock signal input terminal; First signal input part; The secondary signal input; The 3rd signal input part and the 4th signal input part; The signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit is connected with first signal input part of described three value JKL trigger basic circuits; The signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit is connected with the secondary signal input of described three value JKL trigger basic circuits; The signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit is connected with the 3rd signal input part of described three value JKL trigger basic circuits; The signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit is connected with the 4th signal input part of described three value JKL trigger basic circuits; The signal output part of described three value JKL trigger basic circuits is connected with the signal input part of described adiabatic domino buffer; The signal output part of described adiabatic domino buffer is connected with the signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of the described first tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of the described second tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; First clock signal input terminal of first clock signal input terminal of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be first clock signal input terminal of three value low-power consumption domino JKL triggers; The second clock signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of the second clock signal input part of described the 4th tri-valued, thermal-insulating domino literal computing circuit and described three value JKL trigger basic circuits and connect and itself and connect the end be the second clock signal input part of three value low-power consumption domino JKL triggers; The 3rd clock signal input terminal of described three value JKL trigger basic circuits is the 3rd clock signal input terminal of three value low-power consumption domino JKL triggers; This three values low-power consumption domino JKL trigger also is provided with the 4th clock signal input terminal; Described first clock signal input terminal inserts first clock signal of amplitude level counterlogic 2; Described second clock signal input part inserts the second clock signal of amplitude level counterlogic 2; Described the 3rd clock signal input terminal inserts the 3rd clock signal of amplitude level counterlogic 1; Described the 4th clock signal input terminal inserts the 4th clock signal of amplitude level counterlogic 1; Described first clock signal is identical with described the 4th clock signal phase; Described second clock signal is identical with described the 3rd clock signal phase, and described first clock signal and described second clock signal phase differ 180 degree.
2. a kind of three value low-power consumption domino JKL triggers according to claim 1; It is characterized in that the described first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module; Described literal computing module is managed by a PMOS; The 2nd PMOS pipe; The 3rd PMOS pipe; The 4th PMOS pipe; The 5th PMOS pipe; The 6th PMOS pipe; The one NMOS pipe; The 2nd NMOS pipe; The 3rd NMOS pipe; The 4th NMOS pipe; The 5th NMOS pipe; The 6th NMOS pipe and the 7th NMOS pipe are formed; The grid of the grid of described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of described NMOS pipe; The grid of the source electrode of described PMOS pipe and described the 3rd PMOS pipe also connects; The source electrode of described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe; The source electrode of described the 3rd PMOS pipe; The drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th PMOS pipe; The drain electrode of described the 4th NMOS pipe; The grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe; The drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects; The grid of described PMOS pipe; The drain electrode of described the 2nd PMOS pipe; The grid of described the 4th PMOS pipe; The drain electrode of described the 5th PMOS pipe; The grid of described the 2nd NMOS pipe; The source electrode of described the 3rd NMOS pipe; The source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to first clock signal input terminal; The drain electrode of described PMOS pipe; The grid of described the 2nd PMOS pipe; The drain electrode of described the 4th PMOS pipe; The grid of described the 5th PMOS pipe; The source electrode of described the 2nd NMOS pipe; The grid of described the 3rd NMOS pipe; The grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part; Described waveform transformation module is managed by the 8th NMOS; The 9th NMOS pipe; The tenth NMOS pipe; The 11 NMOS pipe; The 12 NMOS pipe and the 13 NMOS pipe are formed; The drain electrode of described the 8th NMOS pipe is connected with the drain electrode of described NMOS pipe; The source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe; The drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe; The source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe; The drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe; The source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe; The grid of described the 8th NMOS pipe; The grid of the grid of described the tenth NMOS pipe and described the 12 NMOS pipe is connected to first clock signal input terminal; The source electrode of described the 9th NMOS pipe; The source electrode of the source electrode of described the 11 NMOS pipe and described the 13 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th NMOS pipe is first signal output part; The drain electrode of described the 11 NMOS pipe is the secondary signal output; The drain electrode of described the 13 NMOS pipe is the 3rd signal output part, the circuit structure of the described second tri-valued, thermal-insulating domino literal computing circuit; The circuit structure of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The circuit structure of described the 4th tri-valued, thermal-insulating domino literal computing circuit is all identical with the described first tri-valued, thermal-insulating domino literal computing circuit.
3. a kind of three value low-power consumption domino JKL triggers according to claim 2; It is characterized in that described three value JKL trigger basic circuits comprise first control signal generation circuit; Second control signal generation circuit and next state signal generating circuit; Described first control signal generation circuit is managed by the 7th PMOS; The 14 NMOS pipe; The 15 NMOS pipe; The 16 NMOS pipe; The 17 NMOS pipe; The 18 NMOS pipe; The 19 NMOS pipe and the 20 NMOS pipe are formed; The source electrode of described the 7th PMOS pipe; The drain electrode of described the 14 NMOS pipe; The drain electrode of the drain electrode of described the 16 NMOS pipe and described the 18 NMOS pipe and connect and itself and to connect end be first control signal output ends; The source electrode of described the 14 NMOS pipe is connected with the drain electrode of described the 15 NMOS pipe; The source electrode of described the 16 NMOS pipe is connected with the drain electrode of described the 17 NMOS pipe; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe; The source electrode of described the 15 NMOS pipe; The source electrode of described the 17 NMOS pipe; The source electrode of described the 19 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; Described second control signal generation circuit is managed by the 8th PMOS; The 21 NMOS pipe; The 22 NMOS pipe; The 23 NMOS pipe; The 24 NMOS pipe; The 25 NMOS pipe; The 26 NMOS pipe and the 27 NMOS pipe are formed; The source electrode of described the 8th PMOS pipe; The drain electrode of described the 21 NMOS pipe; The drain electrode of the drain electrode of described the 23 NMOS pipe and described the 25 NMOS pipe and connect and itself and to connect end be second control signal output ends; The source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe; The source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 24 NMOS pipe; The source electrode of described the 25 NMOS pipe is connected with the drain electrode of described the 26 NMOS pipe; The source electrode of described the 22 NMOS pipe; The source electrode of described the 24 NMOS pipe; The source electrode of described the 26 NMOS pipe is connected with the drain electrode of described the 27 NMOS pipe; Described next state signal generating circuit is managed by the 9th PMOS; The tenth PMOS pipe and the 28 NMOS pipe are formed; The grid of described the 9th PMOS pipe is connected with described first control signal output ends; The grid of described the tenth PMOS pipe is connected with described second control signal output ends; The source electrode of described the 9th PMOS pipe; The drain electrode of the source electrode of described the tenth PMOS pipe and described the 28 NMOS pipe and connect and itself and connect end and be signal output part; The grid of described the 14 NMOS pipe is connected with the secondary signal output of the described first tri-valued, thermal-insulating domino literal computing circuit; The grid of the 15 NMOS pipe all is connected with first signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 22 NMOS pipe; The grid of described the 16 NMOS pipe is connected with first signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 17 NMOS pipe all is connected with the secondary signal output of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 24 NMOS pipe; The grid of described the 18 NMOS pipe is connected with the 3rd signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 19 NMOS pipe all is connected with the 3rd signal output part of described the 4th tri-valued, thermal-insulating domino literal computing circuit with the grid of described the 26 NMOS pipe; The grid of described the 21 NMOS pipe is connected with the 3rd signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 23 NMOS pipe is connected with the secondary signal output of the described second tri-valued, thermal-insulating domino literal computing circuit; The grid of described the 25 NMOS pipe is connected with first signal output part of described the 3rd tri-valued, thermal-insulating domino literal computing circuit; The drain electrode of described the 7th PMOS pipe; The drain electrode of described the 8th PMOS pipe; The source electrode of described the 20 NMOS pipe; The grid of the source electrode of described the 27 NMOS pipe and described the 28 NMOS pipe is connected to first clock signal input terminal; The grid of described the 7th PMOS pipe; The grid of described the 8th PMOS pipe; The drain electrode of described the tenth PMOS pipe; The grid of described the 20 NMOS pipe; The grid of described the 27 NMOS pipe and described the 28 NMOS pipe source electrode are connected to the second clock signal input part, and the drain electrode of described the 9th PMOS pipe is the 3rd clock signal input terminal.
4. each described a kind of three value low-power consumption domino JKL triggers in the claim 1～3; It is characterized in that described adiabatic domino buffer managed by the 11 PMOS; The 12 PMOS pipe; The 13 PMOS pipe; The 14 PMOS pipe; The 15 PMOS pipe; The 16 PMOS pipe; The 29 NMOS pipe; The 30 NMOS pipe; The 31 NMOS pipe; The 32 NMOS pipe; The 33 NMOS pipe; The 34 NMOS pipe; The 35 NMOS pipe; The 36 NMOS pipe; The 37 NMOS pipe; The 38 NMOS pipe and the 39 NMOS pipe are formed; The source electrode of described the 11 PMOS pipe; The grid of described the 13 PMOS pipe is connected with the drain electrode of described the 29 NMOS pipe; The source electrode of described the 29 NMOS pipe is connected with the drain electrode of described the 30 NMOS pipe; The source electrode of described the 12 PMOS pipe is connected with the drain electrode of described the 13 PMOS pipe; The source electrode of described the 13 PMOS pipe; The drain electrode of described the 31 NMOS pipe is connected with the drain electrode of described the 35 NMOS pipe; The source electrode of described the 14 PMOS pipe; The grid of described the 16 PMOS pipe; The drain electrode of described the 32 NMOS pipe is connected with the grid of described the 35 NMOS pipe; The source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe; The source electrode of described the 15 PMOS pipe is connected with the drain electrode of described the 16 PMOS pipe; The drain electrode of described the 16 PMOS pipe; The drain electrode of described the 34 NMOS pipe is connected with the drain electrode of described the 38 NMOS pipe; The drain electrode of described the 35 NMOS pipe is connected with the drain electrode of described the 36 NMOS pipe; The source electrode of described the 36 NMOS pipe is connected with the grid of described the 37 NMOS pipe; The source electrode of described the 38 NMOS pipe is connected with the grid of described the 39 NMOS pipe; The grid of the grid of described the 29 NMOS pipe and described the 32 NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe and connect and itself and connect end and be signal output part; The drain electrode of described the 11 PMOS pipe; The grid of described the 12 PMOS pipe; The drain electrode of described the 14 PMOS pipe; The grid of described the 15 PMOS pipe; The source electrode of described the 30 NMOS pipe; The grid of described the 31 NMOS pipe; The source electrode of described the 33 NMOS pipe; The source electrode of the grid of described the 34 NMOS pipe and described the 39 NMOS pipe and connect and itself and to connect end be first clock signal input terminal; The grid of described the 11 PMOS pipe; The drain electrode of described the 12 PMOS pipe; The grid of described the 14 PMOS pipe; The drain electrode of described the 15 PMOS pipe; The grid of described the 30 NMOS pipe; The source electrode of described the 31 NMOS pipe; The grid of described the 33 NMOS pipe; The source electrode of described the 34 NMOS pipe; The grid of the grid of described the 36 NMOS pipe and described the 38 NMOS pipe and connect and itself and connect end and be the second clock signal input part; The source electrode of described the 37 NMOS pipe is the 3rd clock signal input terminal; The output signal of described adiabatic domino buffer is identical with its input signal; And its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half; First clock signal input terminal of described adiabatic domino buffer is connected with first clock signal input terminal of the described first tri-valued, thermal-insulating domino literal computing circuit; The second clock signal input part of described adiabatic domino buffer is connected with the second clock signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit, and the 3rd clock signal input terminal of described adiabatic domino buffer is connected with described the 4th clock signal input terminal.
CN201210247564.6A 2012-07-17 2012-07-17 Three-value low power consumption domino JKL trigger Expired - Fee Related CN102790602B (en)

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CN106452427A (en) * 2016-09-21 2017-02-22 宁波大学 Bootstrapping adiabatic circuit employing clock-controlled transmission gate and four-level inverter/buffer

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US7764087B2 (en) * 2006-02-01 2010-07-27 Wisconsin Alumni Research Foundation Low swing domino logic circuits
CN102394638A (en) * 2011-10-14 2012-03-28 宁波大学 Ternary adiabatic JKL flip-flop and adiabatic novenary asynchronous counter

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Publication number Priority date Publication date Assignee Title
US7764087B2 (en) * 2006-02-01 2010-07-27 Wisconsin Alumni Research Foundation Low swing domino logic circuits
CN102394638A (en) * 2011-10-14 2012-03-28 宁波大学 Ternary adiabatic JKL flip-flop and adiabatic novenary asynchronous counter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106452427A (en) * 2016-09-21 2017-02-22 宁波大学 Bootstrapping adiabatic circuit employing clock-controlled transmission gate and four-level inverter/buffer
CN106452427B (en) * 2016-09-21 2019-01-04 宁波大学 It is a kind of to use clock transmission gate bootstrapping adiabatic circuits and level Four inverters/buffers

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