CN102765695A - Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point - Google Patents
Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point Download PDFInfo
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Abstract
The invention relates to a method of manufacturing a low-dimensional nano-structure and is used for solving the problems that existing orderly low-dimensional nano-structure is only produced in small area, the cost is high and the pollution is serious. The method of manufacturing a wafer-level low-dimensional nano-structure based on the self-focusing of an electrostatic field singular-point comprises the following steps of: firstly, obtaining a self-assembled physical substrate template of the low-dimensional nano-structure on a wafer-level silicon slice substrate by a photo-etching process and an etching process; secondly, putting the self-assembled physical substrate template on a magnetic control sputtering device target, and automatically depositing synthesized noble metal nano-particles onto a tip structure to obtain a noble metal film; and at last, annealing. According to the manufacturing method provided by the invention, the synthesized nano-particles are used, and a traditional MEMS (micro electro mechanical system) processing technology is adopted, so that the wafer-level large-scale low-dimensional nanometer material structure with low cost, zero pollution, high reliability and orderly height is obtained; and the manufacturing method can be widely suitable for manufacturing the orderly low-dimensional nano-structure in large area.
Description
Technical field
The present invention relates to the preparation method of low-dimensional nano structure, be specially a kind of preparation method of the wafer level low-dimensional nano structure based on the self-focusing of electrostatic field singular point.
Background technology
The ordered nano self-assembled structures has become one of emphasis and focus of domestic and international research in recent years, and the scientific research personnel has studied low-dimensional nano structures such as nano particle, quantum dot, the nano wire synthesis technique of assembling in order.At present, low-dimensional nano structure has been widely applied to every field such as micro-nano electronics, photoelectron, biochemical sensor in order, and has shown tempting prospect and considerable society, economic worth.
Along with low-dimensional nano structure and device progressively to highly integrated and practicability development; All stress to be applied as guiding for low Wei Nami self-assembly process at present; To a great extent low Wei Nami self-assembling technique is had higher requirement; This not only need guarantee the low Wei Nami self-assembly process that low cost, high-sequential, large tracts of land are made, compatibility that also will be good with the traditional MEMS processing technology.But at present in order the preparation method of low-dimensional nano structure can only the small size manufacturing, has greatly wasted resource and cost is higher, and low with traditional MEMS processing technology compatibility; Adopt the residual a large amount of chemical refuse of chemical synthesis process meeting when preparing simultaneously; And preparation cost is higher; And the earth that we depend on for existence is being faced with severe environmental issue; Everybody is responsible for the protection environment, so research cost is low, consumptive material is few, the nanosecond science and technology of zero pollution also become our each earth sons and daughters's research mission.
Summary of the invention
The present invention can only the small size manufacturing in order to solve existing orderly low-dimensional nano structure, cost is high, seriously polluted and with the problem of traditional M EMS processing technology poor compatibility, a kind of preparation method of the wafer level low-dimensional nano structure based on the self-focusing of electrostatic field singular point is provided.
The present invention adopts following technical scheme to realize: the preparation method based on the wafer level low-dimensional nano structure of electrostatic field singular point self-focusing comprises the steps:
(1), the preparation of low-dimensional nano structure physics substrate template (its process chart is as shown in Figure 1):
Step 1: cut-off is the wafer level silicon chip substrate (1) of 300～600 μ m for 3inch～6inch, thickness directly; (thermal oxidation method of silicon is meant: silicon and the gas that contains oxidation material to adopt thermal oxidation method; For example steam and oxygen at high temperature carry out chemical reaction, and produce the fine and close silica membrane of one deck at silicon chip surface) be the SiO of 300nm～500nm at the front and back of the wafer level silicon chip substrate layer thickness of all growing
2Mask layer.
Step 2: the front of wafer level silicon chip substrate is carried out being coated with one deck positive photoresist after cleaning surfaces is handled (it is the technology that those skilled in the art realize easily that cleaning surfaces is handled, and cleans through ultrasonic wave acetone, alcohol, deionized water successively usually); (photoetching process is on the clean smooth silicon chip of a slice, to be coated with one deck positive photoresist, is radiated on the silicon chip through a mask plate that is carved with figure with the relief ultraviolet light to utilize photoetching process; After silicon chip put into developer solution reaction; Rotten being corroded can take place in the part photoresist that is irradiated to; The photoresist that is not irradiated to then can still stick in above the silicon chip), make to obtain on the front of wafer level silicon chip substrate and mask plate (figure on the mask plate can be designed as square array or vertical bar array etc. as required) is gone up the identical litho pattern of shape.
Step 3: the SiO that the using plasma dry etching method is positive with the wafer level silicon chip substrate
2The exposed portions serve of mask layer erodes, thereby exposes the front of the wafer level silicon chip substrate that will be etched.
Step 4: adopt wet method anisotropy rot etching method that the wafer level silicon chip substrate is put into corrosive liquid circle level silicon wafer substrate is carried out etching, thereby the partial corrosion that exposed portions serve on the front of wafer level silicon chip substrate is eroded and wafer level silicon chip substrate top is contacted with litho pattern becomes tip-shape structure; Wherein corrosive liquid is to be KOH:IPA:H by mass percent
2O=23%:14%:63% mixes.The wafer level silicon chip substrate is made up of monocrystalline silicon, and wherein monocrystalline silicon has three crystal faces: 100,110,111, wherein horizontal plane is (110) face, (100) face is perpendicular to (110) face, with the angle of (100) face be 54.74 ° be (111) face; Because atomic arrangement density difference has caused the silicon single crystal anisotropy on the various crystal faces, shows as the corrosion rate difference highlightedly; Corrosive liquid is far longer than (111) face to the corrosion rate of (100) face on the wafer level silicon chip substrate, so corrosive liquid corrodes on (100) face, forms the V-type groove along (111) face, and shape structure like this tapers off to a point when two V-shaped grooves link together.
Step 5: the wafer level silicon chip substrate put into the supporting stripper of positive photoresist react, thereby remove the positive litho pattern of wafer level silicon chip substrate.
Step 6: putting into the wafer level silicon chip substrate by percent by volume is HF:H
2Remove the positive SiO of wafer level silicon chip substrate in the hydrofluoric acid solution that O=1:5 mixes
2Mask layer, thus obtain having the low-dimensional nano structure physics substrate template of tip-shape structure.
(2), in being placed on, establishes low-dimensional nano structure physics substrate template on the target of magnetic control sputtering device of noble metal target material (noble metal can be selected Au, Ag, Pt etc. for use); With feeding the inert gas argon gas in the magnetic control sputtering device; Thereby be deposited on the low Wei Nami physics substrate template after the bombardment noble metal target material synthesizes the noble metal nano particles that breaks away from noble metal target material behind the ionized inert gas; On the orderly compact cutting-edge structure that deposits to tip-shape structure of noble metal nano particles synthetic under the electrostatic field singular point effect, thereby obtain one deck noble metal film.As shown in Figure 9; Synthetic noble metal nano particles can attach negative electrical charge automatically; When the noble metal nano particles that has electrostatic charge when having the low Wei Nami physics substrate template apparent motion of tip-shape structure; Charged noble metal nano particles will form an electron cloud, the electrostatic field that forms through this electron cloud low-dimensional nano structure physics substrate template that will further polarize, and (electric field singular point effect is meant in the big place of body surface curvature in electric field singular point effect; Close like top equipotential face sharp-pointed, fines, electric-field intensity increases severely; On the contrary, in the little place of curvature, approach zero like charge density such as recess, even surfaces, electric-field intensity reduces sharply) effect can form the electrostatic field singular point at the place, tip of cutting-edge structure down; Synthetic noble metal nano particles can deposit to the place, tip of cutting-edge structure automatically under the effect of electric field singular point effect; And finally reach electrostatic equilibrium and distribute; Form one deck noble metal film, thereby realize orderly self assembly from the synthesis of nano particle to low-dimensional nano structure.
(3), low-dimensional nano structure physics substrate template is carried out annealing process; The grain spacing of self-assembled nano structures noble metal film inside and the electrons transport property of the way of contact and nano structured unit inside are changed; Realize the transformation of nanostructured inside from the nanoparticle aggregate to the densification, thereby finally obtain the wafer level low-dimensional nano structure.
Said thermal oxidation method, photoetching process, plasma dry etching, wet method anisotropy rot etching method are the technology of well known to a person skilled in the art.
Preparation method of the present invention makes full use of synthetic noble metal nano particles self charging characteristic and electrostatic field singular point effect principle; With the good compatible prerequisite of traditional MEMS processing technology under; Adopt physical method, obtained the noble metal low-dimension nano material structure of low-cost, zero pollution, wafer level large tracts of land, high reliability and high-sequential; Break through low-dimensional nano structure inefficiency, technological jejune technical barrier in the large tracts of land self-assembly process, realized the self assembly manufacturing of wafer level low-dimensional nano structure; Having solved existing orderly low-dimensional nano structure can only the small size manufacturing, cost is high, seriously polluted and with the problem of traditional M EMS processing technology poor compatibility, can be adaptable across the large tracts of land manufacturing of orderly low-dimensional nano structure.
Description of drawings
Fig. 1 is the process chart of the first step of the present invention.
Fig. 2 is the structural representation of wafer level silicon chip substrate.
Fig. 3 is the structural representation of step 1 in the first step of the present invention.
Fig. 4 is the structural representation of step 2 in the first step of the present invention.
Fig. 5 is the structural representation of step 3 in the first step of the present invention.
Fig. 6 is the structural representation of step 4 in the first step of the present invention.
Fig. 7 is the structural representation of step 5 in the first step of the present invention.
Fig. 8 is the structural representation of step 6 in the first step of the present invention.
Fig. 9 is the schematic diagram of noble metal nano particles self-focusing under electric field singular point effect.
Figure 10 is the stereogram of one-dimensional nano line physics substrate template among the embodiment 1.
Figure 11 is the structural representation of the small size low-dimensional nano structure unit that obtains of embodiment 1.
Figure 12 is the stereogram of zero-dimension nano point physics substrate template among the embodiment 2.
Figure 13 is the structural representation of the small size low-dimensional nano structure unit that obtains of embodiment 2.
Among the figure: 1-wafer level silicon chip substrate; 2-SiO
2Mask layer; The 3-litho pattern; The tip-shape structure of 4-; The 5-cross section is leg-of-mutton tip-shape structure; 6-nanowires of gold array; The tip-shape structure of 7-rectangular pyramid nano dot; 8-silver nanometer lattice row.
The specific embodiment
Embodiment 1:
Preparation method based on the wafer level low-dimensional nano structure of electrostatic field singular point self-focusing comprises the steps:
(1) preparation of one-dimensional nano line physics substrate template:
Step 1: cut-off is the wafer level silicon chip substrate 1 of 600 μ m for 3inch, thickness directly, and adopting thermal oxidation method is the SiO of 300nm at the front and back of wafer level silicon chip substrate 1 layer thickness of all growing
2 Mask layer 2;
Step 2: the front of wafer level silicon chip substrate 1 is carried out being coated with one deck positive photoresist after cleaning surfaces is handled; Select vertical bar array-like mask plate for use, utilize photoetching process, make and form vertical bar array-like litho pattern on the front of wafer level silicon chip substrate 1;
Step 3: the SiO that the using plasma dry etching method is positive with the wafer level silicon chip substrate
2The exposed portions serve of mask layer 2 erodes;
Step 4: adopting wet method anisotropy rot etching method that wafer level silicon chip substrate 1 is put into corrosive liquid wafer level silicon chip substrate 1 is carried out etching, is leg-of-mutton tip-shape structure 5 thereby exposed portions serve on the front of wafer level silicon chip substrate 1 is eroded and the partial corrosion that wafer level silicon chip substrate 1 top contacts with vertical bar array-like litho pattern is become the cross section; Wherein corrosive liquid is to be KOH:IPA:H by mass percent
2O=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate 1 put into the supporting stripper of positive photoresist react, thereby remove the positive vertical bar array-like litho pattern of wafer level silicon chip substrate 1;
Step 6: putting into wafer level silicon chip substrate 1 by percent by volume is HF:H
2Remove the SiO of wafer level silicon chip substrate 1 front and back in the hydrofluoric acid solution that O=1:5 mixes
2Mask layer 2, thus obtain having the one-dimensional nano line physics substrate template that the cross section is leg-of-mutton tip-shape structure 5; Shown in figure 10;
(2), in being placed on, establishes one-dimensional nano line physics substrate template on the target of magnetic control sputtering device of gold target material; With feeding the inert gas argon gas in the magnetic control sputtering device; Thereby be deposited on the one-dimensional nano line physics substrate template after bombardment gold target material synthesizes the gold nano grain that breaks away from the gold target material behind the ionized inert gas, thereby obtain one deck nanowires of gold array 6 on the tip that the cross section is leg-of-mutton tip-shape structure 5 in compact in order the depositing to of gold nano grain synthetic under the electrostatic field singular point effect;
(3) one-dimensional nano line physics substrate template is carried out annealing process, thereby obtain the wafer level low-dimensional nano structure.
During use the above-mentioned wafer level low-dimensional nano structure that makes is carried out cutting whole into sections, obtain small size low-dimensional nano structure unit shown in figure 11,, thereby realize real through engineering approaches application so that be applied in the MEMS device.
Embodiment 2:
Preparation method based on the wafer level low-dimensional nano structure of electrostatic field singular point self-focusing comprises the steps:
(1) preparation of zero-dimension nano point physics substrate template:
Step 1: cut-off is the wafer level silicon chip substrate 1 of 300 μ m for 6inch, thickness directly, and adopting thermal oxidation method is the SiO of 500nm at the front and back of wafer level silicon chip substrate 1 layer thickness of all growing
2 Mask layer 2;
Step 2: the front of wafer level silicon chip substrate 1 is carried out being coated with one deck positive photoresist after cleaning surfaces is handled; Select square array mask plate for use, utilize photoetching process, make and form square array-like litho pattern on the front of wafer level silicon chip substrate 1;
Step 3: the using plasma dry etching method is with the SiO in wafer level silicon chip substrate 1 front
2The exposed portions serve of mask layer 2 erodes;
Step 4: adopt wet method anisotropy rot etching method that wafer level silicon chip substrate 1 is put into corrosive liquid wafer level silicon chip substrate 1 is carried out etching, thereby exposed portions serve on the front of wafer level silicon chip substrate 1 is eroded and the partial corrosion that wafer level silicon chip substrate 1 top contacts with square array-like litho pattern is become the tip-shape structure 7 of rectangular pyramid nano dot; Wherein corrosive liquid is to be KOH:IPA:H by mass percent
2O=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate 1 put into the supporting stripper of positive photoresist react, thereby remove the positive square array-like litho pattern of wafer level silicon chip substrate 1;
Step 6: putting into wafer level silicon chip substrate 1 by percent by volume is HF:H
2Remove the SiO of wafer level silicon chip substrate 1 front and back in the hydrofluoric acid solution that O=1:5 mixes
2Mask layer 2, thus obtain having the zero-dimension nano point physics substrate template of the tip-shape structure 7 of rectangular pyramid nano dot; Shown in figure 12;
(2) zero-dimension nano being put the physics substrate template establishes in being placed on the target of magnetic control sputtering device of silver-colored target; With feeding the inert gas argon gas in the magnetic control sputtering device; Thereby the silver-colored target of bombardment is deposited on the zero-dimension nano point physics substrate template after the silver nano-grain that breaks away from silver-colored target is synthesized behind the ionized inert gas, thereby on the orderly compact tip that deposits to the tip-shape structure 7 of rectangular pyramid nano dot of silver nano-grain synthetic under the electrostatic field singular point effect, obtains one deck silver nanometer lattice row 8;
(3) zero-dimension nano is put the physics substrate template and carry out annealing process, thereby obtain the wafer level low-dimensional nano structure.
During use the above-mentioned wafer level low-dimensional nano structure that makes is carried out cutting whole into sections, obtain small size low-dimensional nano structure unit shown in figure 13,, thereby realize real through engineering approaches application so that be applied in the MEMS device.
Claims (2)
1. based on the preparation method of the wafer level low-dimensional nano structure of electrostatic field singular point self-focusing, it is characterized in that: comprise the steps:
(1), the preparation of low-dimensional nano structure physics substrate template:
Step 1: cut-off is the wafer level silicon chip substrate (1) of 300～600 μ m for 3inch～6inch, thickness directly, and adopting thermal oxidation method is the SiO of 300nm～500nm at the front and back of wafer level silicon chip substrate (1) layer thickness of all growing
2Mask layer (2);
Step 2: the front of wafer level silicon chip substrate (1) is carried out being coated with one deck positive photoresist after cleaning surfaces is handled; Utilize photoetching process, make obtain on the front of wafer level silicon chip substrate (1) with mask plate on the identical litho pattern (3) of shape;
Step 3: the SiO that the using plasma dry etching method is positive with wafer level silicon chip substrate (1)
2The exposed portions serve of mask layer (2) erodes;
Step 4: adopt wet method anisotropy rot etching method that wafer level silicon chip substrate (1) is put into corrosive liquid wafer level silicon chip substrate (1) is carried out etching, thereby the partial corrosion that exposed portions serve on the front of wafer level silicon chip substrate (1) is eroded and wafer level silicon chip substrate (1) top is contacted with litho pattern (3) becomes tip-shape structure (4); Wherein corrosive liquid is to be KOH:IPA:H by mass percent
2O=23%:14%:63% mixes;
Step 5: wafer level silicon chip substrate (1) put into the supporting stripper of positive photoresist react, thereby remove the positive litho pattern (3) of wafer level silicon chip substrate (1);
Step 6: putting into wafer level silicon chip substrate (1) by percent by volume is HF:H
2Remove the SiO of wafer level silicon chip substrate (1) front and back in the hydrofluoric acid solution that O=1:5 mixes
2Mask layer (2), thus obtain having the low-dimensional nano structure physics substrate template of tip-shape structure (4);
(2), in being placed on, establishes low-dimensional nano structure physics substrate template on the target of magnetic control sputtering device of noble metal target material; With feeding the inert gas argon gas in the magnetic control sputtering device; Thereby the bombardment noble metal target material is deposited on the low-dimensional nano structure physics substrate template after the noble metal nano particles that breaks away from noble metal target material synthesize behind the ionized inert gas, noble metal nano particles synthetic under the electrostatic field singular point effect in order compactness deposit to tip-shape structure (4) thus the tip on obtain one deck noble metal film;
(3), low-dimensional nano structure physics substrate template is carried out annealing process, thus finally obtain the wafer level low-dimensional nano structure.
2. the preparation method of the wafer level low-dimensional nano structure based on the self-focusing of electrostatic field singular point according to claim 1 is characterized in that: said magnetic control sputtering device adopts Qprep400-BASE type nanocluster depositing system.
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| CN103048308A (en) * | 2013-01-11 | 2013-04-17 | 中国科学院光电技术研究所 | Fabrication method of surface-enhanced Raman probe based on secondary enhancement |
| CN103934472A (en) * | 2014-04-10 | 2014-07-23 | 陕西师范大学 | Method for preparing silver micro-nano particles through annealing with assistance of electric field |
| CN110002393A (en) * | 2019-04-04 | 2019-07-12 | 中国科学院微电子研究所 | The preparation method of method for selective etching and nanometer pinpoint structure |
| CN111188006A (en) * | 2020-01-08 | 2020-05-22 | 电子科技大学 | Preparation method of micro-nano metal particles in periodic arrangement |
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