CN109941962A - A method of being electrically connected high density slope step nano wire - Google Patents
A method of being electrically connected high density slope step nano wire Download PDFInfo
- Publication number
- CN109941962A CN109941962A CN201910240844.6A CN201910240844A CN109941962A CN 109941962 A CN109941962 A CN 109941962A CN 201910240844 A CN201910240844 A CN 201910240844A CN 109941962 A CN109941962 A CN 109941962A
- Authority
- CN
- China
- Prior art keywords
- layer
- nano wire
- electrically connected
- high density
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 238000009616 inductively coupled plasma Methods 0.000 claims description 11
- 239000010409 thin film Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 10
- 230000012010 growth Effects 0.000 claims description 9
- 239000002243 precursor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000002082 metal nanoparticle Substances 0.000 claims description 7
- 230000003197 catalytic effect Effects 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000002207 thermal evaporation Methods 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 241000209094 Oryza Species 0.000 claims description 4
- 235000007164 Oryza sativa Nutrition 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910017817 a-Ge Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 235000009566 rice Nutrition 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000005030 aluminium foil Substances 0.000 claims description 3
- 229910000808 amorphous metal alloy Inorganic materials 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000012686 silicon precursor Substances 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 235000013339 cereals Nutrition 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 235000012149 noodles Nutrition 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 150000003503 terephthalic acid derivatives Chemical class 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 abstract description 4
- 238000003491 array Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- -1 Lan Bao Stone Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000007773 growth pattern Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- KUCOHFSKRZZVRO-UHFFFAOYSA-N terephthalaldehyde Chemical class O=CC1=CC=C(C=O)C=C1 KUCOHFSKRZZVRO-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
The invention discloses a kind of methods for being electrically connected high density slope step nano wire, using photoresist in alternately etching technics, it is different that local curvature's difference leads to move back erosion rate, to realize the step surface more much broader than low curvature (or straight) position in step higher curvature (both ends of such as band) position, so be conducive to easily prepare electrode on pace, it realizes and high density nanowire arrays on cliff is electrically connected respectively, the discrete nanowire field-effect device to realize high-density laminated provides great convenience.
Description
Technical field
The present invention relates to the method that high density slope step is obtained by cycle alternation etching technics more particularly to a kind of electricity
The method for learning connection high density slope step nano wire.
Background technique
Crystal silicon or related semiconductor nano wire (Nanowire) be develop of new generation High-performance micro-nano electronic logic, sensing and
Show the crucial construction unit of application.In order to preferably mutually compatible with plane electronics technique, and realize that positioning is integrated, the application hair
Bright people proposes a kind of plane solid-liquid earliest and consolidates (IP SLS) growth pattern: where using amorphous silicon as presoma, by eutectic
Point indium metal, tin nanoparticles absorb amorphous silicon and grow crystal silicon nanowire structure.Meanwhile using mask layer and substrate to quarter
The different etching response of gas is lost, multistage slope surface nanometer step can be prepared by the method that cycle alternation etches, with this three-dimensional
Step is as guidance, and molten drop is in the case where the amorphous silicon that step edge covers attracts, the step edge that postpones movement, thus by nanometer
Line is grown in step edge, realizes high density slope step nano-wire array.
It is difficult to apply in the problems in electronic device however, this high density nanowire arrays are but faced with.In micro-nano electricity
In sub- device, for the ease of the needs such as testing, encapsulating, metal electrode its size being electrically connected is realized with nanowire channel often
It is micron order, and the spacing for the slope step realized before this only has nanoscale, biggish size disparity often makes metal electrode
It cannot substantially and securely be connect with nano wire, this not only brings huge challenge to manufacturing process, while also reducing nanometer
Utilization rate of the line as channel, it is difficult to prepare the electronic device of high current, high integration.
Summary of the invention
Goal of the invention: the present invention proposes a kind of method for being electrically connected high density slope step nano wire, by exposure mask
The design of layer shape, i.e., short side curvature is larger and long side curvature is smaller, since mask layer etching gas is to the biggish short side of curvature
Spacing difference in length-width direction is formed in slope surface for the method for etching faster, thus can use cycle alternation etching and spacing can
The solid matter of control guides nanometer step, is so conducive to easily prepare electrode on pace, and high density on cliff is received in realization
Nanowire arrays are electrically connected respectively, and the discrete nanowire field-effect device to realize high-density laminated provides great convenience.
Technical solution:
A method of it being electrically connected high density slope step nano wire, comprising steps of
1) insulating medium layer of one layer of 200~1000nm thickness is deposited using PECVD or PVD process on substrate；
2) photoetching, electron-beam direct writing or mask plate technical definition step edge are utilized, keeps its short side curvature larger and grows
Side curvature is smaller；The insulating medium layer shape is etched using inductively coupled plasma etching or reactive ion body etching technics
At perpendicular steps side wall；Thickness of the etch thicknesses no more than the insulating medium layer；
3) a layer photoresist mask layer is covered at the top of the step, is performed etching by ICP etching technics；It is passed through again
SF6、C4F8、CF4Or Ar performs etching the silicon oxide dielectric layer of photoresist mask layer edge exposure；To above-mentioned two
Step carries out circulation etching several times, obtains multistage slope surface nanometer step, and the series of step is corresponding to the number of circulation etching；
4) in slope surface nanometer step one end, by photoetching, thermal evaporation process or sputtering technology, part deposits a layer thickness
For the band-like catalyzing metal layer of 20~100nm；Temperature to catalyzing metal layer fusing point or more is increased, reducibility gas plasma is passed through
Body is handled, and the catalyzing metal layer for being covered on described slope surface nanometer step one end is made to be changed into the metal nanoparticle of separation；
5) temperature is reduced to metal nanoparticle fusing point hereinafter, covering one layer and required life in total surface deposition
The long corresponding amorphous semiconductor precursor thin-film layer of nano wire；
6) in vacuum or the environment of inert gas shielding, catalytic metal fusing point or more is raised the temperature to, so that golden
Metal nano-particle refuse starts to absorb amorphous silicon layer in its front end, and deposits out the nano wire of crystalline state in rear end；It is described to receive
Rice noodles, as guidance channel Parallel Growth, obtain Parallel Growth and receive in the slope surface by the multi-stage stairs on slope surface nanometer step
Nano-wire array on meter Tai Jie；
7) remaining amorphous silicon precursor thin-film layer is removed by hydrogen gas plasma, ICP RIE etching technics；
8) at the slope surface nanometer step both ends, pattern is formed using photoetching or electron-beam direct writing, is then steamed using heat
Hair or sputtering technology deposit the discrete metal electrode of one layer of 50~200nm thickness, are formed reliably electric respectively to the nano wire
Learn connection.
In the step 1), the material of the substrate is crystal silicon, glass, aluminium foil, silicon nitride, silica, silicon carbide, Lan Bao
Stone, polyimides or poly terephthalic acid class plastics.
In the step 1), the insulating medium layer is with a thickness of 100~600nm.
In the step 1), the dielectric layer material is silica.
In the step 3), for the height of every grade of step in 1~1000 nanometer range, circulation etching number is 1~10；It is long
The spacing spent on direction is 2~3 times of width direction.
The catalytic metal is indium.
The precursor thin-film layer is amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy
Layer or heterogeneous laminated construction.
On the slope surface nanometer step, every layer of precursor thin-film layer cladding thickness is between 2~500nm.
The utility model has the advantages that 1) respond using mask layer and substrate to the different etching of etching gas, only pass through a photoetching+quarter
Etching technique can be etched by cycle alternation and obtain multistage slope surface nanometer step.Guidance nano wire be can be directly used in this slope surface
Upper Parallel Growth obtains density three-dimensional slope surface nanowire array structure；2) by the particular design of mask layer shape, using covering
Film layer etching gas realizes its higher curvature (both ends of such as band) position ratio to the difference of mask layer both direction etching speed
The much broader step surface in low curvature (or straight) position, then grows the nano wire for being parallel to step；3) slope step is long
Biggish spacing prepares metal electrode convenient for subsequent process on degree direction, this is the micro-nano electronics for realizing high integration, high current
Device provides possibility；4) electrode of discrete form takes full advantage of each nano wire, and the nano wire at one on step is no longer
It uses as a whole, since the number that the series of step can be etched by cycle alternation controls, thus this form has
Hope the integrated level for greatly improving device.
Detailed description of the invention
Fig. 1 is a kind of preparation flow schematic diagram for being electrically connected high density slope step nano wire provided by the invention.Its
In, Fig. 1 a substrate pre-treatment, Fig. 1 b deposits one layer of dielectric layer on substrate, and Fig. 1 c etch media layer forms perpendicular steps and covers
Mask layer, Fig. 1 d move back erosion technology and form multistage slope step, and the e step one end Fig. 1 deposits ribbon catalyzing metal layer, Fig. 1 f hydrogen etc.
Gas ions processing forms catalytic metal drop, and Fig. 1 g covers noncrystal precursor layer, and Fig. 1 h starts to grow nano wire, Fig. 1 i step two
End deposits discrete metal electrode.
Fig. 2 is that one kind provided by the invention is electrically connected high density slope step structure SEM schematic diagram.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated.
Fig. 1 is a kind of preparation flow schematic diagram for being electrically connected high density slope step nano wire provided by the invention.Such as
Shown in Fig. 1, the method for being electrically connected high density slope step nano wire of the invention, step includes:
1) (poly- with crystal silicon, glass, aluminium foil, silicon nitride, silica, silicon carbide, sapphire, PI (polyimides) or PET
Terephthaldehyde's acids plastics) it is used as substrate, the dielectric of one layer of 200~1000nm thickness is deposited using PECVD or PVD process
Layer；In the present invention, more optimal solution is the dielectric that one layer of 100~600nm thickness is deposited using PECVD or PVD process
Layer, the material of the insulating medium layer are silica, such as SiO2, Si3N4Deng；
2) photoetching, electron-beam direct writing or mask plate technical definition step edge are utilized, keeps its short side curvature larger and grows
Side curvature is smaller, this is conducive to subsequent step and forms the step appearance needed；Using inductively coupled plasma body (ICP) etching or
Person's reactive ion body etches (RIE) technique etch media layer and forms perpendicular steps side wall；Etch thicknesses are situated between no more than silica
Matter thickness degree；
3) a layer photoresist mask layer is covered at the top of step is passed through O in ICP etching technics2、Cl2Or and exposure mask
The corresponding etching gas of layer forms plasma, also can be in the horizontal direction to inside contracting while photoresist vertical direction is etched
It is retracted more into certain distance, and on the biggish short side direction of curvature, then passes to SF6、C4F8、CF4Or Ar is to photoresist
The silicon oxide dielectric layer of mask layer edge exposure performs etching；Such two steps cycle alternation carries out, gradually due to mask layer
It moves back and moves back erosion rate difference caused by erosion and local curvature's difference, it is larger and wide that length direction top bar spacing may finally be obtained
The small-pitch multistage slope surface nanometer step of direction top bar is spent, and the series of step is corresponding to the number of circulation etching；Every grade
For the height of step in 1~1000 nanometer range, cycle period can be 1~10；Width direction is spaced about on length direction
2~3 times；
4) in slope surface nanometer step one end, by photoetching, thermal evaporation process or sputtering technology, part deposits a layer thickness
For the band-like catalyzing metal layer of 20~100nm；Temperature to catalyzing metal layer fusing point or more is increased, the reduction such as hydrogen, ammonia is passed through
Property gaseous plasma is handled, and the metal for making the catalyzing metal layer for being covered on slope surface nanometer step one end be changed into separation is received
Rice grain；In the present invention, the catalytic metal is indium；
5) temperature is reduced to metal nanoparticle fusing point hereinafter, total surface deposition covers one layer and required growth
The corresponding amorphous semiconductor precursor thin-film layer of nano wire；The precursor thin-film layer is amorphous silicon a-Si, amorphous germanium a-Ge, non-
Brilliant carbon a-C or other amorphous alloy layers and heterogeneous lamination (such as a-Ge/a-Si) structure；On slope surface nanometer step, often
Layer film cladding thickness is between 2~500nm；
6) in vacuum or the environment of inert gas shielding, catalytic metal fusing point or more is raised the temperature to, so that golden
Metal nano-particle refuse starts to absorb amorphous silicon layer in its front end, and deposits out the nano wire of crystalline state in rear end；By slope
Multi-stage stairs on face obtain Parallel Growth in the nano-wire array on slope step as guidance channel；
7) remaining amorphous silicon precursor thin-film layer can be removed by hydrogen gas plasma, ICP RIE etching technics；By
It is greater than remaining noncrystal membrane precursor layer in slope surface in the nanowire diameter of slope step growth, general diameter is film thickness
2~3 times, and in ICP, RIE etching technics, the etch rate of amorphous layer is usually above the etching to crystalline state nano wire, therefore
Amorphous layer on slope step is selectively cleared；
8) at slope surface nanometer step both ends, form pattern using photoetching or electron-beam direct writing, then using thermal evaporation or
Person's sputtering technology deposits the discrete metal electrode of one layer of 50~200nm thickness, and formation is reliably electrically connected nano wire respectively.
The preferred embodiment of the present invention has been described above in detail, but during present invention is not limited to the embodiments described above
Detail can carry out a variety of equivalents to technical solution of the present invention (in full within the scope of the technical concept of the present invention
Amount, shape, position etc.), these equivalents belong to protection of the invention.
Claims (8)
1. a kind of method for being electrically connected high density slope step nano wire, it is characterised in that: comprising steps of
1) insulating medium layer of one layer of 200~1000nm thickness is deposited using PECVD or PVD process on substrate；
2) photoetching, electron-beam direct writing or mask plate technical definition step edge are utilized, makes that its short side curvature is larger and long side is bent
Rate is smaller；It is formed using inductively coupled plasma etching or the reactive ion body etching technics etching insulating medium layer vertical
Straight mesa sidewall；Thickness of the etch thicknesses no more than the insulating medium layer；
3) a layer photoresist mask layer is covered at the top of the step, is performed etching by ICP etching technics；It is passed through SF again6、
C4F8、CF4Or Ar performs etching the silicon oxide dielectric layer of photoresist mask layer edge exposure；To above-mentioned two stepping
Row circulation etching several times, obtains multistage slope surface nanometer step, and the series of step is corresponding to the number of circulation etching；
4) in slope surface nanometer step one end, by photoetching, thermal evaporation process or sputtering technology, it is 20 that part, which deposits a layer thickness,
The band-like catalyzing metal layer of~100nm；Increase temperature to catalyzing metal layer fusing point more than, be passed through reducibility gas plasma into
Row processing, makes the catalyzing metal layer for being covered on described slope surface nanometer step one end be changed into the metal nanoparticle of separation；
5) temperature metal nanoparticle fusing point is reduced to receive hereinafter, covering one layer in total surface deposition with required growth
The corresponding amorphous semiconductor precursor thin-film layer of rice noodles；
6) in vacuum or the environment of inert gas shielding, catalytic metal fusing point or more is raised the temperature to, so that metal is received
Rice grain refuse starts to absorb amorphous silicon layer in its front end, and deposits out the nano wire of crystalline state in rear end；The nano wire
By the multi-stage stairs on slope surface nanometer step as guidance channel Parallel Growth, Parallel Growth is obtained in the slope surface nanometer platform
Nano-wire array on rank；
7) remaining amorphous silicon precursor thin-film layer is removed by hydrogen gas plasma, ICP RIE etching technics；
8) at the slope surface nanometer step both ends, form pattern using photoetching or electron-beam direct writing, then using thermal evaporation or
Person's sputtering technology deposits the discrete metal electrode of one layer of 50~200nm thickness, is formed and reliably distinguishes the nano wire electricity company
It connects.
2. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: the step
It is rapid 1) in, the material of the substrate be crystal silicon, glass, aluminium foil, silicon nitride, silica, silicon carbide, sapphire, polyimides or
Person's poly terephthalic acid class plastics.
3. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: the step
It is rapid 1) in, the insulating medium layer is with a thickness of 100~600nm.
4. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: the step
It is rapid 1) in, the dielectric layer material be silica.
5. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: the step
It is rapid 3) in, the height of every grade of step in 1~1000 nanometer range, circulation etching number be 1~10；Spacing on length direction
It is 2~3 times of width direction.
6. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: described to urge
Change metal is indium.
7. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: before described
Drive thin-film layers are amorphous silicon a-Si, amorphous germanium a-Ge, amorphous carbon a-C or other amorphous alloy layers or heterogeneous lamination knot
Structure.
8. the method according to claim 1 for being electrically connected high density slope step nano wire, it is characterised in that: described
On slope surface nanometer step, every layer of precursor thin-film layer cladding thickness is between 2~500nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910240844.6A CN109941962B (en) | 2019-03-28 | 2019-03-28 | Method for electrically connecting high-density slope step nanowires |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910240844.6A CN109941962B (en) | 2019-03-28 | 2019-03-28 | Method for electrically connecting high-density slope step nanowires |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109941962A true CN109941962A (en) | 2019-06-28 |
| CN109941962B CN109941962B (en) | 2021-06-01 |
Family
ID=67012119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910240844.6A Active CN109941962B (en) | 2019-03-28 | 2019-03-28 | Method for electrically connecting high-density slope step nanowires |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109941962B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110767537A (en) * | 2019-11-05 | 2020-02-07 | 南京大学 | Method for preparing three-dimensional super-stretchable crystalline nanowire |
| CN113247860A (en) * | 2020-06-24 | 2021-08-13 | 南京大学 | Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure |
| CN113428832A (en) * | 2021-06-25 | 2021-09-24 | 杭州电子科技大学温州研究院有限公司 | High-density multi-modal neural microelectrode array and preparation and integration method thereof |
| CN113968571A (en) * | 2021-10-21 | 2022-01-25 | 南京大学 | Preparation method of anti-crosstalk self-limiting ultrafine close-packed crystal silicon nanowires |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040040683A (en) * | 2002-11-07 | 2004-05-13 | 삼성전자주식회사 | Method of processing exposure for semiconductor device fabrication |
| CN101208776A (en) * | 2005-05-27 | 2008-06-25 | 都柏林伊丽莎白女皇神学院 | Method of forming conducting nanowires |
| US20140327099A1 (en) * | 2013-05-06 | 2014-11-06 | Andrew J. Boudreau | Nanometer-scale level structures and fabrication method for digital etching of nanometer-scale level structures |
| CN108217591A (en) * | 2018-01-04 | 2018-06-29 | 南京大学 | A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN108878398A (en) * | 2017-05-16 | 2018-11-23 | 晟碟半导体（上海）有限公司 | Semiconductor devices including conductive bump interconnection |
| CN109496354A (en) * | 2018-10-18 | 2019-03-19 | 长江存储科技有限责任公司 | The method for forming the multi partition hierarchic structure of three-dimensional storage equipment |
-
2019
- 2019-03-28 CN CN201910240844.6A patent/CN109941962B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040040683A (en) * | 2002-11-07 | 2004-05-13 | 삼성전자주식회사 | Method of processing exposure for semiconductor device fabrication |
| CN101208776A (en) * | 2005-05-27 | 2008-06-25 | 都柏林伊丽莎白女皇神学院 | Method of forming conducting nanowires |
| US20140327099A1 (en) * | 2013-05-06 | 2014-11-06 | Andrew J. Boudreau | Nanometer-scale level structures and fabrication method for digital etching of nanometer-scale level structures |
| CN108878398A (en) * | 2017-05-16 | 2018-11-23 | 晟碟半导体（上海）有限公司 | Semiconductor devices including conductive bump interconnection |
| CN108217591A (en) * | 2018-01-04 | 2018-06-29 | 南京大学 | A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN109496354A (en) * | 2018-10-18 | 2019-03-19 | 长江存储科技有限责任公司 | The method for forming the multi partition hierarchic structure of three-dimensional storage equipment |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110767537A (en) * | 2019-11-05 | 2020-02-07 | 南京大学 | Method for preparing three-dimensional super-stretchable crystalline nanowire |
| CN113247860A (en) * | 2020-06-24 | 2021-08-13 | 南京大学 | Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure |
| CN113247860B (en) * | 2020-06-24 | 2022-06-21 | 南京大学 | Preparation method of embedded cross-surface growth three-dimensional nanowire spiral structure |
| CN113428832A (en) * | 2021-06-25 | 2021-09-24 | 杭州电子科技大学温州研究院有限公司 | High-density multi-modal neural microelectrode array and preparation and integration method thereof |
| CN113428832B (en) * | 2021-06-25 | 2024-02-02 | 杭州电子科技大学温州研究院有限公司 | High-density multi-mode nerve microelectrode array and preparation and integration methods thereof |
| CN113968571A (en) * | 2021-10-21 | 2022-01-25 | 南京大学 | Preparation method of anti-crosstalk self-limiting ultrafine close-packed crystal silicon nanowires |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109941962B (en) | 2021-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109941962A (en) | A method of being electrically connected high density slope step nano wire | |
| CN108557758B (en) | Method for growing nanowire array by guiding steps of circularly alternately etching homogeneous multistage slope surface | |
| CN108217591A (en) | A kind of method of heterogeneous alternative stacked step guiding growing three-dimensional slope surface nano-wire array | |
| CN109950393B (en) | Preparation method of nanowire cross point array resistive random access memory device structure capable of being prepared in stacked large area | |
| EP2319069A1 (en) | A method of growing a thin film, a method of forming a structure and a device. | |
| CN104995741A (en) | Recessed contact to semiconductor nanowires | |
| US20110089402A1 (en) | Composite Nanorod-Based Structures for Generating Electricity | |
| CN111312592B (en) | Preparation method of three-dimensional self-changing growth stacked nanowire channel and spring structure | |
| CN109650330A (en) | It is the preparation method that template realizes large-area graphene nano-band array based on programmable nano wire | |
| CN110767537A (en) | Method for preparing three-dimensional super-stretchable crystalline nanowire | |
| CN102354669A (en) | Production method of silicon nano-wire device | |
| CN103030097B (en) | Method for preparing wafer level low-dimensional nanostructures based on electrostatic field self-focusing | |
| CN102765695B (en) | Method of manufacturing wafer-level low-dimensional nano-structure based on self-focusing of electrostatic field singular-point | |
| Chen et al. | Fabrication of GaAs nanowires by colloidal lithography and dry etching | |
| TWI466816B (en) | Vertically oriented nanowires array structure and method thereof | |
| CN103715280B (en) | A kind of micrometer/nanometer secondary array structure thin film solar cell and preparation method thereof | |
| CN104538476A (en) | Silicon nano-wire suede based heterojunction solar battery and preparation method thereof | |
| CN109911847A (en) | A method of it is discharged by transfer and obtains high density nanowire arrays | |
| CN106328750B (en) | A kind of core shell structure heterojunction solar battery based on chalcogen cuprous compound and preparation method thereof | |
| CN108028290A (en) | Photo-electric conversion element includes the solar module and photovoltaic power generation system of the photo-electric conversion element | |
| CN104254925B (en) | The forming method of zinc oxide concaveconvex structure and utilize its manufacture method of solaode | |
| US7759150B2 (en) | Nanorod sensor with single-plane electrodes | |
| CN106486560B (en) | Plasma drop epitaxial GaAs quantum dot solar battery and its manufacturing method | |
| CN113173557A (en) | Preparation method of vertical nanowire array | |
| CN103107065A (en) | Nanowire device preparation method based on nanowire ordered arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |