CN102751243B - Semiconductor device and manufacture method of semiconductor device - Google Patents
Semiconductor device and manufacture method of semiconductor device Download PDFInfo
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- CN102751243B CN102751243B CN201110101177.7A CN201110101177A CN102751243B CN 102751243 B CN102751243 B CN 102751243B CN 201110101177 A CN201110101177 A CN 201110101177A CN 102751243 B CN102751243 B CN 102751243B
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Abstract
The invention discloses a semiconductor device and a manufacture method of the semiconductor device. The semiconductor device comprises a substrate, a first semiconductor element and a second semiconductor element, wherein the first semiconductor element is a memory, the second semiconductor element comprises a metal oxide semiconductor, a capacitor or a resistor, and the first semiconductor element and the second semiconductor element are formed on the single substrate. The manufacture method of the semiconductor device disclosed by the invention is simple, and in addition, the cost is low. In addition, good electric connection can be realized between the memory and the metal oxide semiconductor.
Description
Technical field
The invention relates to semiconductor device and manufacture method thereof, relate to especially metal-oxide semiconductor (MOS) and memory and manufacture method thereof.
Background technology
In semiconductor device, for instance, can need metal-oxide semiconductor (MOS) and memory simultaneously.Metal-oxide semiconductor (MOS) in semiconductor device is generally the technique of separating with memory, is respectively formed on different substrates.In encapsulation process, utilize routing that the metal-oxide semiconductor (MOS) on different substrates and memory are electrically connected.Therefore, the complex process of semiconductor device and cost are high.In addition, the fault rate being electrically connected between metal-oxide semiconductor (MOS) and memory can be higher, and poor effect.
Summary of the invention
The invention relates to a kind of semiconductor device and manufacture method thereof.Compared to general technology, the manufacture method of the semiconductor device of embodiment is simple and cost is low.In addition, for instance, between memory and metal-oxide semiconductor (MOS), can there is good electric connection.
A kind of manufacture method of semiconductor device is provided.Method is included in and on substrate, forms the first semiconductor element and the second semiconductor element.Substrate is single.The first semiconductor element is memory.The second semiconductor element comprises metal-oxide semiconductor (MOS), electric capacity or resistance.
A kind of semiconductor device is provided.Semiconductor device comprises substrate, the first semiconductor element and the second semiconductor element.The first semiconductor element is memory.The second semiconductor element comprises metal-oxide semiconductor (MOS), electric capacity or resistance.The first semiconductor element and the second semiconductor element are formed on single substrate.
Preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below:
Brief description of the drawings
Fig. 1 illustrates according to the profile of the semiconductor device of an embodiment.
Fig. 2 to Figure 20 illustrates according to the manufacture method of the semiconductor device of an embodiment.
Figure 21 illustrates according to the semiconductor device of an embodiment and manufacture method thereof.
[main semiconductor element symbol description]
2,102: substrate
4,104,204: the first substrate zones
6,8,10,12,106,108,110,112: the second substrate zones
14,50,114,150: the three doped regions
16,116,216: the first doped regions
18,54,58,78,118,154,158,178,218: the second doped regions
20,120,220: the first dielectric layers
22,36,46,122,127,136,146,222: the second dielectric layers
24: dielectric structure
26,38,44,126,129,138,144: the first electrode layers
28,64,66,76,82,128,164,166,176,182: bag doped region
30,40,42,48,62,74,130,133,142,148,162,174: clearance wall
32,132: dielectric element
34,134,234,288: the second electrode lay
52,152: the four doped regions
56,68,70,84,86,107,111,113,117,137,156,168,170,184,186: doped region
60,72,80,160,172,180,260,272,280: grid structure
103,109,119,121,123,125,131,135: photoresist layer
115: film
139: interlayer dielectric
141: conductive plunger
143: conductive layer
Embodiment
Fig. 1 illustrates according to the profile of the semiconductor device of an embodiment.Please refer to Fig. 1, substrate 2 comprises the first different substrate zones 4 and the second substrate zone 6, the second substrate zone 8, the second substrate zone 10 and the second substrate zone 12.In embodiment, substrate 2 is single.In addition, the first semiconductor element is configured on the first substrate zone 4.For instance, the second different semiconductor elements is configured in respectively on the second substrate zone 6, the second substrate zone 8, the second substrate zone 10 and the second substrate zone 12.
Please refer to Fig. 1, the first semiconductor element on the first substrate zone 4 comprises the 3rd doped region 14, is disposed in substrate 2.The first doped region 16 is disposed in the 3rd doped region 14.The second doped region 18 is disposed in the first doped region 16.For instance, comprise that the dielectric structure 24 of the first dielectric layer 20 and the second dielectric layer 22 is disposed on the first doped region 16 between the second doped region 18, and extend on the second doped region 18.The first electrode layer 26 is disposed on dielectric structure 24.Configuration bag doped region 28.Configuration clearance wall 30 is on the sidewall of dielectric structure 24 and the first electrode layer 26.For instance, substrate 2, the first 16Yu Dai doped region, doped region 28 have for example P conductivity type of the first conductivity type.The 3rd doped region 14 and the second doped region 18 have for example N conductivity type of the second conductivity type in contrast to the first conductivity type.In embodiment, the first semiconductor element on the first substrate zone 4 is memory.For instance, the second doped region 18 is as bit line.The first electrode layer 26 is as word line.
Please refer to Fig. 1, the second semiconductor element on the second substrate zone 6 comprises dielectric element 32, is disposed on substrate 2.The second electrode lay 34 is disposed on dielectric element 32.The second dielectric layer 36 is disposed on the second electrode lay 34.The first electrode layer 38 is disposed on the second dielectric layer 36.The second electrode lay 34, the second dielectric layer 36 and the first electrode layer 38 can form electric capacity.Clearance wall 40 is configurable on the sidewall of the second electrode lay 34.Clearance wall 42 is configured on the sidewall of the second dielectric layer 36 and the first electrode layer 38.The first electrode layer 44 is disposed in the part that substrate 2 do not cover by the second electrode lay 34.In embodiment, the first electrode layer 44 is as resistance.The second dielectric layer 46 is configured between dielectric element 32 and the first electrode layer 44.Clearance wall 48 is configured on the first electrode layer 44 and the second dielectric layer 46.
Please refer to Fig. 1, the second semiconductor element on the second substrate zone 8 comprises the 3rd doped region 50, is disposed in substrate 2.The 4th doped region 52 is configured in the 3rd doped region 50.The second doped region 54 is configured in the 4th doped region 52.Doped region 56 is configured in the 3rd doped region 50.The second doped region 58 is configured in doped region 56.Grid structure 60 is configured on the 3rd doped region 50 and the 4th doped region 52.Clearance wall 62 is configured on the sidewall of grid structure 60.Configuration bag 64Yu Dai doped region, doped region 66.For instance, the 4th doped region 52, bag doped region 64, bag doped region 66 have for example P conductivity type of the first conductivity type.The 3rd doped region 50, the second doped region 54, the second doped region 58 have for example N conductivity type of the second conductivity type in contrast to the first conductivity type.Doped region 56 can have P conductivity type or N conductivity type.In embodiment, the second semiconductor element on the second substrate zone 8 is metal-oxide semiconductor (MOS) (MOS), for example 85V lateral double diffusion metal oxide semiconductor (LateralDouble-diffused MOS; LDMOS).
Please refer to Fig. 1, the second semiconductor element on the second substrate zone 10 comprises doped region 68, is configured in substrate 2.Doped region 70 is configured in doped region 68.Grid structure 72 is configured on doped region 68.Clearance wall 74 is configurable on the sidewall of grid structure 72.Also configuration bag doped region 76.The second semiconductor element on the second substrate zone 12 comprises the second doped region 78, is configured in substrate 2.Grid structure 80 is configured on the substrate 2 between the second doped region 78.Configuration bag doped region 82.Doped region 68 is configurable on doped region 86 with doped region 84.For instance, doped region 70Yu Dai doped region 82 has for example P conductivity type of the first conductivity type.Bag doped region 68, bag doped region 76, the second doped region 78, doped region 84 have for example N conductivity type of the second conductivity type in contrast to the first conductivity type with doped region 86.In embodiment, being formed on the second substrate zone 10 is respectively the MOS of phase transoid with the second semiconductor element on the second substrate zone 12, and for example low pressure (LV) is if the PMOS of 5V and LV are as the NMOS of 5V.
Fig. 2 to Figure 20 illustrates according to the manufacture method of the semiconductor device of an embodiment.Please refer to Fig. 2, substrate 102 is provided.Substrate 102 comprises the first substrate zone 104 and the second substrate zone 106, the second substrate zone 108, the second substrate zone 110 and the second substrate zone 112.Utilize gold-tinted photoetching process on substrate 102, to form photoresist layer 103.The for example antimony of substrate 102 implanted dopants (Sb) that photoresist layer 103 is exposed to form doped region 186 in substrate 102.Please refer to Fig. 3, remove photoresist layer 103.Can carry out annealing steps with diffusing, doping district 186.In an embodiment, can carry out cleaning step removing between photoresist layer 103 and annealing steps.
Please refer to Fig. 4, to for example boron of substrate 102 implanted dopants (boron) so that contrary conductivity type is caused in the region of substrate 102 beyond doped region 186.Deposit or epitaxial growth step to form film on substrate 102.In an embodiment, for example form, between step (extension or deposition step) at implantation step and film, carry out cleaning step.
Please refer to Fig. 5, in substrate 102, form the 3rd doped region 114 and the 3rd doped region 150.In an embodiment, be that cleaning step is carried out in the surface of substrate 102, then form pad oxide (pad oxide) on the surface of substrate 102.Utilize gold-tinted photoetching process on substrate 102, to form the photoresist layer of patterning.The for example phosphorus of substrate 102 implanted dopants (phosphorus) that the photoresist layer of patterning is exposed to form the 3rd doped region 114 and the 3rd doped region 150 simultaneously in substrate 102.Remove substrate 102 capable of washing after photoresist layer.Carry out annealing steps to spread the 3rd doped region 114 and the 3rd doped region 150.
Please refer to Fig. 6, in substrate 102, form doped region 168 and doped region 184.In the 3rd doped region 150, form doped region 107.In an embodiment, be that cleaning step is carried out in the surface of substrate 102, then form pad oxide (pad oxide) on the surface of substrate 102.Utilize gold-tinted photoetching process on substrate 102, to form the photoresist layer of patterning.The substrate 102 that the photoresist layer of patterning is exposed and the 3rd for example phosphorus of doped region 150 implanted dopants (phosphorus) are to form doped region 168, doped region 184 and doped region 107 simultaneously.Then remove photoresist layer.Please refer to Fig. 7, utilize gold-tinted photoetching process on substrate 102, to form photoresist layer 109.The for example boron of substrate 102 implanted dopants (boron) that photoresist layer 109 is exposed to form doped region 111, doped region 113, doped region 156 and the first doped region 116 in substrate 102.Then remove photoresist layer 109.
Please refer to Fig. 8, diffusing, doping district 111, doped region 113, doped region 156, the first doped region 116, doped region 184 and doped region 168.In addition, on substrate 102, form film 115.Film 115 can comprise the silicon nitride layer on pad oxide and pad oxide.In an embodiment, before forming film 115, clean the surface of substrate 102.Then carry out annealing steps with diffusing, doping district 111, doped region 113, doped region 156, the first doped region 116, doped region 184 and doped region 168.After cleaning the surface of substrate 102, form pad oxide, and on pad oxide deposited silicon nitride layer, to form film 115.Utilize gold-tinted photoetching process to form the photoresist layer of patterning, etching removes the film 115 that the photoresist layer of patterning exposes.Then remove the photoresist layer of patterning.
Please refer to Fig. 9, in substrate 102, form doped region 117.In an embodiment, be to utilize gold-tinted photoetching process on substrate 102, to form the photoresist layer of patterning.The for example boron of substrate 102 implanted dopants (boron) that the photoresist layer of patterning is exposed are to form doped region 117.After implantation step, remove the photoresist layer of patterning.On the substrate 102 exposing at film 115, form for example field oxide of dielectric element 132 as shown in figure 10, and remove film 115.In an embodiment, be to form dielectric element 132 after the surface of cleaning substrate 102.After removing film 115, clean the surface of substrate 102, and form sacrificial oxide layer on substrate 102.Utilizing gold-tinted photoetching process to form after photoresist layer 119, for example boron of substrate 102 implanted dopants (boron) that photoresist layer 119 is exposed, so that doped region 111 has enough p type impurities.In an embodiment, after this doping step, doped region 168 still maintains has the conductivity type contrary with doped region 111, for example N conductivity type.Remove photoresist layer 119.
Please refer to Figure 11, on substrate 102, form the second electrode lay 134, grid structure 160, grid structure 172 and grid structure 180.In an embodiment, be after the surface of cleaning substrate 102, sequentially form from the bottom to top such as tungsten silicide of oxide layer, polysilicon and metal silicide.Then etch away and be not utilized part that the photoresist layer of patterning that gold-tinted photoetching process forms covers to form the second electrode lay 134, grid structure 160, grid structure 172 and grid structure 180 as shown in figure 11.The second electrode lay 134 can comprise polysilicon and metal silicide.Between the second electrode lay 134 and 132, also can there is oxide layer.Remove the photoresist layer of patterning.
Please refer to Figure 12, utilize gold-tinted photoetching process on substrate 102, to form photoresist layer 121.The for example boron of substrate 102 implanted dopants (boron) that photoresist layer 121 is exposed to form doped region 152 in 150.Remove photoresist layer 121.Please refer to Figure 13, utilize gold-tinted photoetching process on substrate 102, to form photoresist layer 123.The for example phosphorus of substrate 102 implanted dopants (phosphorus) that photoresist layer 123 is exposed to form the second doped region 118, doped region simultaneously in the first doped region 116, in the 4th doped region 152, form the second doped region 154, doped region, in doped region 156, form the second doped region 158, doped region, and in doped region 111, form the second doped region 178, doped region.Please refer to Figure 13, utilize inclination angle (tilt) with rotation (rotate) inject mode impurity for example boron with form simultaneously bag doped region 128, bag doped region 164, bag 166Yu Dai doped region, doped region 182.Remove photoresist layer.
Please refer to Figure 14, on the first doped region 116, form the first dielectric layer 120.In an embodiment, the formation method of the first dielectric layer 120 is included in and on substrate 102, conformally forms from the bottom to top for example thickness approximately 50 dusts of oxide layer and for example thickness approximately 120 dusts of silicon nitride layer.Oxide layer can dry process form.After utilizing gold-tinted photoetching process formation photoresist layer 125, etching removes silicon nitride layer and the partial oxidation layer that photoresist layer 125 exposes, and for instance, leaves the oxide layer of thickness approximately 20 dusts.Forming before oxide layer, mode that can wet etching erosion removes the oxide on substrate 102.Remove photoresist layer 125.
Please refer to Figure 15, can on substrate 102, be conformally formed the second dielectric layer 127 and the first electrode layer 129.Can thermal oxidation mode deposit the second dielectric layer 127.Also method that can wet type forms the second dielectric layer 127.In an embodiment, the thickness of the second dielectric layer 127 approximately 300 dusts.The mode that can deposit forms the first electrode layer 129, comprises polysilicon (polycide).Also can carry out resistance injection (HR-IMP) to the first electrode layer 129.The thickness of the first electrode layer 129 is about 2000 dusts.
Please refer to Figure 16, utilize gold-tinted photoetching process on substrate 102, to form photoresist layer 131.The such as phosphorus of substrate 129 implanted dopants that photoresist layer 131 is exposed, the about E15/cm of dosage
2.Remove photoresist layer 131.In an embodiment, utilizing after gold-tinted photoetching process forms the photoresist layer of patterning on substrate 102, carry out etch step to remove the second dielectric layer 127 that photoresist layer was exposed and first electrode layer 129 of patterning, as shown in figure 17, form the second dielectric layer 122 and the first electrode layer 126, the second dielectric layer 146 and the first electrode layer 144 simultaneously, and the second dielectric layer 136 and the first electrode layer 138.For instance, can leave the oxide layer of thickness approximately 100 dusts.After removing the photoresist layer of patterning, can carry out metal silicide annealing steps.
Please refer to Figure 18, can form clearance wall 130, clearance wall 133, clearance wall 142, clearance wall 148, clearance wall 162 and clearance wall 174 simultaneously.In addition, form in 170Yu doped region, doped region 168, and form doped region 137 in the 4th doped region 152 and 154.Clearance wall 130, clearance wall 133, clearance wall 142, clearance wall 148, clearance wall 162 can be included in for example tetraethyl silica alkane (Tetraethoxysilane of deposited oxide layer on substrate 102 with the formation method of clearance wall 174; TEOS), then utilize etching method to remove the oxide layer of part.Doped region 170 comprises and utilizes gold-tinted photoetching process on substrate 102, to form photoresist layer 135 with the formation method of doped region 137, the such as boron of substrate 102 implanted dopants then photoresist layer 135 being exposed.Please refer to Figure 18, utilize inclination angle (tilt) with rotation (rotate) inject mode impurity for example phosphorus with form bag a doped region 176.Remove photoresist layer.
Please refer to Figure 19, on substrate 102, form the interlayer dielectric 139 with opening.For instance, the formation method of interlayer dielectric 139 comprises deposition boron-phosphorosilicate glass (BPSG).Utilizing after gold-tinted photoetching process forms the photoresist layer of patterning, utilize etching technics to remove the part that photoresist layer that interlayer dielectric 139 is not patterned covers, to form opening.In some embodiment, before deposition interlayer dielectric 139, can carry out cleaning step to substrate 102.After forming opening, remove the photoresist layer of patterning.Please refer to Figure 20, form conductive plunger 141 in the opening of interlayer dielectric 139.Also form conductive layer 143 in interlayer dielectric 139.Conductive plunger 141 comprises metal.In an embodiment, be on the sidewall of the opening of interlayer dielectric 139, form barrier layer after, carry out rapid thermal anneal step, then fill in opening with chemical vapour deposition technique metal for example tungsten to form conductive plunger 141.
In embodiment, for the technique of the first semiconductor element of memory be with in order to form the second semiconductor element two-carrier-complementary metal oxide semiconductors (CMOS) conductor of (comprising metal-oxide semiconductor (MOS) for example LDMOS, DMOS, CMOS or two-carrier MOS)-dual diffused metal oxide emiconductor conductor (Bipolar-CMOS-DMOS; BCD) process integration becomes a continuous flow process together.In other embodiment, also can combine and become a continuous flow process with logic process in order to the technique that forms memory.The first semiconductor element and the second semiconductor element are formed on single substrate.Therefore the low cost of manufacture of semiconductor device, and can there is good electric connection between the first semiconductor element and the second semiconductor element.
Figure 21 illustrates according to the semiconductor device of an embodiment and manufacture method thereof.The difference of the semiconductor device that the semiconductor device that Figure 21 illustrates and Fig. 1 illustrate is, the second electrode lay 288 is formed on the first doped region 216 between the second doped region 218.The first dielectric layer 220 is formed between the second electrode lay 288 and the second dielectric layer 222.The second dielectric layer 222 is formed on the upper surface of the first dielectric layer 220, and extends on the sidewall of the first dielectric layer 220 and the second electrode lay 288.In embodiment, the second electrode lay 288 can form together with grid structure 280 with the second electrode lay 234, grid structure 260, grid structure 272 simultaneously.In an embodiment, the first semiconductor element being formed on the first substrate zone 204 is flash memory.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on the claim scope of enclosing.
Claims (9)
1. a manufacture method for semiconductor device, comprising:
On a substrate, form one first semiconductor element and one second semiconductor element, wherein this first semiconductor element and this second semiconductor element are formed on single substrate, this substrate comprises one first different substrate zones and one second substrate zone, this first semiconductor element is formed on this first substrate zone, this second semiconductor element is formed on this second substrate zone, this first semiconductor element is memory, and this second semiconductor element comprises metal-oxide semiconductor (MOS), electric capacity or resistance;
Wherein, the formation method of this first semiconductor element comprises:
Form one first doped region in this substrate, wherein this first doped region has one first conductivity type;
Form multiple the second doped regions separated from each other in this first doped region, wherein this second doped region has one second conductivity type in contrast to this first conductivity type;
Form a dielectric structure on this first doped region between those second doped regions; And
Form one first electrode layer on this second doped region and this dielectric structure.
2. the manufacture method of semiconductor device according to claim 1, wherein the technique of this first semiconductor element is together with the two-carrier-complementary metal oxide semiconductors (CMOS) conductor-dual diffused metal oxide emiconductor conductor process integration with in order to form this second semiconductor element.
3. the manufacture method of semiconductor device according to claim 1, wherein the formation method of this second semiconductor element comprises:
Form those second doped regions separated from each other in this substrate, wherein those second doped regions of this first semiconductor element and those second doped regions of this second semiconductor element form simultaneously; And
Form a grid structure on this substrate between those second doped regions.
4. the manufacture method of semiconductor device according to claim 1, wherein the formation method of this second semiconductor element comprises:
Form a dielectric element on this substrate;
Form a second electrode lay on this dielectric element;
Form one second dielectric layer on this second electrode lay, wherein this second dielectric layer of this first semiconductor element and this second dielectric layer of this second semiconductor element form simultaneously; And
Form this first electrode layer on this second dielectric layer, wherein this first electrode layer of this first semiconductor element and this first electrode layer of this second semiconductor element form simultaneously.
5. the manufacture method of semiconductor device according to claim 4, wherein the formation method of this second semiconductor element more comprises: in the part that formation one resistance is not covered by this second electrode lay in this substrate, wherein this first electrode layer of this first semiconductor element and this resistance of this second semiconductor element form simultaneously.
6. the manufacture method of semiconductor device according to claim 1, wherein the formation method of this first semiconductor element more comprises: form one the 3rd doped region in this substrate, wherein this first doped region is to be formed in the 3rd doped region, this substrate has this first conductivity type, and the 3rd doped region has this second conductivity type.
7. the manufacture method of semiconductor device according to claim 6, wherein the formation method of this second semiconductor element comprises:
Form the 3rd doped region in this substrate, wherein the 3rd doped region of this first semiconductor element and the 3rd doped region of this second semiconductor element form simultaneously;
Form one the 4th doped region in the 3rd doped region, wherein the 4th doped region has this first conductivity type;
Form this second doped region in the 4th doped region, wherein this second doped region of this first semiconductor element and this second doped region of this second semiconductor element form simultaneously; And
Form a grid structure on the 3rd doped region and the 4th doped region.
8. the manufacture method of semiconductor device according to claim 1, wherein forms a dielectric structure on this first doped region between those second doped regions; And formation one first electrode layer can be replaced by this dielectric structure:
Form a second electrode lay on this first doped region between those second doped regions;
Form a dielectric structure on this second electrode lay; And
Form one first electrode layer on this dielectric structure, this second electrode lay and this second doped region.
9. a semiconductor device, comprising:
One substrate;
One first semiconductor element, wherein this first semiconductor element is memory; And
One second semiconductor element, wherein this second semiconductor element comprises metal-oxide semiconductor (MOS), electric capacity or resistance, this first semiconductor element and this second semiconductor element are formed on single this substrate, this substrate comprises one first different substrate zones and one second substrate zone, this first semiconductor element is formed on this first substrate zone, and this second semiconductor element is formed on this second substrate zone;
Wherein, this first semiconductor element comprises:
Be formed at one first doped region in this substrate, this first doped region has one first conductivity type;
Be formed at multiple the second doped regions separated from each other in this first doped region, this second doped region has one second conductivity type in contrast to this first conductivity type;
Be formed at the dielectric structure on this first doped region between these second doped regions; And
Be formed at one first electrode layer on this second doped region and this dielectric structure.
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| CN106876337B (en) * | 2017-01-04 | 2019-01-29 | 宗仁科技(平潭)有限公司 | NLDMOS integrated device and preparation method thereof |
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