TWI585951B - Memory structure - Google Patents

Description

Memory structure

The present invention relates to a semiconductor device structure, and more particularly to a memory structure.

Memory is a semiconductor component used to store information or data. It is widely used in personal computers, mobile phones, and the Internet. It has become an indispensable electronic product in life. As the functions of computer microprocessors become stronger and stronger, the programs and operations performed by software are also increased, and the storage of various data is increasing, so the capacity requirements of memory are becoming higher and higher.

Under the current trend of miniaturization of memory components, the industry actively promotes the accumulation of memory components in a limited space, which in turn makes the structure and process of memory components increasingly complex. Therefore, in the fabrication process of the memory device, it is often necessary to use a plurality of photomasks to complete the fabrication of the memory component, thereby causing a substantial increase in manufacturing cost.

The invention provides a memory structure, which has a simple structure and a low process complexity, thereby effectively reducing manufacturing costs.

The present invention provides a memory structure including a substrate, a selective gate structure, a first heavily doped region, a second heavily doped region, and a floating contact window. The gate structure is selected to be disposed on the substrate. The first heavily doped region and the second heavily doped region are respectively disposed in the substrate on one side and the other side of the selective gate structure. The floating contact window is disposed on the substrate between the first heavily doped region and the selected gate structure, and is isolated from the substrate.

According to an embodiment of the invention, in the memory structure, selecting a gate structure includes selecting a gate and a dielectric layer. The selection gate is disposed on the substrate. The dielectric layer is disposed between the selection gate and the substrate.

According to an embodiment of the invention, in the above memory structure, the top surface of the floating contact window is, for example, higher than the top surface of the selective gate structure.

In accordance with an embodiment of the invention, in the memory structure described above, the floating contact window is, for example, traversing the active area.

According to an embodiment of the invention, in the above memory structure, the floating contact window and the substrate, for example, do not have a metal telluride layer.

According to an embodiment of the invention, in the memory structure described above, a dielectric structure is further included. A dielectric structure is disposed between the floating contact window and the substrate to isolate the floating contact window from the substrate.

According to an embodiment of the invention, in the above memory structure, the dielectric structure may be a single layer structure or a multilayer structure.

According to an embodiment of the invention, in the memory structure, the first lightly doped region is further included. The first lightly doped region is disposed in the substrate between the first heavily doped region and the selected gate structure.

According to an embodiment of the invention, in the memory structure, the second lightly doped region is further included. The second lightly doped region is disposed in the substrate between the second heavily doped region and the selected gate structure.

According to an embodiment of the invention, in the memory structure, the first contact window is further included. The first contact window is electrically connected to the first heavily doped region.

According to an embodiment of the present invention, in the memory structure, the first interconnect structure and the second interconnect structure are further included. The first interconnect structure is electrically connected to the first contact window. The second interconnect structure is electrically connected to the floating contact window.

According to an embodiment of the present invention, in the memory structure, the first interconnect structure located on the side of the second interconnect structure may be located on one side of the second interconnect structure and located in the second The sides of the wiring structure or surround the second interconnect structure.

According to an embodiment of the invention, in the memory structure, a portion of the first interconnect structure may be located above the second interconnect structure.

According to an embodiment of the invention, in the memory structure, a second contact window is further included. The second contact window is electrically connected to the second heavily doped region.

According to an embodiment of the invention, in the memory structure, the memory structure can be used as an OTP memory, a multi-programmable memory (MTP memory) or a flash memory. Flash memory.

Based on the above, since the memory structure proposed by the present invention uses a floating contact window for storing the electric charge, the memory structure has a simple structure and can be formed by a simple process, thereby effectively reducing the manufacturing cost.

The above described features and advantages of the invention will be apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a structure of a memory according to a first embodiment of the present invention. 2 is a schematic view of the floating contact window and the active area of FIG. 1. Figure 3 is a cross-sectional view showing the structure of a memory according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a memory according to a third embodiment of the present invention.

Referring to FIG. 1 , the memory structure 100 includes a substrate 102 , a selective gate structure 104 , a heavily doped region 106 , a heavily doped region 108 , and a floating contact window 110 . The memory structure 100 can be used as a one-time programmable memory, multiple programmable memory or flash memory. The substrate 102 is, for example, a semiconductor substrate such as a germanium substrate or the like.

The select gate structure 104 is disposed on the substrate 102. The select gate structure 104 includes a select gate 112 and a dielectric layer 114 and may further include a spacer 116. The selection gate 112 is disposed on the substrate 102. The material of the gate 112 is selected, for example, as a conductor material such as doped polysilicon. The method of forming the gate 112 is, for example, a chemical vapor deposition method. The dielectric layer 114 is disposed between the selection gate 112 and the substrate 102 and can be used as a gate dielectric layer. The material of the dielectric layer 114 is, for example, ruthenium oxide. The method of forming the dielectric layer 114 is, for example, a thermal oxidation method. The spacers 116 are disposed on the sidewalls of the selection gate 112. The material of the spacers 116 is, for example, tantalum nitride. The method for forming the spacers 116 is formed by first forming a spacer material layer (not shown) covering the selection gate 112, and then performing an etch back process on the spacer material layer.

The heavily doped regions 106, 108 are respectively disposed in the substrate 102 on one side of the selection gate structure 104 and on the other side. The heavily doped regions 106, 108 may each be an N-type heavily doped region or a P-type heavily doped region. In this embodiment, the heavily doped regions 106, 108 are described by taking an N-type heavily doped region as an example. The method of forming the heavily doped regions 106, 108 is, for example, an ion implantation method.

The floating contact window 110 is disposed on the substrate 102 between the heavily doped region 106 and the select gate structure 104 and is isolated from the substrate 102. The floating contact window 110 can be used to store charge. Since the memory structure 100 uses the floating contact window 110 for charge storage, the memory structure 100 has a simple structure and can be formed by a simple process, thereby effectively reducing manufacturing costs. The top surface of the floating contact window 110 is, for example, higher than the top surface of the select gate structure 104. For example, since the floating contact window 110 and the substrate 102 do not have a metal telluride layer, the charge is not captured by the metal telluride layer, and the operation of the memory can be performed efficiently. In addition, referring to FIG. 2, the floating contact window 110 is, for example, traversing the active area AA, thereby preventing leakage current from being generated. The material of the floating contact window 110 is, for example, a conductor material such as a metal such as tungsten or a doped polysilicon. In this embodiment, the material of the floating contact window 110 is exemplified by tungsten. The method of forming the floating contact window 110 is, for example, a damascene method.

In addition, referring to FIG. 1 , the memory structure 100 further selectively includes a lightly doped region 118 , a lightly doped region 120 , a dielectric structure 122 , a dielectric layer 124 , a contact etch stop layer (CESL ) 126 , and At least one of the electrical layer structure 128, the metal telluride layers 130a-130c, the contact window 132, the contact window 134, the barrier layers 136a-136c, and the metal interconnects 138, 140, 142.

Lightly doped region 118 is disposed in substrate 102 between heavily doped region 106 and select gate structure 104. The lightly doped region 120 is disposed in the substrate 102 between the heavily doped region 108 and the select gate structure 104. The doping concentration and depth of the lightly doped regions 118, 120 are, for example, less than the doping concentration and depth of the heavily doped regions 106, 108. The lightly doped regions 118, 120 can be N-type lightly doped regions or P-type lightly doped regions. In this embodiment, the lightly doped regions 118 and 120 are described by taking an N-type lightly doped region as an example. The method of forming the lightly doped regions 118, 120 is, for example, an ion implantation method.

The dielectric structure 122 is disposed between the floating contact window 110 and the substrate 102 and can be used to isolate the floating contact window 110 from the substrate 102. The dielectric structure 122 can be a single layer structure or a multilayer structure. In this embodiment, the dielectric structure 122 is exemplified by a single layer atomic layer deposition (ALD) ruthenium oxide layer, but the invention is not limited thereto. In other embodiments, the dielectric structure 122 can also be a multi-layer structure. Those skilled in the art can adjust the number and type of dielectric structures 122 based on reliability and manufacturing cost considerations.

Hereinafter, different aspects of the dielectric structure will be described in comparison with the embodiments of FIGS. 1, 3 and 4, but the invention is not limited thereto. In the memory structure 100a of FIG. 3 and the memory structure 100b of FIG. 4, the materials, arrangement, and efficacy of the components similar to the memory structure 100 of FIG. 1 are described with reference to the embodiment of FIG. This will not be repeated here.

Referring to FIG. 1, a method of forming the dielectric structure 122 includes the following steps. A contact opening 110a is formed through the dielectric layer structure 128, the contact etch stop layer 126 and the dielectric layer 124, wherein the contact opening 110a is for forming the floating contact window 110. Next, a dielectric structure 122 is formed in the contact opening 110a. In the embodiment of FIG. 1, since the dielectric structure 122 is formed after the contact opening 110a is formed, reliability is preferred. In addition, dielectric structures 122 are also formed in contact openings 132a, 134a, respectively. Thus, in contrast to the embodiment of FIGS. 3 and 4, the embodiment of FIG. 1 is configured to electrically connect the contact windows 132, 134 subsequently formed in the contact openings 132a, 134a to the heavily doped regions 106, 108, respectively. Thus, a reticle process is performed to remove the dielectric structure 122 at the bottom of the contact window openings 132a, 134a. Thus, the embodiment of Figure 1 is more expensive to manufacture than the embodiment of Figures 3 and 4.

Referring to FIG. 3, in the memory structure 100a, the dielectric structure 122a includes a two-layer structure formed by an atomic layer deposited yttrium oxide layer 123 and a dielectric layer 124. The atomic layer deposited yttrium oxide layer 123 and the dielectric layer 124 are sequentially disposed on the substrate 102. In the embodiment of FIG. 3, after the atomic layer deposition of the hafnium oxide layer 123 and the dielectric layer 124 is formed, the contact opening 110a is formed in the atomic layer deposition of the hafnium oxide layer 123 and the dielectric layer 124. Since the contact opening 110a is stopped in the dielectric layer 124, it is less convenient to control the stop position of the bottom of the contact opening 110a in the process. Therefore, the reliability of the embodiment of Fig. 1 is better when the embodiment of Fig. 1 is compared with the embodiment of Fig. 3, but the manufacturing cost of the embodiment of Fig. 3 is low.

Referring to FIG. 4, in the memory structure 100b, a single dielectric layer 124 is used as the dielectric structure. In the embodiment of FIG. 4, after the dielectric layer 124 is formed, a contact opening 110a is formed in the dielectric layer 124. Since the contact opening 110a is stopped in the dielectric layer 124, it is less convenient to control the stop position of the bottom of the contact opening 110a in the process. In addition, when the embodiment of FIG. 3 is compared with the embodiment of FIG. 4, since the embodiment of FIG. 4 does not have the atomic layer deposited yttria layer 123 of FIG. 3, the reliability of the embodiment of FIG. 3 is higher. Preferably, the embodiment of Figure 4 is less expensive to manufacture.

Referring to FIG. 1 , a dielectric layer 124 is disposed on the substrate 102 between the heavily doped region 106 and the select gate structure 104 . Therefore, when the metal telluride layer 130 is formed, since the contact opening 110a has not been formed in the dielectric layer 124, the dielectric layer 124 covers the substrate 102 between the heavily doped region 106 and the selective gate structure 104. It can be used to prevent the formation of a metal telluride layer on the substrate 102 between the heavily doped region 106 and the select gate structure 104. The dielectric layer 124 is, for example, a ruthenium oxide layer formed by phosphorus-containing tetraethoxy decane (P-TEOS).

The contact etch stop layer 126 is disposed on the dielectric layer 124 and the metal sulphide layers 130a-130c. The material of the contact etch stop layer 126 is, for example, tantalum nitride. The method of forming the contact etch stop layer 126 is, for example, a chemical vapor deposition method.

The dielectric layer structure 128 is disposed on the contact etch stop layer 126. The dielectric layer structure 128 is, for example, a structure formed of a plurality of dielectric layers. The material of the dielectric layer structure 128 is, for example, ruthenium oxide. The method of forming the dielectric layer structure 128 is, for example, a chemical vapor deposition method. In this embodiment, the conductive members of the memory structure 100 (such as the contact windows 132, 134, the floating contact windows 110 and the interconnect structures 138, 140, 142, etc.) are exemplified in the dielectric layer structure 128. To explain.

Metal telluride layers 130a-130c are disposed on heavily doped region 106, heavily doped region 108, and select gate 112, respectively. The material of the metal telluride layers 130a to 130c is, for example, titanium telluride, cobalt telluride, nickel telluride, palladium telluride, platinum telluride or molybdenum telluride. The metal telluride layers 130a to 130c are formed, for example, by a self-aligned silicide (salicide) process.

Contact windows 132, 134 are electrically coupled to heavily doped regions 106, 108, respectively. Contact windows 132, 134 can be electrically connected to heavily doped regions 106, 108, respectively, by metal telluride layers 130a, 130b. Contact window 132 can be used as a source line, and contact window 134 can be used as a bit line. The material of the contact windows 132, 134 is, for example, a conductor material such as a metal such as tungsten or a doped polysilicon. In this embodiment, the material of the contact windows 132, 134 is exemplified by tungsten. The method of forming the contact windows 132, 134 is, for example, a damascene method. In addition, the contact windows 132, 134 and the floating contact window 110 can be simultaneously formed by the same process.

On the other hand, since a coupling effect occurs between the floating contact window 110 and the contact window 132, the coupling ratio and the capacitance ratio between the floating contact window 110 and the contact window 132 can be effectively improved. Further, the operation of the memory element can be performed at a low voltage. Thereby, the memory structure 100 can be programmed by means of source side injection (SSI).

The barrier layers 136a-136c may be respectively disposed on the two sides and the bottom of the contact window 132, the floating contact window 110, and the contact window 134. The material of the barrier layers 136a to 136c is, for example, TiN or TaN. The formation method of the barrier layers 136a to 136c is, for example, a physical vapor deposition method or a chemical vapor deposition method.

The interconnect structure 138 is electrically connected to the contact window 132 and can be used as a source line. The interconnect structure 138 includes a conductor layer 144 and a barrier layer 146. The barrier layer 146 may be disposed on both sides and the bottom of the conductor layer 144. The material of the conductor layer 144 is, for example, a metal such as copper or aluminum. The method of forming the conductor layer 144 is, for example, a damascene method. The material of the barrier layer 146 is, for example, TiN or TaN. The formation method of the barrier layer 146 is, for example, a physical vapor deposition method or a chemical vapor deposition method. In addition, the number of layers of the conductor layer 144 of the interconnect structure 138 of FIG. 1 is merely illustrative, and those skilled in the art can adjust the conductor layer 144 in the interconnect structure 138 in accordance with product design requirements. The number of layers.

The interconnect structure 140 is electrically connected to the floating contact window 110 and can be used to store charges. The interconnect structure 140 includes a conductor layer 148 and a barrier layer 150. The barrier layer 150 may be disposed on both sides and the bottom of the conductor layer 148. The material of the conductor layer 148 is, for example, a metal such as copper or aluminum. The method of forming the conductor layer 148 is, for example, a damascene method. The material of the barrier layer 150 is, for example, TiN or TaN. The formation method of the barrier layer 150 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In addition, since a coupling effect occurs between the interconnect structures 138 and 140, the coupling ratio and the capacitance ratio can be further increased, and the operating voltage of the memory device can be further reduced. Additionally, a portion of the interconnect structure 138 can be positioned over the interconnect structure 140 to further increase the coupling ratio to capacitance ratio.

On the other hand, the interconnect structure 138 on the side of the interconnect structure 140 may be located on one side of the interconnect structure 140, on either side of the interconnect structure 140, or around the interconnect structure 140. In the above three cases, the coupling area, the coupling ratio and the capacitance ratio between the interconnect structures 138 and 140 are increased from small to large, and the memory cell size is increased from small to large. Therefore, those skilled in the art can select the arrangement of the interconnect structure 138 based on the consideration of the coupling area, the coupling ratio, the capacitance ratio, and the memory cell size. In this embodiment, the interconnect structure 138 is illustrated on the two sides of the interconnect structure 140 as an example.

The interconnect structure 142 is electrically connected to the contact window 134 and can be used as a bit line. The interconnect structure 142 includes a conductor layer 152 and a barrier layer 154. The barrier layer 154 may be disposed on both sides and the bottom of the conductor layer 152. The material of the conductor layer 152 is, for example, a metal such as copper or aluminum. The method of forming the conductor layer 152 is, for example, a damascene method. The material of the barrier layer 154 is, for example, TiN or TaN. The formation method of the barrier layer 154 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In addition, the number of layers of the conductor layers 144, 148, and 152 of the interconnect structure 138, 140, 142 in FIG. 1 is merely an example, and those skilled in the art can adjust the interconnection according to product design requirements. The number of layers of conductor layers 144, 148, 152 in line structures 138, 140, 142. For example, the number of layers of conductor layers 144, 148 in interconnect structures 138, 140 can be increased simultaneously to increase the coupling area between interconnect structures 138, 140 to further increase the coupling ratio to capacitance ratio.

In summary, since the memory structure of the above embodiment uses a floating contact window for storing the charge, the memory structure has a simple structure and can be formed by a simple process, thereby effectively reducing the manufacturing cost. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 100a, 100b‧‧‧ memory structure

102‧‧‧Base

104‧‧‧Select gate structure

106, 108‧‧‧ heavily doped area

110‧‧‧Floating contact window

110a, 132a, 134a‧‧‧ contact window openings

112‧‧‧Select gate

114‧‧‧Dielectric layer

116‧‧‧ spacer

118, 120‧‧‧Lightly doped area

122, 122a‧‧‧ dielectric structure

123‧‧‧Atomic layer deposition of yttrium oxide layer

124‧‧‧ dielectric layer

126‧‧‧Contact window etch stop layer

128‧‧‧Dielectric layer structure

130a~130c‧‧‧metal telluride layer

132, 134‧‧‧Contact window

136a~136c, 146, 150, 154‧ ‧ barrier layer

138, 140, 142‧‧‧ interconnection structure

144, 148, 152‧‧‧ conductor layers

AA‧‧‧Active Area

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a structure of a memory according to a first embodiment of the present invention. 2 is a schematic view of the floating contact window and the active area of FIG. 1. Figure 3 is a cross-sectional view showing the structure of a memory according to a second embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a memory according to a third embodiment of the present invention.

100‧‧‧ memory structure

102‧‧‧Base

104‧‧‧Select gate structure

106, 108‧‧‧ heavily doped area

110‧‧‧Floating contact window

110a, 132a, 134a‧‧‧ contact window openings

112‧‧‧Select gate

114‧‧‧Dielectric layer

116‧‧‧ spacer

118, 120‧‧‧Lightly doped area

122‧‧‧Dielectric structure

124‧‧‧ dielectric layer

126‧‧‧Contact window etch stop layer

128‧‧‧Dielectric layer structure

130a~130c‧‧‧metal telluride layer

132, 134‧‧‧Contact window

136a~136c, 146, 150, 154‧ ‧ barrier layer

138, 140, 142‧‧‧ interconnection structure

144, 148, 152‧‧‧ conductor layers

Claims (14)

A memory structure includes: a substrate; a selective gate structure disposed on the substrate; a first heavily doped region and a second heavily doped region disposed on one side of the selective gate structure and another a floating contact window disposed on the substrate between the first heavily doped region and the selected gate structure and isolated from the substrate; and a dielectric structure disposed on the substrate The floating contact window is interposed between the substrate and the substrate to isolate the floating contact window from the substrate. The memory structure of claim 1, wherein the select gate structure comprises: a select gate disposed on the substrate; and a dielectric layer disposed between the select gate and the substrate . The memory structure of claim 1, wherein a top surface of the floating contact window is higher than a top surface of the selective gate structure. The memory structure of claim 1, wherein the floating contact window traverses the active area. The memory structure of claim 1, wherein the floating contact window and the substrate do not have a metal telluride layer. The memory structure according to claim 1, wherein the dielectric structure is a single layer structure or a multilayer structure. The memory structure of claim 1, further comprising a first lightly doped region disposed in the substrate between the first heavily doped region and the selected gate structure. The memory structure of claim 1, further comprising a second lightly doped region disposed in the substrate between the second heavily doped region and the selected gate structure. The memory structure of claim 1, further comprising a first contact window electrically connected to the first heavily doped region. The memory structure of claim 9, further comprising: a first interconnect structure electrically connected to the first contact window; and a second interconnect structure electrically connected to the float Set the contact window. The memory structure of claim 10, wherein the first interconnecting structure located on a side of the second interconnecting structure is located on one side of the second interconnecting structure and located in the second The two sides of the wiring structure or surround the second interconnect structure. The memory structure of claim 10, wherein a portion of the first interconnect structure is above the second interconnect structure. The memory structure of claim 1, further comprising a second contact window electrically connected to the second heavily doped region. The memory structure according to claim 1, which is used as a one-time programmable memory, a plurality of programmable memory or a flash memory.