CN106935586A - Memory structure - Google Patents
Memory structure Download PDFInfo
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- CN106935586A CN106935586A CN201610086854.5A CN201610086854A CN106935586A CN 106935586 A CN106935586 A CN 106935586A CN 201610086854 A CN201610086854 A CN 201610086854A CN 106935586 A CN106935586 A CN 106935586A
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- heavily doped
- contact window
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- 230000015654 memory Effects 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000007667 floating Methods 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims description 101
- 238000010276 construction Methods 0.000 claims description 59
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- 239000002356 single layer Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 24
- 239000000463 material Substances 0.000 description 23
- 239000004020 conductor Substances 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 19
- 230000004888 barrier function Effects 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000008878 coupling Effects 0.000 description 10
- 238000010168 coupling process Methods 0.000 description 10
- 238000005859 coupling reaction Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- XSKXPHGJRMYISG-UHFFFAOYSA-N [Si](OCC)(OCC)(OCC)OCC.[P] Chemical compound [Si](OCC)(OCC)(OCC)OCC.[P] XSKXPHGJRMYISG-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a memory structure, which comprises a substrate, a selection grid structure, a first heavily doped region, a second heavily doped region and a floating contact window. The selection gate structure is disposed on the substrate. The first heavily doped region and the second heavily doped region are respectively arranged in the substrate at one side and the other side of the selection gate structure. The floating contact window is arranged on the substrate between the first heavily doped region and the selection gate structure and is isolated from the substrate.
Description
Technical field
The present invention relates to a kind of semiconductor assembly structure, and more particularly to a kind of memory construction.
Background technology
Memory is the semiconductor subassembly to storage information or data, is widely used in individual calculus
The aspects such as machine, mobile phone, network, it has also become indispensable important electronic products in life.Due to
The function of computer microprocessor is more and more stronger, and the program that software is carried out is consequently increased with computing, and
Various memory data outputs also increase increasingly, thus memory capacity requirement also with regard to more and more higher.
Under the trend of the continuous microminiaturization of current memory assembly, industry is energetically carried in a limited space
The integration of memory assembly is risen, also so that the structure of memory assembly is increasingly multiple with manufacture craft
It is miscellaneous.Therefore, in the manufacturing process of memory assembly, often need to use many photomasks to complete storage
The making of device assembly, in turn results in manufacturing cost and is significantly increased.
The content of the invention
It is an object of the invention to provide a kind of memory construction, the complexity of its simple structure and manufacture craft
Degree is low, and then can be effectively reduced manufacturing cost.
The present invention proposes a kind of memory construction, including substrate, selection grid structure, the first heavily doped region,
Second heavily doped region and floating contact window.Selection grid structure setting is in substrate.First heavily doped region with
Second heavily doped region is respectively arranged in the substrate of selection grid structure side and opposite side.Floating contact window
It is arranged in the substrate between the first heavily doped region and selection grid structure and mutually isolated with substrate.
According to described in one embodiment of the invention, in above-mentioned memory construction, grid structure bag is selected
Include selection grid and dielectric layer.Selection grid is arranged in substrate.Dielectric layer is arranged at selection grid and base
Between bottom.
According to described in one embodiment of the invention, in above-mentioned memory construction, the top of floating contact window
Face is, for example, higher than the top surface of selection grid structure.
According to described in one embodiment of the invention, in above-mentioned memory construction, floating contact window is for example
It is to cross active region.
According to described in one embodiment of the invention, in above-mentioned memory construction, floating contact window and base
It is, for example, do not have metal silicide layer between bottom.
According to described in one embodiment of the invention, in above-mentioned memory construction, also including dielectric structure.
Dielectric structure is arranged between floating contact window and substrate, may be used to isolate floating contact window and substrate.
According to described in one embodiment of the invention, in above-mentioned memory construction, dielectric structure can be single
Rotating fields or sandwich construction.
According to described in one embodiment of the invention, in above-mentioned memory construction, also gently mixed including first
Miscellaneous area.First lightly doped district is arranged in the substrate between the first heavily doped region and selection grid structure.
According to described in one embodiment of the invention, in above-mentioned memory construction, also gently mixed including second
Miscellaneous area.Second lightly doped district is arranged in the substrate between the second heavily doped region and selection grid structure.
According to described in one embodiment of the invention, in above-mentioned memory construction, also including the first contact
Window.First contact hole is electrically connected to the first heavily doped region.
It is also inline including first in above-mentioned memory construction according to described in one embodiment of the invention
Machine structure and the second interconnection structure.First interconnection structure is electrically connected to the first contact hole.Second is inline
Machine structure is electrically connected to floating contact window.
It is online in second in above-mentioned memory construction according to described in one embodiment of the invention
First interconnection structure of structure side can be located at the side of the second interconnection structure, online in second
The both sides of structure surround the second interconnection structure.
It is online in part first in above-mentioned memory construction according to described in one embodiment of the invention
Structure can be located at the top of the second interconnection structure.
According to described in one embodiment of the invention, in above-mentioned memory construction, also including the second contact
Window.Second contact hole is electrically connected to the second heavily doped region.
According to described in one embodiment of the invention, in above-mentioned memory construction, memory construction can use
In memory (OTP memory), the memory (MTP of multiple programmable as disposable programmable
) or flash memories (flash memory) memory.
Based on above-mentioned, because memory construction proposed by the invention is to carry out electricity using floating contact window
The storage of lotus, so memory construction has simple structure, and can be formed by easy manufacture craft,
And then manufacturing cost can be effectively reduced.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate
Appended accompanying drawing is described in detail below.
Brief description of the drawings
Fig. 1 is the sectional view of the memory construction of first embodiment of the invention；
Fig. 2 is the schematic diagram of the floating contact window in Fig. 1 and active region；
Fig. 3 is the sectional view of the memory construction of second embodiment of the invention；
Fig. 4 is the sectional view of the memory construction of third embodiment of the invention；
Symbol description
100、100a、100b：Memory construction
102：Substrate
104：Selection grid structure
106、108：Heavily doped region
110：Floating contact window
110a、132a、134a：Contact window
112：Selection grid
114：Dielectric layer
116：Clearance wall
118、120：Lightly doped district
122、122a：Dielectric structure
123：Ald silicon oxide layer
124：Dielectric layer
126：Contact hole etching stop layer
128：Dielectric layer structure
130a~130c：Metal silicide layer
132、134：Contact hole
136a~136c, 146,150,154：Barrier layer
138、140、142：Interconnection structure
144、148、152：Conductor layer
AA：Active region
Specific embodiment
Fig. 1 is the sectional view of the memory construction of first embodiment of the invention.Fig. 2 is floating in Fig. 1
The schematic diagram of contact hole and active region.Fig. 3 is the sectional view of the memory construction of second embodiment of the invention.
Fig. 4 is the sectional view of the memory construction of third embodiment of the invention.
Fig. 1 is refer to, memory construction 100 includes substrate 102, selection grid structure 104, heavy doping
Area 106, heavily doped region 108 and floating contact window 110.Memory construction 100 is used as once
The memory or flash memories of programmable memory, multiple programmable.Substrate 102 is e.g. partly led
Body substrate, such as silicon base.
Selection grid structure 104 is arranged in substrate 102.Selection grid structure 104 includes selection grid
112 and dielectric layer 114, and may also include clearance wall 116.Selection grid 112 is arranged in substrate 102.
The material for selecting grid 112 is, for example, the conductor material such as DOPOS doped polycrystalline silicon.Select the formation side of grid 112
Rule chemical vapour deposition technique in this way.Dielectric layer 114 is arranged between selection grid 112 and substrate 102,
Can be used as gate dielectric layer.The material of dielectric layer 114 is, for example, silica.The formation of dielectric layer 114
Method is, for example, thermal oxidation method.Clearance wall 116 is arranged on the side wall of selection grid 112.Clearance wall 116
Material be, for example, silicon nitride.The forming method of clearance wall 116 is, for example, to be initially formed covering selection grid 112
Spacer material layer (not illustrating), then spacer material layer is carried out by etch-back manufacture craft and formed.
Heavily doped region 106,108 is respectively arranged at the substrate of the selection side of grid structure 104 and opposite side
In 102.Heavily doped region 106,108 can be respectively N-type heavily doped region or p-type heavily doped region.Herein
In embodiment, heavily doped region 106,108 is illustrated by taking N-type heavily doped region as an example.Heavy doping
The forming method in area 106,108 is, for example, ion implantation.
Floating contact window 110 is arranged at the substrate between heavily doped region 106 and selection grid structure 104
It is on 102 and mutually isolated with substrate 102.Floating contact window 110 can be used to store electric charge.Due to depositing
Reservoir structures 100 are that the storage of electric charge is carried out using floating contact window 110, so memory construction 100
With simple structure, and can be formed by easy manufacture craft, and then can be effectively reduced and be manufactured into
This.The top surface of floating contact window 110 is, for example, higher than the top surface of selection grid structure 104.Floating contact
It is, for example, do not have metal silicide layer between window 110 and substrate 102, therefore electric charge will not be produced golden
The situation that category silicide layer is captured, and can effectively enter the operation of line storage.Additionally, refer to
Fig. 2, floating contact window 110 is, for example, to cross active region AA, thus can prevent leakage current from producing.It is floating
Put the material e.g. conductor material of contact hole 110, such as tungsten metal or DOPOS doped polycrystalline silicon.Implement herein
In example, the material of floating contact window 110 is illustrated by taking tungsten as an example.The shape of floating contact window 110
It is, for example, damascene into method.
In addition, refer to Fig. 1, memory construction 100 be also optionally included with lightly doped district 118,
Lightly doped district 120, dielectric structure 122, dielectric layer 124, contact hole etching stop layer (CESL) 126,
Dielectric layer structure 128, metal silicide layer 130a~130c, contact hole 132, contact hole 134, barrier
Online 138,140, at least one of 142 in layer 136a~136c, metal.
Lightly doped district 118 is arranged at the substrate 102 between heavily doped region 106 and selection grid structure 104
In.Lightly doped district 120 is arranged at the substrate 102 between heavily doped region 108 and selection grid structure 104
In.The doping concentration and depth of lightly doped district 118,120 are, for example, less than heavily doped region 106,108
Doping concentration and depth.Lightly doped district 118,120 can be N-type lightly doped district or p-type lightly doped district.
In this embodiment, lightly doped district 118,120 is illustrated by taking N-type lightly doped district as an example.Gently
The forming method of doped region 118,120 is, for example, ion implantation.
Dielectric structure 122 is arranged between floating contact window 110 and substrate 102, may be used to isolation floating
Contact hole 110 and substrate 102.Dielectric structure 122 can be single layer structure or sandwich construction.Implement herein
In example, dielectric structure 122 is illustrated by taking the ald of individual layer (ALD) silicon oxide layer as an example,
But the present invention is not limited thereto.In other embodiments, dielectric structure 122 also can be sandwich construction.
Art skilled person can adjust dielectric knot based on the consideration of reliability and manufacturing cost
The number of plies and kenel of structure 122.
Hereinafter, it is compared come the different aspects to dielectric structure from the embodiment of Fig. 4 with Fig. 1, Fig. 3
Illustrate, but the present invention is not limited thereto.Additionally, in the memory construction 100a and Fig. 4 of Fig. 3
In memory construction 100b, material, the configuration side of the component similar to the memory construction 100 of Fig. 1
Formula and effect etc. refer to the explanation of the embodiment of Fig. 1, be repeated no more in this.
Fig. 1 is refer to, the forming method of dielectric structure 122 is comprised the following steps.Formed through dielectric layer
The contact window 110a of structure 128, contact hole etching stop layer 126 and dielectric layer 124, wherein connecing
It is for forming floating contact window 110 to touch window opening 110a.Then, in contact window 110a
Form dielectric structure 122.In the embodiment in figure 1, because dielectric structure 122 is in contact window
110a is just formed after being formed, therefore reliability is preferable.Additionally, dielectric structure 122 can also be formed respectively
In contact window 132a, 134a.Therefore, compared to the embodiment of Fig. 3 and Fig. 4, Fig. 1's
Embodiment is in order that the contact hole 132,134 being subsequently formed in contact window 132a, 134a can
Heavily doped region 106,108 is respectively electrically connected to, therefore one photomask manufacture craft can be carried out to remove morely
Positioned at the dielectric structure 122 of contact window 132a, 134a bottoms.Therefore, compared to Fig. 3 and Fig. 4
Embodiment, the manufacturing cost of the embodiment of Fig. 1 is higher.
Fig. 3 is refer to, in memory construction 100a, dielectric structure 122a includes ald oxygen
The double-decker that SiClx layer 123 is formed with dielectric layer 124.Ald silicon oxide layer 123 and Jie
Electric layer 124 is sequentially arranged in substrate 102.In the fig. 3 embodiment, forming ald oxygen
After SiClx layer 123 and dielectric layer 124, then at ald silicon oxide layer 123 and dielectric layer 124
Middle formation contact window 110a.Because contact window 110a is off in dielectric layer 124, institute
With the stop position of the contact window 110a bottoms less easy to control in manufacture craft.Therefore, inciting somebody to action
When the embodiment of Fig. 1 is compared with the embodiment of Fig. 3, the reliability of the embodiment of Fig. 1 is preferable, but
The manufacturing cost of the embodiment of Fig. 3 is relatively low.
Fig. 4 is refer to, in memory construction 100b, using individual layer dielectric layer 124 as dielectric structure.
In the fig. 4 embodiment, after dielectric layer 124 is formed, contact hole is formed in dielectric layer 124
Opening 110a.Because contact window 110a is off in dielectric layer 124, so in manufacture craft
On contact window 110a bottoms less easy to control stop position.Additionally, by the embodiment of Fig. 3
When embodiment with Fig. 4 is compared, due to Fig. 4 embodiment and without the atomic layer deposition in Fig. 3
Product silicon oxide layer 123, therefore the embodiment of Fig. 3 reliability preferably, but the embodiment of Fig. 4 manufacture
Cost is relatively low.
Fig. 1 is continued referring to, dielectric layer 124 is arranged at heavily doped region 106 with selection grid structure 104
Between substrate 102 on.Therefore, when metal silicide layer 130 is formed, due to not yet in dielectric layer
In 124 formed contact window 110a, so dielectric layer 124 can cover positioned at heavily doped region 106 with
Substrate 102 between selection grid structure 104, and may be used to prevent in heavily doped region 106 and selection grid
Metal silicide layer is formed in substrate 102 between pole structure 104.Dielectric layer 124 is, for example, by containing
The silicon oxide layer that phosphorus tetraethoxysilane (P-TEOS) is formed.
Contact hole etching stop layer 126 is arranged on dielectric layer 124 and metal silicide layer 130a~130c.
The material of contact hole etching stop layer 126 is, for example, silicon nitride.The formation of contact hole etching stop layer 126
Method is, for example, chemical vapour deposition technique.
Dielectric layer structure 128 is arranged on contact hole etching stop layer 126.Dielectric layer structure 128 is for example
It is the structure formed by multilayer dielectric layer.The material of dielectric layer structure 128 is, for example, silica.Dielectric
The forming method of Rotating fields 128 is, for example, chemical vapour deposition technique.In this embodiment, memory construction
100 conductive member (such as contact hole 132,134, floating contact window 110 and interconnection structure 138,140,
142 etc.) it is to be illustrated as a example by be arranged in dielectric layer structure 128.
Metal silicide layer 130a~130c is respectively arranged at heavily doped region 106, heavily doped region 108 with choosing
Select on grid 112.The material of metal silicide layer 130a~130c is, for example, titanium silicide, cobalt silicide, silicon
Change nickel, palladium silicide, platinum silicide or molybdenum silicide.Metal silicide layer 130a~130c is, for example, to carry out voluntarily
Metal silicide (self-aligned silicide, salicide) manufacture craft is formed.
Contact hole 132,134 is respectively electrically connected to heavily doped region 106,108.Contact hole 132,134
Heavily doped region 106,108 can be electrically connected to by metal silicide layer 130a, 130b respectively.Contact hole
132 can be used as source electrode line, and contact hole 134 can be used as bit line.Contact hole 132,134
Material be, for example, conductor material, such as tungsten metal or DOPOS doped polycrystalline silicon.In this embodiment, contact hole
132nd, 134 material is illustrated by taking tungsten as an example.The forming method of contact hole 132,134 is for example
It is damascene.Additionally, contact hole 132,134 can be by identical making with floating contact window 110
Technique is formed simultaneously.
On the other hand, due to coupling effect can be produced between floating contact window 110 and contact hole 132, because
This can effectively lift the coupling efficiency (coupling ratio) between floating contact window 110 and contact hole 132
With capacity ratio (capacitance ratio), and then the operation of memory assembly can be carried out with low-voltage.By
This, the mode that memory construction 100 can inject (source side injection, SSI) by source side is come
Carry out programming operations.
Barrier layer 136a~136c may be disposed at contact hole 132, floating contact window 110 and contact hole respectively
134 both sides and bottom.The material of barrier layer 136a~136c is, for example, TiN or TaN.Barrier layer
The forming method of 136a~136c is, for example, physical vaporous deposition or chemical vapour deposition technique.
Interconnection structure 138 is electrically connected to contact hole 132, may be used as source electrode line and uses.It is interior online
Structure 138 includes conductor layer 144 and barrier layer 146.Barrier layer 146 may be disposed at conductor layer 144
Both sides and bottom.The material of conductor layer 144 is, for example, the metals such as copper or aluminium.The formation side of conductor layer 144
Rule damascene in this way.The material of barrier layer 146 is, for example, TiN or TaN.Barrier layer 146
Forming method is, for example, physical vaporous deposition or chemical vapour deposition technique.Additionally, interior online in Fig. 1
The number of plies of the conductor layer 144 that structure 138 has by way of example only, this skill is familiar with this technical field
Patient can adjust the number of plies of the conductor layer 144 in interconnection structure 138 according to product design demand.
Interconnection structure 140 is electrically connected to floating contact window 110, can be used to store electric charge.Interior online knot
Structure 140 includes conductor layer 148 and barrier layer 150.Barrier layer 150 may be disposed at the two of conductor layer 148
Side and bottom.The material of conductor layer 148 is, for example, the metals such as copper or aluminium.The forming method of conductor layer 148
E.g. damascene.The material of barrier layer 150 is, for example, TiN or TaN.The shape of barrier layer 150
It is, for example, physical vaporous deposition or chemical vapour deposition technique into method.
Further, since coupling effect can be produced between interconnection structure 138,140, therefore can be further
Ground lifting coupling efficiency and capacity ratio, and can further reduce the operating voltage of memory assembly.Additionally,
Part interconnection structure 138 can be located at the top of interconnection structure 140, with further improve coupling efficiency with
Capacity ratio.
On the other hand, the interconnection structure 138 positioned at the side of interconnection structure 140 can be located at interior online knot
The side of structure 140, positioned at the both sides of interconnection structure 140 or around interconnection structure 140.Above-mentioned three
Coupling area, coupling efficiency and capacity ratio between the interconnection structure 138,140 of the situation of kind is ascending
It is incremented by, and memory cell size is ascending incremental.Therefore, art skilled person can
Consideration based on coupling area, coupling efficiency, capacity ratio and memory cell size selects interior online knot
The set-up mode of structure 138.In this embodiment, interconnection structure 138 is with positioned at interconnection structure 140
Both sides as a example by illustrate.
Interconnection structure 142 is electrically connected to contact hole 134, may be used as bit line and uses.Interior online knot
Structure 142 includes conductor layer 152 and barrier layer 154.Barrier layer 154 may be disposed at the two of conductor layer 152
Side and bottom.The material of conductor layer 152 is, for example, the metals such as copper or aluminium.The forming method of conductor layer 152
E.g. damascene.The material of barrier layer 154 is, for example, TiN or TaN.The shape of barrier layer 154
It is, for example, physical vaporous deposition or chemical vapour deposition technique into method.
Additionally, the interconnection structure 138,140,142 in Fig. 1 have conductor layer 144,148,
152 number of plies by way of example only, can be according to product design demand in this technical field skilled person
To adjust the number of plies of the conductor layer 144,148,152 in interconnection structure 138,140,142.Citing
For, can simultaneously increase the number of plies of the conductor layer 144,148 in interconnection structure 138,140 to improve
Coupling area between interconnection structure 138,140, further to improve coupling efficiency and capacity ratio.
In sum, because the memory construction of above-described embodiment is to carry out electric charge using floating contact window
Storage, so memory construction has simple structure, and can be formed by easy manufacture craft,
And then manufacturing cost can be effectively reduced.
Although disclosing the present invention with reference to above example, but it is not limited to the present invention, any
Skilled person in art, without departing from the spirit and scope of the present invention, can make a little
Change and retouching, therefore protection scope of the present invention should be by being defined that the claim enclosed is defined.
Claims (15)
1. a kind of memory construction, including：
Substrate；
Selection grid structure, is arranged in the substrate；
First heavily doped region and the second heavily doped region, be respectively arranged at the selection grid structure side with it is another
In the substrate of side；And
Floating contact window, is arranged at the substrate between first heavily doped region and the selection grid structure
On, and it is mutually isolated with the substrate.
2. memory construction as claimed in claim 1, wherein selection grid structure includes：
Selection grid, is arranged in the substrate；And
Dielectric layer, is arranged between the selection grid and the substrate.
3. memory construction as claimed in claim 1, the wherein top surface of the floating contact window were higher than should
Select the top surface of grid structure.
4. memory construction as claimed in claim 1, wherein floating contact window crosses active region.
5. memory construction as claimed in claim 1, wherein between the floating contact window and the substrate
Without metal silicide layer.
6. memory construction as claimed in claim 1, also including dielectric structure, is arranged at this floating
Between contact hole and the substrate, to isolate the floating contact window and the substrate.
7. memory construction as claimed in claim 6, the wherein dielectric structure are single layer structure or many
Rotating fields.
8. memory construction as claimed in claim 1, also including the first lightly doped district, is arranged at this
In the substrate between first heavily doped region and the selection grid structure.
9. memory construction as claimed in claim 1, also including the second lightly doped district, is arranged at this
In the substrate between second heavily doped region and the selection grid structure.
10. memory construction as claimed in claim 1, also including the first contact hole, is electrically connected to this
First heavily doped region.
11. memory constructions as claimed in claim 10, also include：
First interconnection structure, is electrically connected to first contact hole；And
Second interconnection structure, is electrically connected to the floating contact window.
12. memory constructions as claimed in claim 11, wherein positioned at the second interconnection structure side
First interconnection structure on side is located at the side of second interconnection structure, positioned at the online knot in second
The both sides of structure surround second interconnection structure.
13. memory constructions as claimed in claim 11, which part first interconnection structure position
In the top of second interconnection structure.
14. memory constructions as claimed in claim 1, also including the second contact hole, are electrically connected to this
Second heavily doped region.
15. memory constructions as claimed in claim 1, its be used for memory as disposable programmable,
The memory or flash memories of multiple programmable.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN1917178A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Nonvolatile memory unit, manufacturing method, and opertion method |
| CN1953161A (en) * | 2005-10-18 | 2007-04-25 | 恩益禧电子股份有限公司 | Semiconductor memory device and method for producing same |
| US20120025290A1 (en) * | 2010-07-28 | 2012-02-02 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
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| TWI258201B (en) * | 2005-02-16 | 2006-07-11 | Powerchip Semiconductor Corp | Method for manufacturing semiconductor device and plug |
| JP5191633B2 (en) * | 2006-04-04 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8383476B2 (en) * | 2010-09-23 | 2013-02-26 | Globalfoundries Singapore Pte. Ltd. | EEPROM cell |
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| CN1917178A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Nonvolatile memory unit, manufacturing method, and opertion method |
| CN1953161A (en) * | 2005-10-18 | 2007-04-25 | 恩益禧电子股份有限公司 | Semiconductor memory device and method for producing same |
| US20120025290A1 (en) * | 2010-07-28 | 2012-02-02 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
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| TW201724473A (en) | 2017-07-01 |
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