CN102741154B - 半导体器件和相应的制造方法 - Google Patents
半导体器件和相应的制造方法 Download PDFInfo
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- CN102741154B CN102741154B CN201080063369.7A CN201080063369A CN102741154B CN 102741154 B CN102741154 B CN 102741154B CN 201080063369 A CN201080063369 A CN 201080063369A CN 102741154 B CN102741154 B CN 102741154B
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Abstract
本发明提供一种半导体器件和一种相应的制造方法。半导体器件包括衬底(1;1');模制封装;和半导体芯片(5;5'),该半导体芯片在模制封装(8)中在衬底(1;1')上方被如此地悬置在模制材料处,使得空腔(10)将半导体芯片(5;5')与衬底(1;1')机械地分离,其中,空腔(10)沿着与衬底(1;1')面对的底面(U;U')延伸。
Description
现有技术
本发明涉及一种半导体器件和一种相应的制造方法。
尽管本发明可以应用于任何半导体器件,但是本发明以及其基于的问题将针对一种微机械的压力传感器进行说明。
DE102006026881A1公开了一种在开式模腔实型铸造技术(Open-Cavity-Full-Mold)中用于绝对压力传感器的装配设计构思。在这种装配设计构思中,芯片被固定在引线框上,被引线键合并且如此地用一种模制材料环绕注塑,使得传感器芯片部分地从模制材料中突出来。传感器膜片位于没有被环绕注塑的部分中。
微机械的传感器装置通常被封装在塑料制成的模制壳体中。在此情况下,一方面使用所谓的引线壳,其具有用于接通下一个层面的弯曲的接触支脚并且完全地包围一个或一些芯片。另一方面,具有所谓的覆盖式模塑的无引线壳体,其特点在于无接触支脚。在此情况下,与下一个层面的接通是经封装的底面上的接触面实现的。这种模制的封装变型的基础系统在此情况下一般地由衬底(Cu,FR4),粘合剂,这些或这个硅芯片和模制材料组成。
另一种封装变型是成本高的预模制壳体。在此涉及的是预制的压铸的基础壳体,其在安置和接通半导体芯片之后用盖子封闭。预模制壳体在此情况下是低应力的封装形状,因为在复合对象硅和模制材料组件之间不存在直接的接触。此外,在封装之内存在的、与封装中的一个开口连通的穴对于介质通道来说是令人感兴趣的并且是符合目的的,如它们例如对于压力传感器,IR-传感器和微音器是所需要的。在成本问题方面,具有一些目标,即在实型模制封装(完全环绕模制)中也实现介质通道和空腔。在一个第一设计构思中应用所谓的薄膜模制法(Filmmoldverfahren)。在此情况下,介质通道通过模具的形状实现。一个突出的模具结构直接地放置在半导体芯片上并且防止在这个区域中的覆盖式模塑,例如在压力传感器膜片的区域中。为了公差补偿,该模具用ETFE薄膜(ETFE=四氟乙烯(Ethylen-Tetrafluorethylen))覆盖。该薄膜可以强烈变形并且不走样地覆盖在模具表面上。在该方法中,在传感器布置和模具结构之间具有直接的关联关系。模具必须遮盖活性的膜片结构,但是不遮盖焊盘面(Padflächen)或焊线(接合线)(Drahtbonds)。因此必须遵守一定的设计规则。此外,依据设计布置的情况,也可能必需将模具整个地放置在活性的结构如例如膜片上并且导致机械负荷。在这种方法中不可能在腔穴中实现咬边(底切)。
另一个设计构思是基于在结合通过倒装芯片和底部填充技术的接通下使用层压薄片为基的衬底。在此情况下经焊料球或凸点和底部填充剂形成传感器与衬底的机械的和电气的接触。压力传感器膜片保持不被遮盖并且经衬底中的通孔获得介质通道。但是尤其是底部填充剂的点是关键性的。为了不使膜片被底部填充剂遮盖,利用了在衬底通孔的边缘处的中断的毛细管效应。因此通孔的大小和边缘形状间接地与底部填充剂的流动路径(和反向地)和由此与传感器膜片的功能相关联。此外,底部填充剂在形成的半月面中朝着膜片方向上延伸并且由此使用了未用过的传感器面。
图9a,b是形式为微机械的压力传感器装置的、举例说明的半导体器件的横截面视图,其中,图9b示出了图9a的区域A的局部放大图。
在图9a,b中,附图标记SUB表示印刷电路板衬底,借助于焊料球LK在该衬底上安置评估芯片(处理芯片)3和微机械的压力传感器芯片5。在微机械的压力传感器芯片5下面设置底部填充剂U,其用于机械稳定作用。两个芯片3,5被封装在由模制材料或模压材料组制成的模制封装(模制管壳)8中。压力传感器芯片5的膜片区M保持无底部填充剂U,因为在衬底中的通孔L设置在相应的位置上。如由图9b中可以看见的,底部填充剂U在通孔L处的边缘和微机械的压力传感器芯片5之间形成半月面MIN,这导致提高的位置空间的需求。
本发明的优点
相对于已知的解决方案,按照权利要求的的本发明的半导体器件和按照权利要求8的相应的制造方法具有优点,即实现一种简单的、成本有利的并且与应力分离的结构。
本发明基于的构思在于在圆晶层面上设置粘合材料和以后在元器件层面上或在组件层面上相对于衬底,模制封装和半导体芯片选择地去除粘合材料,由此将半导体芯片这样地在模制封装中悬置在衬底的上方,使得一个在其中不设置任何液态的或固态的介质的空腔将半导体芯片与衬底机械地分离。因此在半导体芯片和衬底之间可以不再出现直接的应力。半导体芯片仅仅还与在模制封装中的复合对象模制材料稳定地连接。
从属权利要求中给出本发明的相应的主题的一些有利的扩展方案和改进方案。
本发明实现了模制封装中的复合系统的分离并且在微机械的传感器芯片的情况下同时形成一个腔穴作为可能的介质通道,微机械的传感器芯片需要这种介质通道。
在一个特别优选的实施方式中,粘合材料被离心涂敷到具有半导体芯片的圆晶的底面上,该底面以后将面对着衬底。在将圆晶分离成各单个的半导体芯片之后,可以全自动地实施衬底的装配,而不必对此配量附加的粘结剂。
按照本发明的封装不需要任何标准芯片接合技术,如粘接或倒装芯片技术。这导致材料和成本的节省。借助于优选的聚合物作为粘合材料将半导体芯片接合在衬底上的加工持续时间仅仅为0.5至3秒,该时间是用于熔化粘合材料所需要的。对应力敏感的半导体芯片仅仅还有一个复合对象,即模制材料,而不是如在现有技术中那样有三个复合对象。该剩下的复合对象,即模制材料,此外最佳地匹配于该半导体,例如硅。不需要粘合材料的结构化处理。
通过去除粘合材料形成的空腔不仅可以用作为介质通道,而且可以用作为补偿复合体变形的自由空间,从而这种变形不影响半导体芯片。空腔在半导体芯片和衬底之间的高度可以在不需要大的费用下通过施加的粘合材料层的厚度和自动装配装置的装配参数进行调整。
尤其是对于形式为压力传感器装置的半导体器件,由此得到以下其它的优点。不需要特殊的模制工具。因此不需要任何设计布置的分离(模具-压力传感器膜片)并且没有窄的公差链,例如在传感器芯片的定位上。膜片不必直接地位于介质通道的上方,这决定了使膜片相对于颗粒,光等等得到更好的保护。此外膜片不承受由于模具接触造成的机械负荷。不需要特殊的模制方法,如例如薄膜模制,并且没有由于底部填充剂造成的任何影响,如例如膜片边缘覆盖。介质通道的尺寸可以通过衬底的通孔的设计布置自由地选择。
作为可选择地去除或分解的粘合材料最好使用聚合物。作为可能的聚合物,尤其是考虑可受热分解的聚合物,如例如多环烯烃。它们的特点在于比较低的分解温度≥100℃。它们一般无残留物地分解成气态反应物,如例如C02,CO和H2。此外它们可以如标准漆一样被离心涂敷并且可结构化。
附图
本发明的实施例在附图中示出并且在以下的描述中进行详细说明。
附图所示:
图1是按照本发明的第一实施方式的、形式为微机械的压力传感器装置的半导体器件的横截面视图;
图2是按照本发明的第二实施方式的、形式为转速传感器装置的半导体器件的横截面视图;
图3是按照本发明的第三实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图;
图4是按照本发明的第四实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图;
图5是按照本发明的第五实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图;
图6是按照本发明的第六实施方式的、形式为微机械的压力传感器装置的半导体器件的横截面视图;
图7a-d是按照本发明的第七实施方式在一种用于按照图1的半导体器件的制造方法中前后相继的处理阶段的横截面视图;
图8a-d是按照本发明的第八实施方式在一种用于按照图6的半导体器件的制造方法中前后相继的处理阶段的横截面视图;和
图9a,b是形式为微机械的压力传感器装置的、举例说明的半导体器件的横截面视图,其中,图9b示出了图9a的区域A的局部放大图。
实施例的描述
在附图中相同的附图标记表示相同的或功能相同的部件。
图1是按照本发明的第一实施方式的、形式为微机械的压力传感器装置的半导体器件的横截面视图。
在图1中,附图标记1表示一个印刷电路板衬底,在其上安置有评估芯片3,它经接合线3a与衬底1连接和经接合线3b与微机械的压力传感器芯片5连接。微机械的芯片5在由塑料模压材料构成的模制封装8中在其顶面O处和在其侧边S的部分区域中在与硅直接的复合接触下被这样地悬置,使得空腔10机械地将微机械的压力传感器芯片5与衬底分离开。
换言之,微机械的压力传感器芯片5在它的底面U处和在它的侧面S的部分区域处不接触衬底1。仅仅在它的顶面O的区域中和在它的侧边S的上部区域中,微机械的压力传感器芯片被悬置在模制封装8中。附图标记1a表示通过衬底1的通孔,它用作微机械的压力传感器芯片5的介质通道。值得注意的是,微机械的压力传感器芯片5的膜片区M不是直接地位于通孔1a上方,而是从侧边与其错开地设置,从而保护它免受外部的影响,如例如颗粒,光,搬运等等。
图2是按照本发明的第二实施方式的、形式为转速传感器装置的半导体器件的横截面视图。
在图2所示的实施方式中,取代微机械的压力传感器芯片5,设置另一个微机械的传感器芯片5',例如旋转速度传感器。在它的顶面O'以及它的侧面S'的一些部分的上方在模制封装8中的悬置,同时在它的底面U'和它的侧边S'的一些下部部分处形成空腔5,这是与按照图1第一实施方式相类似的。
附图标记ST表示一些区域,在这些区域中可以产生热感应应力。该应力尤其是在评估芯片3下方出现,该评估芯片直接地或经粘接技术或倒装芯片技术与衬底1连接。相反,微机械的传感器芯片5'保持与其不接触,因为它仅仅在区域EK中被悬挂在模制封装8上,该模制封装以热机械方式很好地与硅相适配。
图3是按照本发明的第三实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图。
按照图3的第三实施方式与按照图2的第二实施方式的区别在于,评估芯片3也被悬置于模制封装8的模制材料中并且一个另外的空腔设置在评估芯片3下面,该空腔将评估芯片3机械地与衬底1分离。因此图2的大的应力承载的区域ST减小成图3中两个小的应力承载的部分区域ST,但是它们不与评估芯片3相邻接,而仅仅与塑料制成的模制封装8相邻接,因此印刷电路板和模制封装之间的复合面积减小。
在按照图3的第三实施方式中,在衬底1中在评估芯片3下方附加地设置一个另外的通孔1c。在上述第一至第三实施方式中的通孔1a或1a和1c除了其自身作为介质通道外也与有关的微机械器件的制造方法相关联,如后面结合图6和7进行说明的那样。
图4是按照本发明的第四实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图。
与按照图3的第三实施方式不同,在按照图4的第四实施方式中,在衬底1’中不设置通孔1a,1c。取而代之地,用衬底1’中的DB1,DB2扩散区表征,它们在后面结合按照本发明的用于半导体器件的制造方法的实施方式进行说明。
图5是按照本发明的第五实施方式的、形式为微机械的转速传感器装置的半导体器件的横截面视图。
在按照图5的第五实施方式中只有一个惟一的微机械的传感器芯片,例如旋转速度传感器,在模制封装8中被悬置在没有通孔的衬底1'的上方。与按照图4的第四实施方式类似地,在图5中,附图标记DB也表示扩散区,它在后面进行说明。
图6是按照本发明的第六实施方式的、形式为微机械的压力传感器装置的半导体器件的横截面视图。
与按照图1的第一实施方式不同,在按照图6的第六实施方式中,在衬底1’中不设置通孔1a,而是有一个侧边的通道1b,通过它可以从外部通入空腔10中。这个侧边的通道1b将结合按照图7a-d的制造方法进行详细说明。
图7a-d是按照本发明的第七实施方式在一种用于按照图1的半导体器件的制造方法中前后相继的处理阶段的横截面视图。
在按照图7a的开始的处理阶段中,评估芯片3被安置到衬底1上,并且例如采用粘接技术来安置。这是在衬底1上的多个器件的器件复合中进行的。
微机械的压力传感器芯片5在圆晶处理的最后的处理步骤中在进行锯割之前通过离心涂覆在它的底面U上获得一个由多环烯烃构成的聚合物层50,该底面以后被面向衬底l。粘合材料50的层厚在与粘合参数相结合下以后将决定在完成处理的微机械的器件中产生的空腔10的高度。在分离出具有微机械的压力传感器芯片5的圆晶之后,微机械的压力传感器芯片被施加在衬底1中的通孔1a上方的规定的安装区域中。
如图7b中所示,在施加期间,借助于被加热的装配装置在限定的参数如例如温度,力,保持时间等等下在衬底1上实施粘接,其中,粘合材料50被熔化。对此,典型的保持时间位于0.5-3秒的范围中。不需要使用任何附加的粘合剂,其涉及分配和通常一小时的费时的开装步骤。在随后将在衬底和评估芯片之间或在评估芯片和压力传感器芯片5之间的接合引线3a,3b进行引线接合(键合)之后,该系统被模制。这个模制处理步骤在170℃的温度下只持续大约一至两分钟,其中,粘合材料50在此时位置或形状稳定地作为接合层(粘合层)保留在压力传感器芯片5和衬底1之间。
通过利用粘合材料50的粘接,依赖于粘合材料50的层厚和粘接参数,微机械的压力传感器芯片5的侧边S处产生轻微的半月面(Menisken)。
在一个随后的步骤中,通过锯割步骤实施器件的分离。
在接下来的PMC(Post-Mold-Cure(后固化))温度步骤(Temperaturschritt)中,该步骤按照标准被实施用于模制封装8的最终交联,粘合材料50被无残留物地分解成气态产物并且因此可以被选择地去除。形成的气态产物经衬底中的通孔1a逸出。
在锯割步骤之后去除粘合材料50具有优点,即在整个装配过程期间可以通过粘合材料对底面U上的敏感的芯片元件,如例如膜片M,实施保护功能。
如果这是不需要的,那么也可以在锯割步骤之前实施粘合材料50的去除。
形成的空腔10形成用于压力传感器芯片5的介质通道并且另一方面负责使对应力敏感的压力传感器芯片5与衬底1分离。压力传感器芯片5的惟一留下的复合对象是以热的方式最佳地匹配于硅的模制封装8的模制材料。通过与衬底1的分离显著地减小热的不匹配和翘曲。此外,通过该分离造成模制封装-衬底的复合体的可能的变形不会或仅仅有限地传递到压力传感器芯片5上。此外,在压力传感器芯片5上的足够小的模制敷层情况下,硅变得占优势并且由此不承受应力。
尽管在结合图7a-d描述的实施方式中选择地去除粘合材料50与PMC温度步骤同时地实施,但自然这并不一定是必需的,而是也可以在一个分开的温度步骤中实施。
此外,在回顾图4和5下应该指出,在衬底1’也可以存在扩散区来取代衬底中的通孔1a或1a和1c,粘合材料50的气态的分解产物可以通过这些扩散区逸出。这些扩散区DB1,D2或DB或者可以是被特定地结构化的区域,或者在可以强力扩散渗透的衬底1’的情况下可以是完全正常的衬底区域,该衬底区域与其环境没有区别。
此外应该提及的是,本发明不局限于粘合材料的热分解,而是也包括化学的和/或物理的分解,如例如通过溶剂或腐蚀剂或等离子体进行分解。
图8a-d是按照本发明的第八实施方式在一种用于按照图6的半导体器件的制造方法中前后相继的处理阶段的横截面视图。
在图8a–d中所示的实施方式中,在图8a和8b中示出的处理步骤对应于按照图7a和7b的相应的处理步骤,这些处理步骤已经在上面做了说明。
在图8b中,附图标记SL表示一个锯割线,沿着该锯割线实施锯割过程,以达到按照图8c的处理状态。在该锯割过程中形成至粘合材料50的侧边通道1b。合适地,在锯割过程之前,将压力传感器芯片5相对于锯割线SL稍微错开地定位,从而在锯割期间压力传感器芯片的侧边S的最小的边缘区域被去除。
在接着按照图8c的处理状态之后,然后在上述第七实施方式中实施选择地去除粘合材料50,以产生空腔10,这或者通过热处理或者化学的和/或物理的处理来实施。由此形成一种与应力分离的传感器组件,其具有侧边的通道1b用于相应的介质(媒质),例如大气压力。
尽管本发明在前面借助于优选的实施例进行说明,但是本发明不局限于此,而是也可以以其它的方式实施。
本发明当然不局限于所述的微机械的传感器芯片,而是原则上可以应用于任意的半导体芯片。
所述的多环烯烃只是可选择去除的粘合材料的许多实例之一,并且可以设想大量的修改,如例如可UV分解的粘合材料,可以有机溶解的蜡,可无机溶解的物质,等等。
Claims (15)
1.半导体器件,具有:
衬底(1;1');
模制封装(8);和
半导体芯片(5;5'),所述半导体芯片在所述模制封装(8)中在所述衬底(1;1')上方这样地悬置在模制材料处,使得一个空腔(10)将所述半导体芯片(5;5')的整个底面(U;U’)与衬底(1;1')机械地分离,其中,所述空腔(10)沿着所述半导体芯片的一个与所述衬底(1;1')面对的底面(U;U’)延伸。
2.按照权利要求1所述的半导体器件,其中,所述空腔(10)至少部分地沿着所述半导体芯片(5;5')的一个与所述底面(U)连接的侧边(S;S')延伸。
3.按照权利要求1所述的半导体器件,其中,所述半导体芯片(5;5')是压力传感器芯片,所述压力传感器芯片具有设置在所述空腔(10)中的膜片区(M)。
4.按照前述权利要求中任一项所述的半导体器件,其中,所述衬底(1;1')具有通孔(1a)或扩散区(DB;DB1,DB2),通过所述通孔或所述扩散区可以从外部接近所述空腔(10)。
5.按照前述权利要求中任一项所述的半导体器件,其中,在所述衬底(1;1')上方设有一个侧边的通道(1b),通过所述通道可以从外部接近所述空腔(10)。
6.按照前述权利要求中任一项所述的半导体器件,其中,在所述模制封装(8)中设有至少一个另外的半导体芯片(3),所述另外的半导体芯片与所述半导体芯片(5;5')电连接。
7.按照权利要求6所述的半导体器件,其中,所述另外的半导体芯片(3)在所述模制封装(8)中在所述衬底(1;1')上方被如此地悬置在所述模制材料处,使得一个另外的空腔(10')将所述另外的半导体芯片(3)与所述衬底(1;1')机械地分离。
8.用于制造半导体器件的方法,包括步骤:
将粘合材料(50)在晶圆级上安置到多个半导体芯片(5;5')上;
借助于所述粘合材料(50)将半导体芯片(5;5')安置到衬底(1;1')上;
将安置在所述衬底(1;1')上的所述半导体芯片(5;5')封装在一个模制封装(8)中;
选择地去除所述粘合材料(50),由此将所述半导体芯片(5;5')在所述模制封装(8)中在所述衬底(1;1')上方这样地悬置在模制材料处,使得一个空腔(10)将所述半导体芯片(5;5')与所述衬底(1;1')机械地分离。
9.按照权利要求8所述的方法,其中,借助于所述粘合材料(50)的熔化将所述半导体芯片(5;5')施加到所述衬底(1;1')上。
10.按照权利要求8或9所述的方法,其中,所述粘合材料(50)以热的方式被选择地去除。
11.按照权利要求8或9所述的方法,其中,所述粘合材料(50)以化学的方式和/或以物理的方式被选择地去除。
12.按照前述权利要求8至11中任一项所述的方法,其中,所述衬底(1;1')在所述粘合材料(50)的区域中具有通孔(1a),由此所述粘合材料(50)被选择地去除。
13.按照前述权利要求8至11中任一项所述的方法,其中,所述衬底(1;1')在所述粘合材料(50)的区域中具有扩散区(DB;DB1,DB2),由此粘合材料(50)被选择地去除。
14.按照前述权利要求8至11中任一项所述的方法,其中,在封装之后实施锯割步骤,通过所述锯割步骤使所述粘合材料(50)通过侧边的通道(1b)暴露出来,在此之后通过所述侧边的通道(1b)实施对所述粘合材料(50)的选择的去除。
15.按照前述权利要求8至14中任一项所述的方法,其中,所述粘合材料(50)具有一种多环烯烃。
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8748231B2 (en) * | 2011-08-23 | 2014-06-10 | Amphenol Thermometrics, Inc. | Component assembly using a temporary attach material |
US8704370B2 (en) * | 2012-06-29 | 2014-04-22 | Freescale Semiconductor, Inc. | Semiconductor package structure having an air gap and method for forming |
DE102012224424A1 (de) * | 2012-12-27 | 2014-07-17 | Robert Bosch Gmbh | Sensorsystem und Abdeckvorrichtung für ein Sensorsystem |
WO2014130047A1 (en) * | 2013-02-25 | 2014-08-28 | General Electric Company | Component assembly using a temporary attach material |
DE102013210535A1 (de) | 2013-06-06 | 2014-12-11 | Robert Bosch Gmbh | Gehäusevorrichtung für ein elektronisches Modul und Verfahren zum Herstellen einer Gehäusevorrichtung für ein elektronisches Modul |
DE102013226686A1 (de) * | 2013-12-19 | 2015-06-25 | Robert Bosch Gmbh | Verfahren zum Herstellen eines elektronischen Bauteils, bei dem ein Sensor-Element von dem Grundmaterial schwingungs- und thermomechanisch entkoppelt ist, sowie elektronisches Bauteil |
DE102015224499A1 (de) * | 2015-12-08 | 2017-06-08 | Robert Bosch Gmbh | Spannungsreduzierung beim Laserwiederverschluss durch Temperaturerhöhung |
US10800651B2 (en) | 2016-05-06 | 2020-10-13 | Analog Devices, Inc. | Low stress integrated device packages |
US20170328197A1 (en) * | 2016-05-13 | 2017-11-16 | Ningbo Wanyou Deepwater Energy Science & Technolog Co.,Ltd. | Data Logger, Manufacturing Method Thereof and Real-time Measurement System Thereof |
CN106531694B (zh) * | 2016-12-06 | 2020-04-21 | 歌尔股份有限公司 | 一种环境传感器 |
DE102018222685A1 (de) * | 2018-12-20 | 2020-06-25 | Robert Bosch Gmbh | Verfahren zur Herstellung einer mikromechanischen Vorrichtung mit Dämpferstruktur |
US11702335B2 (en) | 2020-12-04 | 2023-07-18 | Analog Devices, Inc. | Low stress integrated device package |
US11495522B2 (en) * | 2020-12-14 | 2022-11-08 | Texas Instruments Incorporated | Suspended semiconductor dies |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1449036A (zh) * | 2002-03-28 | 2003-10-15 | 三菱电机株式会社 | 树脂模制型器件及其制造装置 |
EP1717562A1 (en) * | 2005-04-29 | 2006-11-02 | Sensirion AG | A method for packaging integrated sensors |
DE102006026881A1 (de) * | 2006-06-09 | 2007-12-13 | Robert Bosch Gmbh | Mikromechanisches Bauelement |
CN101091245A (zh) * | 2004-09-30 | 2007-12-19 | 英飞凌科技股份公司 | 半导体器件中不同部件界面间的层及其制造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0828396B2 (ja) * | 1992-01-31 | 1996-03-21 | 株式会社東芝 | 半導体装置 |
WO1999000844A2 (en) * | 1997-06-30 | 1999-01-07 | Formfactor, Inc. | Sockets for semiconductor devices with spring contact elements |
US6122171A (en) * | 1999-07-30 | 2000-09-19 | Micron Technology, Inc. | Heat sink chip package and method of making |
US6335224B1 (en) * | 2000-05-16 | 2002-01-01 | Sandia Corporation | Protection of microelectronic devices during packaging |
US6548895B1 (en) * | 2001-02-21 | 2003-04-15 | Sandia Corporation | Packaging of electro-microfluidic devices |
US7166911B2 (en) * | 2002-09-04 | 2007-01-23 | Analog Devices, Inc. | Packaged microchip with premolded-type package |
WO2005054804A1 (en) * | 2003-12-04 | 2005-06-16 | National University Of Singapore | Capacitive pressure sensor with a cantilever member |
US7825484B2 (en) * | 2005-04-25 | 2010-11-02 | Analog Devices, Inc. | Micromachined microphone and multisensor and method for producing same |
US7202552B2 (en) * | 2005-07-15 | 2007-04-10 | Silicon Matrix Pte. Ltd. | MEMS package using flexible substrates, and method thereof |
DE102005053765B4 (de) * | 2005-11-10 | 2016-04-14 | Epcos Ag | MEMS-Package und Verfahren zur Herstellung |
US7661318B2 (en) * | 2006-02-27 | 2010-02-16 | Auxitrol S.A. | Stress isolated pressure sensing die, sensor assembly inluding said die and methods for manufacturing said die and said assembly |
DE602007013484D1 (de) * | 2006-02-27 | 2011-05-12 | Auxitrol Sa | Spannungsisolierter Drucksensorchip |
US7781852B1 (en) * | 2006-12-05 | 2010-08-24 | Amkor Technology, Inc. | Membrane die attach circuit element package and method therefor |
US7550828B2 (en) * | 2007-01-03 | 2009-06-23 | Stats Chippac, Inc. | Leadframe package for MEMS microphone assembly |
ITMI20070099A1 (it) * | 2007-01-24 | 2008-07-25 | St Microelectronics Srl | Dispositivo elettronico comprendente dispositivi sensori differenziali mems e substrati bucati |
TW201019453A (en) * | 2008-11-05 | 2010-05-16 | Windtop Technology Corp | MEMS package |
JP5045769B2 (ja) * | 2009-03-04 | 2012-10-10 | 株式会社デンソー | センサ装置の製造方法 |
JP5590814B2 (ja) * | 2009-03-30 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
JP2010245337A (ja) * | 2009-04-07 | 2010-10-28 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8748231B2 (en) * | 2011-08-23 | 2014-06-10 | Amphenol Thermometrics, Inc. | Component assembly using a temporary attach material |
-
2010
- 2010-02-09 DE DE102010001711A patent/DE102010001711A1/de not_active Withdrawn
- 2010-12-20 EP EP10792943.2A patent/EP2534092B1/de not_active Not-in-force
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- 2010-12-20 CN CN201080063369.7A patent/CN102741154B/zh not_active Expired - Fee Related
- 2010-12-20 WO PCT/EP2010/070278 patent/WO2011098187A2/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1449036A (zh) * | 2002-03-28 | 2003-10-15 | 三菱电机株式会社 | 树脂模制型器件及其制造装置 |
CN101091245A (zh) * | 2004-09-30 | 2007-12-19 | 英飞凌科技股份公司 | 半导体器件中不同部件界面间的层及其制造方法 |
EP1717562A1 (en) * | 2005-04-29 | 2006-11-02 | Sensirion AG | A method for packaging integrated sensors |
DE102006026881A1 (de) * | 2006-06-09 | 2007-12-13 | Robert Bosch Gmbh | Mikromechanisches Bauelement |
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