CN102739555B - Data transmission method and data interface card - Google Patents
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Abstract
The application discloses a data interface card which comprises a field programmable gate array (FPGA), a special integrated circuit, a first random storage module and a second random storage module, wherein the FPGA is used for receiving data of a first format from an upper interface, carrying out deserialization and de-encapsulation on the data of the first format, extracting effective data and the port number of a lower interface, and generating storage state information corresponding to effect data; the effect data is stored to the first random storage module; the storage state information corresponding to the effective data and the port number of the lower interface are stored into the second random storage module; corresponding effective data is read from the first random storage module according to the storage state information of the effective data read from the second random storage module, and the effective data is recovered into a data pocket; and the data pocket is transmitted to the special integrated circuit according to the port number of the lower interface read from the second random storage module. The application also discloses a data transmission method.
Description
Technical field
The application relates to technical field of data storage, particularly relates to a kind of data transmission method and data interface card.
Background technology
In the practical application of technical field of data storage, can run into the situation that first line of a couplet interface type is different from second line of a couplet interface type, the maximum difference of upper connecting port and second line of a couplet interface is mainly manifested in the different of data format and speed.In order to realize the transfer of data between distinct interface, generally field programmable gate array (FPGA can be used, Field ProgrammableGate Array) realize the conversion of data format, and do by the random asccess memory (RAM, RandomAccess Memory) of FPGA outside the coupling that buffering realizes different rates.
Above connecting port is ten thousand mbit ethernet interfaces below, second line of a couplet interface is the group technology (POS in SDH (Synchronous Digital Hierarchy), Pakage Over Synchronous Digital Hierarchy) interface is that example is told about, prior art is the coupling how being realized data different rates by RAM storage.
Fig. 1 is the data interface card block diagram of prior art, mainly comprises FPGA 101, application-specific integrated circuit (ASIC) 107 and random memory module 108 (comprising 4 RAM).Wherein, FPGA 101 comprises:
Ethernet mac nucleus module (Ethernet MAC Core) 102, for completing the conversion of serial ether data to parallel data, then extracting effective Ethernet message and sending to first user logic module.
First user logic module (User Logic (1)) 103, for completing the decapsulation of Ethernet message, extract the information that application-specific integrated circuit (ASIC) (ASIC) 107 needs, and be finally packaged into set form, be stored in random memory module 108 by RAM controller 104.
Wherein, the packets of information that application-specific integrated circuit (ASIC) 107 needs contains port numbers (Port_number) and data (data).
RAM controller (RAM Controller) 104, for carrying out control and management to random memory module 108.
Second user logic module (User Logic (2)) 105, for data being read from random memory module 108, and is sent to downstream interface 106 the data transaction interface shape that becomes downstream interface 106 to use read.
Downstream interface (DOWN Stream Interface) 106, for the data from the second user logic module 105 are sent to application-specific integrated circuit (ASIC) 107 with the interface shape of standard, the interface of standard includes but not limited to as the 4th layer of second stage system packet interface (SPI-4.2, System Packet interface Level 4, Phase 2), POS-PHYLevel 2 (POS-PHYlevel 2, Pakage Over Synchronous Digital Hierarchy PHY level 2) interface, POS-PHY Level 3 (POS-PHY level 3, Pakage Over Synchronous Digital Hierarchy PHYlevel 3) interface etc.
Application-specific integrated circuit (ASIC) 107, for the conversion of the serial physical interface of the interface to the second line of a couplet that realize standard.Serial physical port is as optical interface.
Based on above-mentioned system configuration, the data format in random memory module 108 as shown in Figure 2.Random memory module 108 comprises the identical N number of parallel port of structure.For each port, need in ram space, mark off buffer descriptor table (BDT, Buffer Descriptor Table) and data storage area two parts, wherein buffer descriptor table is as depositing a circular linked list, and data storage area is for storing data.For port 0, buffer descriptor table comprises M node, and wherein i-th node comprises (1≤i<M, 1≤j):
Data buffer zone pointer i, points to the first address of data block corresponding to this node in RAM;
Valid data byte length j, for showing the valid data byte length of the data block that this node is corresponding;
Next node pointer, is used in reference to the first address of the i-th+1 node in RAM.
M node comprises:
Data buffer zone pointer M, points to the first address of data block corresponding to this node in RAM;
Valid data byte length j, for showing the valid data byte length of the data block that this node is corresponding;
Next node pointer, is used in reference to the first address of the 1st node in RAM.
It should be noted that the valid data byte length of the data block that different node is corresponding is not necessarily identical.
Based on storage mode above, FPGA needs to safeguard buffer descriptor table, introduces the processing procedure of FPGA in storing process below for node i (1≤i<M):
(1) first, according to the valid data byte length of the data buffer zone pointer i-1 of (i-1) node and data block corresponding to the i-th-1 node, the data buffer zone pointer i of this corresponding node is calculated.
(2) then, according to the data sended over from first user logic module 103, the i-th node is calculated corresponding
The valid data byte length of data block.
(3) last, according to the valid data byte length of the i-th node pointer and data block corresponding to the i-th node, calculate
Go out the pointer of the i-th+1 node.
The process read from RAM, needs to do and store contrary action, just repeats no more here.
There is following shortcoming in the RAM data storage method in available data interface card:
1, the capacity of RAM is not fully used, and needs the ram space taking a part to deposit buffer descriptor table time data store;
2, reduce the bandwidth that data store, need to take fractional bandwidth time data store and visit ram space corresponding to buffer descriptor table;
3, the codes implement of FPGA is relatively complicated, because need FPGA to realize the maintenance of buffer descriptor table time data store, and needs when reading data the pointer first obtaining data buffer zone, then extracts data according to total data length.
Because above-mentioned shortcoming can cause the memory capacity of RAM to reduce and access speed reduction, have impact on the maximum data bandwidth of second line of a couplet port.
Summary of the invention
This application provides a kind of data transmission method and data interface card, effectively can improve memory capacity and the access speed of RAM in data interface card, improve the maximum data bandwidth of second line of a couplet port.
A kind of data interface card that the embodiment of the present invention provides, comprise field programmable gate array (FPGA), application-specific integrated circuit (ASIC) and the first random memory module, described data interface card also comprises the second random memory module;
Described first formatted data, for receiving the first formatted data from upper connecting port, is carried out decapsulation after serioparallel exchange, is extracted the port numbers of valid data and second line of a couplet interface by described FPGA; According to the length of valid data and the buffer memory form of setting, generate storaging state information corresponding to valid data, the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory; Described valid data are stored into the first random memory module, the port numbers of storaging state information corresponding for described valid data and second line of a couplet interface is stored into the second random memory module; The storaging state information that described valid data are corresponding comprises packet original position, packet end position, valid data byte length; And from the second random memory module, read the storaging state information of valid data, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length and revert to packet, according to the port numbers of the second line of a couplet interface read from the second random memory module by described Packet Generation to application-specific integrated circuit (ASIC);
Application-specific integrated circuit (ASIC) is used for the packet received to be converted to the second formatted data, and described second formatted data is sent to second line of a couplet interface;
Wherein, according to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and the concrete methods of realizing of buffer memory is: according to the length of valid data and the bit wide of the first random memory module, calculate the length of the storable packet of the first random memory module per unit bit wide, thus the packet original position calculated in the storaging state information that described in the second random memory module per unit bit wide, valid data are corresponding, packet end position, valid data byte length, the packet original position, the packet end position that calculate described in encapsulating successively by the unit bit wide sum of the first random memory module and the second random memory module, the port numbers of valid data byte length and described second line of a couplet interface and valid data part corresponding to this valid data byte length are set form and buffer memory, until the whole buffer memory of valid data completes.
Preferably, the described first random memory module comprises 4 random access memory rams, and total bit wide is 64, and the second random memory module comprises 1 random asccess memory, and total bit wide is 8.
Preferably, described first formatted data is ether data, and the second formatted data is optical network data.
Preferably, described FPGA comprises: ethernet mac nucleus module, first user logic module, RAM controller, the second user logic module and downstream interface;
Described serial ether data, for receiving the serial ether data from upper connecting port, are converted to parallel data, and extract effective Ethernet message by described ethernet mac nucleus module;
First user logic module, effective Ethernet message for being exported by ethernet mac nucleus module carries out decapsulation, extract the port numbers of valid data and second line of a couplet interface, according to the length of valid data and the buffer memory form of setting, generate valid data corresponding storaging state information, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and buffer memory, by RAM controller, the described valid data in buffer memory are stored in the first random memory module, the port numbers of storaging state information corresponding for the described valid data in buffer memory and second line of a couplet interface is stored in the second random memory module,
RAM controller, for carrying out access control management to the first random memory module and the second random memory module;
Second user logic module, for reading storaging state information corresponding to valid data by RAM controller from the second random memory module, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length by RAM controller, described valid data converted to interface shape that downstream interface uses and be sent to downstream interface corresponding to the port numbers of the second line of a couplet interface read from the second random memory module;
Downstream interface, for being sent to application-specific integrated circuit (ASIC) by the data from the second user logic module with the interface shape of standard.
Preferably, the interface of described standard is SPI-4.2 interface.
Preferably, total bit wide of the described first random memory module and the second random memory module is less than or equal to the maximum bit wide that RAM controller is supported.
The embodiment of the present invention additionally provides a kind of data transmission method, and described transfer of data is realized by data interface card described above, comprises the steps:
A, receive the first formatted data from upper connecting port, after described first formatted data is carried out serioparallel exchange, decapsulation extracts the port numbers of valid data and second line of a couplet interface; According to the length of valid data and the buffer memory form of setting, generate storaging state information corresponding to valid data, the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory; The storaging state information that described valid data are corresponding comprises packet original position, packet end position and valid data byte length;
B, by the valid data sealed storage in buffer memory to the first random memory module, the port numbers of storaging state information corresponding for the valid data in buffer memory and second line of a couplet interface is stored into the second random memory module;
C, from the second random memory module, read storaging state information corresponding to valid data, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length and revert to packet, according to the port numbers of the second line of a couplet interface read from the second random memory module by described Packet Generation to application-specific integrated circuit (ASIC);
The packet received is converted to the second formatted data by D, application-specific integrated circuit (ASIC), and described second formatted data is sent to second line of a couplet interface;
Wherein, according to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and the concrete methods of realizing of buffer memory is: according to the length of valid data and the bit wide of the first random memory module, calculate the length of the storable packet of the first random memory module per unit bit wide, thus the packet original position calculated in the storaging state information that described in the second random memory module per unit bit wide, valid data are corresponding, packet end position, valid data byte length, the packet original position, the packet end position that calculate described in encapsulating successively by the unit bit wide sum of the first random memory module and the second random memory module, the port numbers of valid data byte length and described second line of a couplet interface and valid data part corresponding to this valid data byte length are set form and buffer memory, until the whole buffer memory of valid data completes.
Preferably, the bit wide of described valid data is 64, and the bit wide of the storaging state information that valid data are corresponding is 8.
Preferably, described first formatted data is ether data, and the second formatted data is optical network data.
As can be seen from the above technical solutions, store with different random incoming memory respectively by valid data with corresponding storaging state information, the principle of the first-in first-out of demand fulfillment complete message, data and storaging state information corresponding to data obtain simultaneously, take full advantage of the readwrite bandwidth of RAM, make the present invention more can meet the higher field of interface rate.Under the condition of identical message size, identical message amount, the total amount of data stored in RAM is fewer than existing technical scheme, and the part that wherein data volume reduces is buffer descriptor table.So namely expanding the ram space for storing valid data, more can meet the larger application scenarios of data volume buffer memory; And the codes implement of FPGA is comparatively simple, need not go to safeguard buffer descriptor table again, reduce the design difficulty of FPGA, shorten the construction cycle of product.
Accompanying drawing explanation
Fig. 1 is the data interface card block diagram of prior art;
Fig. 2 is the data format schematic diagram in the random memory module 108 shown in Fig. 1;
The data interface card block diagram that Fig. 3 provides for the embodiment of the present invention;
Fig. 4 carries out the flow chart of transfer of data for data interface card that the embodiment of the present invention provides;
Fig. 5 is the set form schematic diagram of cache information in the first user logic module 303 shown in Fig. 3;
Fig. 6 is the data format schematic diagram in the first random memory module 308 shown in Fig. 3 and the second random memory module 309;
Fig. 7 is the data format schematic diagram of data buffer storage in first user logic module 303 of 66 bytes being sent to port one in an embody rule example.
Embodiment
Core concept of the present invention is: use different RAM to store respectively valid data and state data memory information, change the serial acquisition storaging state information of data and the flow process of data in prior art into run simultaneously and obtain data storaging state information and data, thus improve the memory bandwidth of data.
The data transmission method that the application provides comprises the steps:
A, receive the first formatted data from upper connecting port, after described first formatted data is carried out serioparallel exchange, decapsulation extracts the port numbers of valid data and second line of a couplet interface; According to the length of valid data and the buffer memory form of setting, generate storaging state information corresponding to valid data, the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory; The storaging state information that described valid data are corresponding comprises packet original position, packet end position and valid data byte length;
B, by the valid data sealed storage in buffer memory to the first random memory module, the port numbers of storaging state information corresponding for the valid data in buffer memory and second line of a couplet interface is stored into the second random memory module;
C, from the second random memory module, read storaging state information corresponding to valid data, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length and revert to packet, according to the port numbers of the second line of a couplet interface read from the second random memory module by described Packet Generation to application-specific integrated circuit (ASIC);
D, application-specific integrated circuit (ASIC) are used for the packet received to be converted to the second formatted data, and described second formatted data is sent to second line of a couplet interface.
In described steps A, according to the length of valid data and the buffer memory form of setting, generate valid data corresponding storaging state information, to be the concrete methods of realizing of set form be the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface:
According to the length of valid data and the bit wide of the first random memory module, calculate the length of the storable packet of the first random memory module per unit bit wide, thus the packet original position, the packet end position that calculate in the storaging state information that described in the second random memory module per unit bit wide, valid data are corresponding, valid data byte length; The packet original position, the packet end position that calculate described in encapsulating successively by the unit bit wide sum of the first random memory module and the second random memory module, the port numbers of valid data byte length and described second line of a couplet interface and valid data part corresponding to this valid data byte length are set form and buffer memory, until the whole buffer memory of valid data completes.
For making the know-why of technical scheme, feature and technique effect clearly, below in conjunction with specific embodiment, technical scheme is described in detail.
The data interface card that the embodiment of the present invention provides as shown in Figure 3, mainly comprises FPGA 301, the random memory module of application-specific integrated circuit (ASIC) 307, first 307 (comprising 4 RAM) and the second random memory module 309 (comprising a slice RAM).Wherein, FPGA 301 comprises:
Ethernet mac nucleus module (Ethernet MAC Core) 302, for completing ether data from upper connecting port to the conversion of FPGA internal user interface, namely complete the conversion of serial ether data to parallel data, then extract effective Ethernet message and send to first user logic module.
First user logic module (User Logic (1)) 303, carries out decapsulation for the effective Ethernet message exported by ethernet mac nucleus module 302, extracts the port numbers of valid data and second line of a couplet interface; According to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding; The port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory, by RAM controller 304, valid data are stored in the first random memory module 308, the port numbers of the storaging state information of valid data and second line of a couplet interface is stored into the second random memory module 309.The storaging state information of described valid data comprises the port numbers of packet original position, packet end position, valid data byte length and second line of a couplet interface in the second random memory module 309 unit bit wide memory block.
RAM controller (RAM Controller) 304, for carrying out access control management to the first random memory module 308 and the second random memory module 309.
Second user logic module (User Logic (2)) 305, for being read the storaging state information of valid data from the second random memory module 309 by RAM controller 304, according to read packet original position, the beginning of packet end position determination packet and end, from the first random memory module 308, corresponding valid data are read according to valid data byte length, and described valid data converted to according to the port numbers of second line of a couplet interface read from the second random memory module 309 interface shape that downstream interface 306 uses and be sent to downstream interface 306.
Downstream interface (DOWN Stream Interface) 306, for the data from the second user logic module 305 are sent to application-specific integrated circuit (ASIC) 307 with the interface shape of standard, the interface of standard includes but not limited to as SPI 4.2 interface, POS-PHY Level 2 interface, POS-PHY Level 3 interface, POS level II etc.
The data interface card that the embodiment of the present invention provides carries out the flow process of transfer of data as shown in Figure 4, comprises the steps:
Step 401: confirm buffer memory in first user logic module 303 data content and form.The data stored are except comprising the most basic information as port numbers (Port_number), valid data byte length (Valid_byte_length), valid data (data) outward, also need additionally to increase by two bits---packet original position (SOP, Start of Package), packet end position (EOP, End of Package).The effect of SOP and EOP is used to beginning and the end of a discriminating packet.
Step 402:FPGA completes the information relevant to state data memory and generates.The port numbers of valid data and second line of a couplet interface is extracted in the packet that first user logic module 303 sends from upper connecting port, and according to the length of valid data and the buffer memory form of setting, generate valid data corresponding storaging state information SOP, EOP and valid data byte length; Then encapsulation is carried out and buffer memory according to buffer memory form as shown in Figure 5.In the data interface card that the embodiment of the present invention provides, in first user logic module 303, the form of the data of buffer memory is as shown in Figure 5.Wherein, original RAM1 to RAM4 stores valid data (64bit), newly-increased RAM5 (8bit) stores state information corresponding to valid data, i.e. SOP (1bit), EOP (1bit), port numbers (3bit), valid data byte length (3bit).The value of above-mentioned storaging state information is the value of the port numbers of packet original position, packet end position, valid data byte length and the second line of a couplet interface of corresponding valid data in the second random memory module 309 in unit bit wide memory block.
Step 403:RAM controller 304 is by the content SOP relevant to the storaging state information of packet, and EOP, Port_number, Valid_byte_length are stored in the second random memory module 309 (RAM5 see in Fig. 6); Valid data are stored in the first random memory module 308 (RAM1 ~ RAM4 see in Fig. 6).See in Fig. 6, respectively the valid data of buffer memory in the first user logic module 303 illustrated in Fig. 5 are stored in RAM1 ~ RAM4, and the storaging state information part of buffer memory in Fig. 5 is stored in RAM5.
Step 404:RAM controller 304 is sense data from the first random memory module 308 and the second random memory module 309, recover complete packet according to SOP and EOP and issue the second user logic module 305, finally by downstream interface 306 by Packet Generation to application-specific integrated circuit (ASIC) 307.
Below by way of an embody rule example, the present invention program is described.Transform existing data interface card, the basis of 4 RAM of available data interface card increases the 5th RAM, the 5th RAM of increase is used for storing the storaging state information of valid data.Calculate the bit wide relevant to packet storaging state information, determine the bit wide of the 5th RAM increased, be namely set in form data cached in first user logic module 304.Wherein,
Port numbers: Port_number, X bit.X decides according to concrete port number, if port number is N, so requires that X value is for being more than or equal to log
2the smallest natural number of N.In this application example, port number=8, then X=3.
Valid data byte length: Valid_byte_length, Ybit.Y decides according to the RAM bit wide being used for storing data, if the RAM bit wide being used for storing data is M, so requires that Y value is for being more than or equal to log
2(M/8) smallest natural number.In this application example, bit wide M=64 (i.e. 8 bytes), then Y=3, namely 3bit indicates in data part 8 bytes has several byte effective, and such as 000 represents that 1 byte is effective, and 001 represents that 2 bytes are effective, the like, 111 represent that 8 bytes are effective.
Packet original position: SOP, 1bit;
Packet end position: EOP, 1bit.
Suppose that second line of a couplet port is 8 ports, the bit wide of 4 RAM being used for storing valid data is 64bit, the bit wide of packet storaging state information: 3+3+2=8bit in this case.Namely only need the RAM of an increase 8bit bit wide just can complete the storage of packet storaging state information in this case.In like manner, if storaging state information is many, store storage state information is carried out with regard to needing the relatively large RAM of increase by.
FPGA completes the information relevant to state data memory and generates.FPGA extracts data and Port_number according in the packet sent from upper connecting port, and generates SOP, EOP, Valid_byte_length.
Be illustrated in figure 7 the data instance of 66 bytes being sent to access port 1, the data format of real cache in first user logic module 303 is described.SOP=1 in Fig. 7, represents the beginning of this message; EOP=1 represents the end of this message, and SOP=EOP=0 represents it is the mid portion of message; Port_number=001 represents that this message is sent to access port 1; Valid_byte_length=001 represents that data division only has 2byte to be effective, and Valid_byte_length=111 represents that valid data part 8byte is entirely effective.
Above-mentioned data are written in random asccess memory by RAM controller 304.Specifically, RAM controller 304 will extract with the relevant content SOP of packet storaging state information in the buffer memory of the first logic module 303, EOP, Port_number, Valid_byte_length, and valid data.Then RAM controller 304 is stored in the content of being correlated with packet storaging state information in the 5th RAM newly increased; Valid data are stored in original 4 RAM.The advantage of hinge structure need not go to calculate the data buffer zone pointer in buffer descriptor table and next node pointer again.
Next, RAM controller 304 sense data from random access memory.Specifically, directly read the content in 5 RAM, comprise the storaging state information be stored in the 5th RAM and the data be stored in 1st ~ 4 RAM.FPGA is according to the SOP read out from the 5th RAM, and EOP identifies beginning and the end of a packet; From the data that 1st ~ 4 RAM read out, effective data are restored according to Valid_byte_length; Second user logic module 305 can be put into downstream interface 306 send to application-specific integrated circuit (ASIC) 307 restore valid data according to the Port_number that reads out from the 5th RAM.
The data transmission scheme that the application provides has following beneficial effect:
1) access data very convenient, the principle of the first-in first-out of a demand fulfillment complete message, state and the data of data obtain simultaneously, take full advantage of the readwrite bandwidth of RAM, make the present invention more can meet the higher field of interface rate.
2) under the condition of identical message size, identical message amount, the total amount of data stored in internal memory is fewer than existing technical scheme, and the part that wherein data volume reduces is buffer descriptor table.So namely expanding the ram space for storing valid data, more can meet the larger application scenarios of data volume buffer memory.
3) codes implement of FPGA is comparatively simple, need not go to safeguard buffer descriptor table again, reduce the design difficulty of FPGA, shorten the construction cycle of product.
The foregoing is only the preferred embodiment of the application; not in order to limit the protection range of the application; within all spirit in technical scheme and principle, any amendment made, equivalent replacements, improvement etc., all should be included within scope that the application protects.
Claims (9)
1. a data interface card, comprise on-site programmable gate array FPGA, application-specific integrated circuit (ASIC) and the first random memory module, it is characterized in that, described data interface card also comprises the second random memory module;
Described first formatted data, for receiving the first formatted data from upper connecting port, is carried out decapsulation after serioparallel exchange, is extracted the port numbers of valid data and second line of a couplet interface by described FPGA; According to the length of valid data and the buffer memory form of setting, generate storaging state information corresponding to valid data, the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory; Described valid data are stored into the first random memory module, the port numbers of storaging state information corresponding for described valid data and second line of a couplet interface is stored into the second random memory module; The storaging state information that described valid data are corresponding comprises packet original position, packet end position, valid data byte length; And from the second random memory module, read the storaging state information of valid data, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length and revert to packet, according to the port numbers of the second line of a couplet interface read from the second random memory module by described Packet Generation to application-specific integrated circuit (ASIC);
Application-specific integrated circuit (ASIC) is used for the packet received to be converted to the second formatted data, and described second formatted data is sent to second line of a couplet interface;
Wherein, according to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and the concrete methods of realizing of buffer memory is: according to the length of valid data and the bit wide of the first random memory module, calculate the length of the storable packet of the first random memory module per unit bit wide, thus the packet original position calculated in the storaging state information that described in the second random memory module per unit bit wide, valid data are corresponding, packet end position, valid data byte length, the packet original position, the packet end position that calculate described in encapsulating successively by the unit bit wide sum of the first random memory module and the second random memory module, the port numbers of valid data byte length and described second line of a couplet interface and valid data part corresponding to this valid data byte length are set form and buffer memory, until the whole buffer memory of valid data completes.
2. data interface card according to claim 1, is characterized in that, the described first random memory module comprises 4 random access memory rams, and total bit wide is 64, and the second random memory module comprises 1 random asccess memory, and total bit wide is 8.
3. data interface card according to claim 1, is characterized in that, described first formatted data is ether data, and the second formatted data is optical network data.
4. data interface card according to claim 3, is characterized in that, described FPGA comprises: ethernet mac nucleus module, first user logic module, RAM controller, the second user logic module and downstream interface;
Described serial ether data, for receiving the serial ether data from upper connecting port, are converted to parallel data, and extract effective Ethernet message by described ethernet mac nucleus module;
First user logic module, effective Ethernet message for being exported by ethernet mac nucleus module carries out decapsulation, extract the port numbers of valid data and second line of a couplet interface, according to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and buffer memory, by RAM controller, the described valid data in buffer memory are stored in the first random memory module, the port numbers of storaging state information corresponding for the described valid data in buffer memory and second line of a couplet interface is stored in the second random memory module,
RAM controller, for carrying out access control management to the first random memory module and the second random memory module;
Second user logic module, for reading storaging state information corresponding to valid data by RAM controller from the second random memory module, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length by RAM controller, described valid data converted to interface shape that downstream interface uses and be sent to downstream interface corresponding to the port numbers of the second line of a couplet interface read from the second random memory module;
Downstream interface, for being sent to application-specific integrated circuit (ASIC) by the data from the second user logic module with the interface shape of standard.
5. data interface card according to claim 4, is characterized in that, the interface of described standard is SPI-4.2 interface.
6. data interface card according to claim 4, is characterized in that, total bit wide of the described first random memory module and the second random memory module is less than or equal to the maximum bit wide of RAM controller support.
7. a data transmission method, described transfer of data, by data interface card realization as claimed in claim 1, is characterized in that, comprises the steps:
A, receive the first formatted data from upper connecting port, after described first formatted data is carried out serioparallel exchange, decapsulation extracts the port numbers of valid data and second line of a couplet interface; According to the length of valid data and the buffer memory form of setting, generate storaging state information corresponding to valid data, the port numbers encapsulating storaging state information corresponding to described valid data, valid data and second line of a couplet interface is set form and buffer memory; The storaging state information that described valid data are corresponding comprises packet original position, packet end position and valid data byte length;
B, by the valid data sealed storage in buffer memory to the first random memory module, the port numbers of storaging state information corresponding for the valid data in buffer memory and second line of a couplet interface is stored into the second random memory module;
C, from the second random memory module, read storaging state information corresponding to valid data, according to beginning and the end of read packet original position, packet end position determination packet, from the first random memory module, read corresponding valid data according to valid data byte length and revert to packet, according to the port numbers of the second line of a couplet interface read from the second random memory module by described Packet Generation to application-specific integrated circuit (ASIC);
The packet received is converted to the second formatted data by D, application-specific integrated circuit (ASIC), and described second formatted data is sent to second line of a couplet interface;
Wherein, according to the length of valid data and the buffer memory form of setting, generate the storaging state information that valid data are corresponding, encapsulate described valid data, the port numbers of the storaging state information that valid data are corresponding and second line of a couplet interface is set form and the concrete methods of realizing of buffer memory is: according to the length of valid data and the bit wide of the first random memory module, calculate the length of the storable packet of the first random memory module per unit bit wide, thus the packet original position calculated in the storaging state information that described in the second random memory module per unit bit wide, valid data are corresponding, packet end position, valid data byte length, the packet original position, the packet end position that calculate described in encapsulating successively by the unit bit wide sum of the first random memory module and the second random memory module, the port numbers of valid data byte length and described second line of a couplet interface and valid data part corresponding to this valid data byte length are set form and buffer memory, until the whole buffer memory of valid data completes.
8. method according to claim 7, is characterized in that, the bit wide of described valid data is 64, and the bit wide of the storaging state information that valid data are corresponding is 8.
9. method according to claim 7, is characterized in that, described first formatted data is ether data, and the second formatted data is optical network data.
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| CN111783378B (en) * | 2020-06-30 | 2022-05-17 | 迈普通信技术股份有限公司 | Data processing method and FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1946176A (en) * | 2006-10-11 | 2007-04-11 | 祝万昌 | Device and method for real time high speed receiving and transmitting DVB data |
| CN102055549A (en) * | 2009-11-10 | 2011-05-11 | 中兴通讯股份有限公司 | Rate matching device and method for long term evolution system |
| CN102510322A (en) * | 2011-09-20 | 2012-06-20 | 北京雷久科技有限责任公司 | IO (Input and Output) interface board card and method for transporting data by same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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2012
- 2012-07-24 CN CN201210256982.1A patent/CN102739555B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1946176A (en) * | 2006-10-11 | 2007-04-11 | 祝万昌 | Device and method for real time high speed receiving and transmitting DVB data |
| CN102055549A (en) * | 2009-11-10 | 2011-05-11 | 中兴通讯股份有限公司 | Rate matching device and method for long term evolution system |
| CN102510322A (en) * | 2011-09-20 | 2012-06-20 | 北京雷久科技有限责任公司 | IO (Input and Output) interface board card and method for transporting data by same |
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