CN106571991A - Method and data for transmitting data - Google Patents
Method and data for transmitting data Download PDFInfo
- Publication number
- CN106571991A CN106571991A CN201610985392.0A CN201610985392A CN106571991A CN 106571991 A CN106571991 A CN 106571991A CN 201610985392 A CN201610985392 A CN 201610985392A CN 106571991 A CN106571991 A CN 106571991A
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- Prior art keywords
- frame
- data
- fifo
- ethernet
- physical port
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/44—Star or tree networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/44—Star or tree networks
- H04L2012/445—Star or tree networks with switching in a hub, e.g. ETHERNET switch
Abstract
The invention discloses a method for transmitting data and a device for achieving the method. An Ethernet physical port and an Ethernet transceiver are adopted, and a MAC controller of the Ethernet is not adopted. A data frame, with a destination address, sent by equipment is transmitted to an interface conversion chip, and the output end of the interface conversion chip serves as the Ethernet physical port; the Ethernet physical port of the interface conversion chip is connected with an exchanger Ethernet physical port, an effective data frame is extracted from data flow of the Ethernet physical port through an exchanger, and the data frame is forwarded to the corresponding Ethernet physical port according to the data frame destination address; after the interface conversion chip receives a data packet through the Ethernet physical port, the effective data frame is extracted, and the data frame is output to equipment through a serial port or a parallel port; the equipment connected into the exchanger through the interface conversion chip can achieve remote, high-rate and high-real-time communication by operating the common serial port or parallel port.
Description
Technical field
The invention belongs to industrial control field, and in particular to a kind of data transmission method and device.
Background technology
In Industry Control occasion, ethernet technology obtains large development.Obtain the reliable industry of high speed actual time safety with
Too net network is the target that everybody makes great efforts.Numerous real-time industrial Ethernet technologies use special switch technology, but real
The safety of when property is still difficult to ensure.Reason is Ethernet to be designed for Industry Control originally, and it is big that it is only suitable for transmission
Bag data, Industry Control occasion data traffic are typically small, if using ethernet communication, even transmit the letter of a bit
Breath, it is also desirable to the packet transmission of at least 64 bytes, the utilization rate of bandwidth is 0.2%.Now, comparing successful story is
EtherCAT bussing techniques, it is simultaneously not used switch, possesses higher real-time and safety.But EtherCAT number of buses
According to from main website to slave station, there is certain hysteresis delay at each station, and this delay is superposition, and this just constrains its real-time and enters
One step is lifted.
Existing switching network, such as star and many star networks, have very compared with the fieldbus of traditional master-slave mode
Big superiority.Because the switch of Y-connection ensure that the communication between each bus access point is main logical to master
Letter.Access point failure and will not cause other irrelevant communication failures, the safety of safeguards system.In addition, main to main communication
Agreement can be very simple, therefore develop safe and reliable communications software modules and become easy, has ensured the safety of system.
Again, the communication of the bus of switch type is multipath concurrence, and Point-to-Point Data handling capacity and access device quantity are unrelated, break
The bottleneck of " shared bandwidth ".Last point, communication delay can be controlled.For the control system of high requirement of real time, star
Connection is the method for low cost.
The content of the invention
In order that Ethernet transmission medium is adapted to real-time Transmission short frame data, short frame data is inserted with using hardware circuit
In the ethernet transceiver data flow of minimum data length；Realize from the ethernet transceiver data for having minimum data length simultaneously
The function of short data frame is extracted in stream；During data transfer, using star-like connection, data are forwarded through switch, it is possible to reduce
The delayed time delay of this kind of buses of EtherCAT, makes communication possess higher real-time.
Based on above-mentioned purpose, the present invention proposes a kind of data transmission method, including,
It is connecing for Ethernet physical port that equipment passes through serial ports or parallel port Frame of the transmission with destination address to outfan
Mouth conversion chip, the Ethernet physical port of the interface conversion chip are connected with switch Ethernet physical port, switch
From extracted valid data frame in Ethernet physical port data flow, and according to Frame destination address, Frame is forwarded to into phase
The Ethernet physical port answered；
After the Ethernet physical port of interface conversion chip receives Frame, effective Frame is extracted, and this is counted
Exported to equipment by serial ports or parallel port according to frame；
Described serial ports includes synchronization or asynchronous serial port；
It is characterized in that：The Ethernet physical port of the interface conversion chip and switch only retains PHY work(
Can, support without MAC functions；The Frame band destination address, the span of the length of the Frame is 8 bytes to 256
Byte；When have to be passed through Frame that Ethernet physical port sends it is ready when, if not actuated packet sends, open immediately
Dynamic packet sends, and after Frame is sent completely, if not having other Frames ready, sends do-nothing instruction frame, and Frame is opened
Keep sending up to data packet byte number for Frame to exceed the maximum number of byte that ethernet transceiver specifies after dynamic, send out when continuous
When sending the do-nothing instruction frame and data packet byte number of amount to have been over the minimum byte number of ethernet transceiver regulation, knot
Beam data bag sends；Too net physical port is completely received without waiting for packet after data are received, and exchange opportunity is from data
Stream extracted valid data frame, is then forwarded according to the destination address of Frame, for interface conversion chip then can be by data
Frame is exported to equipment by serial ports or parallel port.
Based on above-mentioned purpose, the present invention also proposes a kind of data transmission device, including exchanger chip, the exchanger core
Piece includes：
Multichannel Ethernet physical port, Ethernet physical port described in per road include：Transmitting-receiving control module, reception annular
FIFO, transmission FIFO, Frame inserter, Frame separator,
One shared switching engine；
The transmitting-receiving control module is responsible for for ethernet transceiver receiving data storage to annular FIFO is received, while negative
Duty is by data is activation in transmission FIFO to ethernet transceiver；The reception annular FIFO is cached for receiving data；The transmission
FIFO is transmission data buffer storage；The Frame that the Frame inserter is responsible for sending is inserted into transmission data buffer storage
FIFO；The Frame separator is responsible for isolating Frame from the data flow for receiving；The switching engine is responsible for control
The exchange of each circuit-switched data frame, described Frame inserter, Frame separator are by switching engine control；
Introducing Frame inserter, Frame separator carries out data flow con-trol with reference to switching engine；Described Frame
Separator judges data frame length to determine Frame by parsing Frame specified byte, while determining next frame beginning position
Put；
After described Frame separator isolates Frame from the data flow for receiving, switching engine will trigger number
According to frame inserter, Frame is moved in the transmission FIFO of destination interface；
Further, the Frame separator is for isolating Frame from the data flow for receiving, and by exchanging
Engine is moved to Frame in the transmission FIFO of destination interface, produces Frame ready after mobile data frame first character section
Signal.
Further, also including interface conversion chip, the interface conversion chip includes：
Serial ports or parallel port module, transmitting-receiving control module, reception annular FIFO, transmission FIFO, Frame inserter, Frame
Separator, controls engine；
The serial ports or parallel port module realize serial ports or parallel port function, and band transmitting-receiving caching, the transmitting-receiving control module are responsible for
Ethernet transceiver is received into data storage to receiving annular data fifo, at the same be responsible for sending data fifo send to
Too net transceiver；The reception annular FIFO is cached for receiving data；The transmission FIFO is transmission data buffer storage；The data
The Frame that frame inserter is responsible for sending is inserted into transmission data buffer storage FIFO；The Frame separator is responsible for receiving
To data flow in isolate Frame；The control engine is responsible for the data of serial ports or parallel port module and Ethernet physical port
Transmission, described Frame inserter, Frame separator, serial ports or parallel port module are by controlling engine control；
Introducing Frame inserter, Frame separator combination control engine carries out data flow con-trol；Described Frame
Separator judges data frame length to determine Frame by parsing Frame specified byte, while determining next frame beginning position
Put；
After described Frame separator isolates Frame from the data flow for receiving, control engine will trigger number
According to frame inserter, Frame is moved to into serial ports or parallel port module is sent in caching.
Further, after Frame separator isolates Frame from the data flow for receiving, switching engine is by number
Serial ports is moved to according to frame or parallel port sends caching, after mobile data frame first character section, produce Frame ready signal.
Further, when data receiver, cache without serial ports or parallel port module, write direct reception annular FIFO.
The invention has the beneficial effects as follows：Ethernet transmission medium is made to be adapted to real-time Transmission short frame data, using hardware circuit
Short frame data is inserted with the ethernet transceiver data flow of minimum data length；Simultaneously realize from there is minimum data length
The function of short data frame is extracted in ethernet transceiver data flow；During data transfer, using star-like connection, data are through switch
Forwarding, it is possible to reduce the delayed time delay of this kind of buses of EtherCAT, makes communication possess higher real-time.
Description of the drawings
Fig. 1 is access device hardware connection figure；
Fig. 2 is exchange hardware connection figure；
Fig. 3 is eight byte instruction frames；
Fig. 4 is that packet extends frame；
Fig. 5 is annular FIFO；
Fig. 6 is that interface conversion chip sends schematic diagram；
Fig. 7 is interface conversion chip record principle figure；
Fig. 8 is interface conversion chip module figure；
Fig. 9 is switch main control chip module figure.
Specific embodiment
Below by taking one embodiment as an example, the specific implementation of the present invention is described.
As shown in figure 1, being access device hardware connection figure.Access device 101, interface conversion chip 102, Ethernet transmitting-receiving
Device 103, network transformer 104 are linked in sequence；Ethernet transceiver adds Ethernet network transformer 104 to constitute Ethernet physics end
Mouthful；Fig. 2 is exchange hardware connection figure, and each port of switch is above-mentioned Ethernet physical port.
A kind of embodiment of the interface conversion chip is the quasi- chip that fpga chip is constituted.
A kind of embodiment of the exchanger chip is the quasi- chip that fpga chip is constituted.
The embodiment of the common port has UART, SPI, parallel port.
A kind of embodiment of the ethernet transceiver interface is RMII interfaces.
The network transformer, a kind of embodiment also include RJ45 Ethernet interface terminals.
A kind of embodiment of the switch is shown in Fig. 2.
102 structure chart of interface conversion chip is shown in Fig. 8.Including serial ports or parallel port module, transmitting-receiving control module, reception ring
Shape FIFO, transmission FIFO, Frame inserter, Frame separator, control engine；
The reception annular FIFO illustrates Fig. 5, is characterized in that next byte of the trail byte of FIFO is the first byte of FIFO.
The serial ports or parallel port module realize serial ports or parallel port function, and band transmitting-receiving caching, the transmitting-receiving control module are responsible for
Ethernet transceiver is received into data storage to receiving annular data fifo, at the same be responsible for sending data fifo send to
Too net transceiver；The reception annular FIFO is cached for receiving data；The transmission FIFO is transmission data buffer storage；The data
The Frame that frame inserter is responsible for sending is inserted into transmission data buffer storage FIFO；The Frame separator is responsible for receiving
To data flow in isolate Frame；The control engine is responsible for the data of serial ports or parallel port module and Ethernet physical port
Transmission, described Frame inserter, Frame separator, serial ports or parallel port module are by controlling engine control；
The switch main control chip structure chart is shown in Fig. 9.Including per the module that ethernet port is included all the way：Transmitting-receiving control
Module, reception annular FIFO, transmission FIFO, Frame inserter, Frame separator,
One shared switching engine；
The transmitting-receiving control module is responsible for for ethernet transceiver receiving data storage to annular FIFO is received, while negative
Duty is by data is activation in transmission FIFO to ethernet transceiver；The reception annular FIFO is cached for receiving data；The transmission
FIFO is transmission data buffer storage；The Frame that the Frame inserter is responsible for sending is inserted into transmission data buffer storage
FIFO；The Frame separator is responsible for isolating Frame from the data flow for receiving；The switching engine is responsible for control
The exchange of each circuit-switched data frame, described Frame inserter, Frame separator are by switching engine control；
Access device and switch and interface conversion chip, preferably support following data frame format (Fig. 3).
Frame is divided into 2 kinds.
A kind of Frame is 8 byte instruction frame of regular length, and a kind of Frame is to be added with 8 byte instruction frame formats beginning tail
Packet of the total length less than 248 extends the data packet frame of frame.
3) form of command frame is：
DST：Destination address byte
SRC：Send address byte
CTR：Frame data type-byte, contains data length information
ID：Frame number byte
D3-D0：4 byte of data
CRC：Check byte, this check byte are the results that the verification of front 7 bytes is calculated, if data are in transmit process
In be destroyed, the CRC results and the CRC that sends over that recipient is calculated according to the verification of front 7 bytes for receiving can differ
Cause, can thus detect the generation for making mistake.The check byte of 4 bytes hereafter is also the same principle.
4) form of packet extension frame is (Fig. 4)：
DN-D0：Data, length are the D3 byte values in 8 byte instruction frames of data packet frame beginning, data packet frame total length
No more than 256；
CRC1-CRC4：Check byte.
In order to realize data exchanging function, exchanger chip must remember each Ethernet physical port correspondence by study
Data frame address；The method and step of realization is as follows：
1), during system start-up, switch sends each access interface device numbering of instructions query, or each access interface equipment
Active report device numbering；
2) subsequently, each port device numbering is stored in list by switch；
3) master controller is periodically detected whether access interface device numbering is changed, and updates port numbering list, so
The hot plug of equipment can be realized.
The method of data transfer includes：
Equipment send the Frame with destination address pass through serial ports or and port transmission to interface conversion chip, interface conversion
Chip output is Ethernet physical port；
The Ethernet physical port of interface conversion chip is connected with switch Ethernet physical port, and switch is from Ethernet
Extracted valid data frame in physical port data flow, and according to Frame destination address, Frame is forwarded to into corresponding ether
Net physical port；
After interface conversion chip Ethernet physical port receives packet, effective Frame is extracted, and by this data
Frame is exported to equipment by serial ports or parallel port；
Described Ethernet physical port packet sends and Frame to send be different concepts, Ethernet physical port
There is the restriction of 64 byte of minimum length and greatest length when sending data, the data flow which sends is data packet form, therefore one
Individual packet can include the Frame of many present embodiment.
Interface conversion chip is similar with the internal structure of exchanger chip, and it is that control multichannel is exchanged that difference is switch,
Interface conversion chip is to control data transfer all the way, and 2 kinds of chips of the present invention include common Frame separator and Frame
Inserter.
Frame separator and Frame inserter are to realize core that short data frame is transmitted in ethernet data stream,
It is the key for being different from traditional ethernet data transfer.
Frame separator, attachment structure such as (Fig. 7), Frame separator by parse Frame destination address byte and
Frame control byte obtains data frame length, and determines next frame beginning location with this；The position of Frame and information quilt
Among being placed on a list；These information of switching engine according to Frame, extract destination address, carry out data forwarding, from
And realize port data function of exchange.(Fig. 7) output port in can be that the serial ports of interface conversion chip or parallel port cache,
It can be the transmission caching of exchanger chip.
Frame inserter, such as (Fig. 6), Frame separator isolates data from the data flow for receiving to attachment structure
After frame, Frame is replicated and is moved in the transmission FIFO of destination interface by switching engine by trigger data frame inserter；Data
After frame completes first data byte, indicate that notebook data frame is ready, while to keep the 1/10 of Ethernet transmitted bit speed
Byte-rate replicates movement, and such as Ethernet transmitted bit speed is 100M bits per seconds, then replicate translational speed every more than 10MB
Second；(Fig. 6) input port in can be the serial ports of interface conversion chip or parallel port order caching, or exchanger chip
Order caching.
For one kind of above-mentioned interface conversion chip is improved, serial ports or parallel port module can be designed to without order caching, number
According to the reception annular FIFO that writes direct when receiving；
In the present embodiment, the example of a transmission data is as follows：
Equipment sends 2 command frames and a data packet frame to other 3 distinct devices by UART serial ports, and equipment first will
Data sequentially send, and receiving data write is received annular FIFO by interface conversion chip, while detecting whether to have received
Frame is sent to the ether of RMII interfaces if finding to receive complete data frame by entire data frame by receiving and dispatching control module
Net transceiver, ethernet transceiver transmit a signal to switch by cable；
Switch is received and dispatched control module and receiving data is stored to annular FIFO is received, and switchboard data frame separator is extracted
The DST in 8 bytes and CTR after frame starting, determines whether data packet frame according to CTR, if data packet frame, then passes through
CTR determines data packet frame total length, if command frame data frame length is then 8 bytes；
Afterwards, switch switching engine module finds corresponding Ethernet physical port by DST byte values, then triggers
Frame is replicated and is inserted in the transmission FIFO of corresponding ports by Frame inserter, and Frame inserter completes first character section
It is effective that Frame ready signal is put in duplication, and switch transceiver module detects this Frame and can effectively send a dataframe to
Interface conversion chip；
Switch transceiver module sends the principle of Frame, once there are the data to be passed through that Ethernet physical port sends
Frame is ready, if not actuated packet sends, log-on data bag sends immediately, after Frame is sent completely, if do not counted
It is ready according to frame, then a do-nothing instruction frame is sent, if Frame is ready, then this Frame is sent, once packet is once startup
Sending up to data packet byte number for Frame must be kept to exceed the maximum number of byte that ethernet transceiver specifies, sent out when continuous
When sending the do-nothing instruction frame and data packet byte number of amount to have been over the minimum byte number of ethernet transceiver regulation, knot
Beam data bag sends；
After interface conversion chip receives data, Frame separator identifies the Frame that destination address is this equipment, and
Among by Frame transfer replication to serial ports or parallel port transmitting-receiving caching, after completing the duplication of the first byte, serial ports or parallel port are triggered
Module sends data to equipment.
Interface conversion chip and the operation of switch internal data are completed by special hardware, so ensure that exchange process
Real-time.Do not carry out the mistake of data inside which, correction process, so partly in order to simplified system, the opposing party can be with
Improve the efficiency for exchanging.
It should be noted that the statement of all uses " first " and " second " is for differentiation two in the embodiment of the present invention
The parameter of the entity or non-equal of individual same names non-equal, it is seen that the convenience of " first " " second " only for statement, should not
The restriction to the embodiment of the present invention is interpreted as, subsequent embodiment is no longer illustrated one by one to this.
Those of ordinary skill in the art should be understood：The discussion of any of the above embodiment is exemplary only, not
It is intended to imply that the scope of the present disclosure (including claim) is limited to these examples；Under the thinking of the present invention, above example
Or can also be combined between the technical characteristic in different embodiments, step can be realized with random order, and is existed such as
Many other changes of the different aspect of the upper described present invention, for simple and clear their no offers in details.
In addition, to simplify explanation and discussing, and in order to obscure the invention, can in the accompanying drawing for being provided
To illustrate or can not illustrate that the known power ground with integrated circuit (IC) chip and other parts is connected.Furthermore, it is possible to
Device is shown in block diagram form, to avoid obscuring the invention, and this have also contemplated that following facts, i.e., with regard to this
The details of the embodiment of a little block diagram arrangements be depend highly on the platform that will implement the present invention (that is, these details should
It is completely in the range of the understanding of those skilled in the art).Elaborating detail (for example, circuit) to describe the present invention's
In the case of exemplary embodiment, it will be apparent to those skilled in the art that these details can not there is no
In the case of or implement the present invention in the case that these details are changed.Therefore, these descriptions are considered as explanation
It is property rather than restricted.
Although invention has been described to have been incorporated with specific embodiment of the invention, according to retouching above
State, many replacements of these embodiments, modification and modification will be apparent for those of ordinary skills.Example
Such as, other memory architectures (for example, dynamic ram (DRAM)) can use discussed embodiment.
Embodiments of the invention be intended to fall within the broad range of claims it is all such replace,
Modification and modification.Therefore, all any omissions within the spirit and principles in the present invention, made, modification, equivalent, improvement
Deng should be included within the scope of the present invention.
Claims (6)
1. a kind of data transmission method, including,
Equipment passes through serial ports or parallel port sends interface of the Frame with destination address to outfan for Ethernet physical port and turns
Change chip, the Ethernet physical port of the interface conversion chip is connected with switch Ethernet physical port, switch from
Too extracted valid data frame in net physical port data flow, and according to Frame destination address, Frame is forwarded to accordingly
Ethernet physical port；
After the Ethernet physical port of interface conversion chip receives Frame, effective Frame is extracted, and by this Frame
Exported to equipment by serial ports or parallel port；
Described serial ports includes synchronization or asynchronous serial port；
It is characterized in that：The Ethernet physical port of the interface conversion chip and switch only retains PHY function,
Support without MAC functions；Frame band destination address, the span of the length of the Frame are 8 bytes to 256 words
Section；When have to be passed through Frame that Ethernet physical port sends it is ready when, if not actuated packet sends, start immediately
Packet sends, and after Frame is sent completely, if not having other Frames ready, sends do-nothing instruction frame, and Frame starts
The sending until data packet byte number exceedes the maximum number of byte that specifies of ethernet transceiver of Frame is kept afterwards, when continuously transmitting
When the do-nothing instruction frame and data packet byte number of amount has been over the minimum byte number of ethernet transceiver regulation, terminate
Packet sends；Too net physical port is completely received without waiting for packet after data are received, and exchange opportunity is from data flow
Extracted valid data frame, is then forwarded according to the destination address of Frame, for interface conversion chip then can be by Frame
Exported to equipment by serial ports or parallel port.
2. a kind of data transmission device, it is characterised in that including exchanger chip, the exchanger chip includes：
Multichannel Ethernet physical port, Ethernet physical port described in per road include：Transmitting-receiving control module, receive annular FIFO,
FIFO, Frame inserter, Frame separator are sent,
One shared switching engine；
The transmitting-receiving control module is responsible for for ethernet transceiver receiving data storage to annular FIFO is received, while responsible will
In sending FIFO, data is activation is to ethernet transceiver；The reception annular FIFO is cached for receiving data；The transmission FIFO
To send data buffer storage；The Frame that the Frame inserter is responsible for sending is inserted into transmission data buffer storage FIFO；Institute
State Frame separator to be responsible for isolating Frame from the data flow for receiving；The switching engine is responsible for controlling each circuit-switched data
The exchange of frame, described Frame inserter, Frame separator are by switching engine control；
Characterized in that, introducing Frame inserter, Frame separator carries out data flow con-trol with reference to switching engine；Described
Frame separator judges data frame length to determine Frame by parsing Frame specified byte, while determining next frame
Beginning location；
After described Frame separator isolates Frame from the data flow for receiving, switching engine is by trigger data frame
Inserter, Frame is moved in the transmission FIFO of destination interface.
3. data transmission device according to claim 2, it is characterised in that the Frame separator is for from receiving
Data flow in isolate Frame, and Frame is moved in the transmission FIFO of destination interface by switching engine, mobile number
According to producing Frame ready signal after frame first character section.
4. data transmission device according to claim 2, also including interface conversion chip, the interface conversion chip bag
Include：
Serial ports or parallel port module, transmitting-receiving control module, reception annular FIFO, transmission FIFO, Frame inserter, Frame are separated
Device, controls engine；
The serial ports or parallel port module realize serial ports or parallel port function, band transmitting-receiving caching, the transmitting-receiving control module be responsible for by with
Too net transceiver receives data storage to annular data fifo is received, while being responsible for transmission data fifo being sent to Ethernet
Transceiver；The reception annular FIFO is cached for receiving data；The transmission FIFO is transmission data buffer storage；The Frame is inserted
Enter the responsible Frame that will be sent of device and be inserted into transmission data buffer storage FIFO；The Frame separator is responsible for receiving
Frame is isolated in data flow；The control engine is responsible for serial ports or parallel port module and is passed with the data of Ethernet physical port
Defeated, described Frame inserter, Frame separator, serial ports or parallel port module are by controlling engine control；
Data flow con-trol is carried out characterized in that, introducing Frame inserter, Frame separator and combining control engine；Described
Frame separator judges data frame length to determine Frame by parsing Frame specified byte, while determining next frame
Beginning location；
After described Frame separator isolates Frame from the data flow for receiving, engine is controlled by trigger data frame
Frame is moved to serial ports or parallel port module is sent in caching by inserter.
5. data transmission device as claimed in claim 4, it is characterised in that Frame separator is from the data flow for receiving
After isolating Frame, Frame is moved to switching engine serial ports or parallel port sends caching, mobile data frame first character
Frame ready signal is produced after section.
6. data transmission device as claimed in claim 4, it is characterised in that when data receiver, without serial ports or parallel port
Module is cached, and write direct reception annular FIFO.
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| CN201610985392.0A CN106571991B (en) | 2016-11-09 | 2016-11-09 | Data transmission method and device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107241382A (en) * | 2017-04-24 | 2017-10-10 | 天津瑞能电气有限公司 | For the data transfer device and its device between serial ports and Ethernet |
| CN109413485A (en) * | 2017-08-17 | 2019-03-01 | 成都鼎桥通信技术有限公司 | Data cache method and device |
| CN110213168A (en) * | 2018-02-28 | 2019-09-06 | 中航光电科技股份有限公司 | A kind of FC turns the data conversion flow control methods and device of Ethernet |
| CN113225376A (en) * | 2021-03-29 | 2021-08-06 | 桂林电子科技大学 | Ethernet frame and SDN data frame adapting method based on FPGA |
| CN113840188A (en) * | 2021-09-29 | 2021-12-24 | 中国电子科技集团公司第三十四研究所 | Device and method for transmitting Ethernet data by DCC overhead |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170430A (en) * | 2011-03-24 | 2011-08-31 | 华中科技大学 | Multi-port multi-network protocol converter |
| CN102347879A (en) * | 2011-05-23 | 2012-02-08 | 大连理工计算机控制工程有限公司 | D-BUS high-speed bus technology based on ring type Ethernet and auxiliary network |
| CN103728957A (en) * | 2014-01-15 | 2014-04-16 | 浙江大学 | HART (highway addressable remote transducer) field equipment management method and system based on real-time database |
-
2016
- 2016-11-09 CN CN201610985392.0A patent/CN106571991B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170430A (en) * | 2011-03-24 | 2011-08-31 | 华中科技大学 | Multi-port multi-network protocol converter |
| CN102347879A (en) * | 2011-05-23 | 2012-02-08 | 大连理工计算机控制工程有限公司 | D-BUS high-speed bus technology based on ring type Ethernet and auxiliary network |
| CN103728957A (en) * | 2014-01-15 | 2014-04-16 | 浙江大学 | HART (highway addressable remote transducer) field equipment management method and system based on real-time database |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107241382A (en) * | 2017-04-24 | 2017-10-10 | 天津瑞能电气有限公司 | For the data transfer device and its device between serial ports and Ethernet |
| CN107241382B (en) * | 2017-04-24 | 2023-10-03 | 天津瑞能电气有限公司 | Data conversion method and device used between serial port and Ethernet |
| CN109413485A (en) * | 2017-08-17 | 2019-03-01 | 成都鼎桥通信技术有限公司 | Data cache method and device |
| CN110213168A (en) * | 2018-02-28 | 2019-09-06 | 中航光电科技股份有限公司 | A kind of FC turns the data conversion flow control methods and device of Ethernet |
| CN113225376A (en) * | 2021-03-29 | 2021-08-06 | 桂林电子科技大学 | Ethernet frame and SDN data frame adapting method based on FPGA |
| CN113840188A (en) * | 2021-09-29 | 2021-12-24 | 中国电子科技集团公司第三十四研究所 | Device and method for transmitting Ethernet data by DCC overhead |
| CN113840188B (en) * | 2021-09-29 | 2023-05-12 | 中国电子科技集团公司第三十四研究所 | Device and method for transmitting Ethernet data by using DCC overhead |
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