CN102739555A - Data transmission method and data interface card - Google Patents
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Abstract
The application discloses a data interface card which comprises a field programmable gate array (FPGA), a special integrated circuit, a first random storage module and a second random storage module, wherein the FPGA is used for receiving data of a first format from an upper interface, carrying out deserialization and de-encapsulation on the data of the first format, extracting effective data and the port number of a lower interface, and generating storage state information corresponding to effect data; the effect data is stored to the first random storage module; the storage state information corresponding to the effective data and the port number of the lower interface are stored into the second random storage module; corresponding effective data is read from the first random storage module according to the storage state information of the effective data read from the second random storage module, and the effective data is recovered into a data pocket; and the data pocket is transmitted to the special integrated circuit according to the port number of the lower interface read from the second random storage module. The application also discloses a data transmission method.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a data transmission method and a data interface card.
Background
In practical application in the field of data storage technology, the situation that the types of the uplink interface and the downlink interface are different can be encountered, and the maximum difference between the uplink interface and the downlink interface is mainly represented by the difference between the data format and the data rate. In order to realize data transmission between different interfaces, a Field Programmable Gate Array (FPGA) is generally used to realize data format conversion, and a Random Access Memory (RAM) outside the FPGA is used for buffering to realize matching of different rates.
The following explains how to implement matching of different data rates through RAM storage in the prior art by taking the example that the upper connection interface is a gigabit ethernet interface and the lower connection interface is a packet Over Synchronous Digital Hierarchy (POS) interface.
Fig. 1 is a block diagram of a prior art data interface card, which mainly comprises an FPGA101, an application specific integrated circuit 107 and a random access memory module 108 (which includes 4 pieces of RAM). Wherein, FPGA101 includes:
an Ethernet MAC Core module (Ethernet MAC Core) 102, configured to complete conversion from serial Ethernet data to parallel data, extract an effective Ethernet packet, and send the Ethernet packet to the first user logic module.
A first User Logic module (User Logic (1)) 103, configured to complete decapsulation of the ethernet packet, extract information required by an Application Specific Integrated Circuit (ASIC) 107, and finally encapsulate the information into a fixed format, and store the information in a random access memory module 108 through a RAM controller 104.
The information required by the asic 107 includes, among others, a Port number (Port _ number) and data (data).
A RAM Controller (RAM Controller) 104 for performing control management on the random access memory module 108.
A second User Logic module (User Logic (2)) 105 for reading data from the random access memory module 108, converting the read data into an interface format used by the downstream interface 106, and transmitting the converted data to the downstream interface 106.
A downstream Interface (DOWN Stream Interface) 106 for sending data from the second user logic module 105 to the asic 107 in a standard Interface form, which includes but is not limited to, for example, a fourth layer second stage System Packet Interface (SPI-4.2, System Packet Interface Level4, Phase 2), a first layer IP Packet (POS Level I) provided by Synchronous Digital Hierarchy, a second layer IP Packet (POS Level II, page Over Synchronous Digital Hierarchy 2) provided by Synchronous Digital Hierarchy, and the like.
And the application specific integrated circuit 107 is used for realizing the conversion of the standard interface to the downstream serial physical interface. A serial physical port such as an optical interface.
Based on the above system structure, the data format in the random access memory module 108 is shown in fig. 2. The random access memory module 108 includes N parallel ports with the same structure. For each port, two parts of a Buffer Descriptor Table (BDT) and a data storage area need to be divided in the RAM space, wherein the Buffer Descriptor Table is used for storing a circular linked list, and the data storage area is used for storing data. Taking port 0 as an example, the buffer descriptor table includes M nodes, where the ith node includes (1 ≦ i < M, 1 ≦ j):
a data buffer pointer i pointing to the first address of the data block corresponding to the node in the RAM;
the effective data byte length j is used for indicating the effective data byte length of the data block corresponding to the node;
and the next node pointer is used for pointing to the first address of the (i + 1) th node in the RAM.
The mth node includes:
a data buffer pointer M pointing to the first address of the data block corresponding to the node in the RAM;
the effective data byte length j is used for indicating the effective data byte length of the data block corresponding to the node;
and the next node pointer is used for pointing to the first address of the 1 st node in the RAM.
It should be noted that the effective data byte lengths of the data blocks corresponding to different nodes are not necessarily the same.
Based on the above storage mode, the FPGA needs to maintain a buffer descriptor table, and the processing process of the FPGA in the storage process is described below by taking a node i (i is greater than or equal to 1 and less than M) as an example:
(1) firstly, according to the data buffer pointer i-1 of the (i-1) th node and the effective data byte length of the data block corresponding to the i-1 th node, the data buffer pointer i of the corresponding node is calculated.
(2) Next, based on the data sent from the first user logic module 103, the effective data byte length of the data block corresponding to the i-th node is calculated.
(3) And finally, calculating the pointer of the (i + 1) th node according to the pointer of the ith node and the effective data byte length of the data block corresponding to the ith node.
The process of reading from the RAM requires the reverse of the process of storing, and is not described here.
The RAM data storage mode in the existing data interface card has the following disadvantages:
1. the capacity of the RAM is not fully utilized, and a part of RAM space is required to be occupied for storing the buffer descriptor table when data are stored;
2. the bandwidth of data storage is reduced, and partial bandwidth is required to be occupied to access the RAM space corresponding to the buffer descriptor table during data storage;
3. the code implementation of the FPGA is relatively complex, because the FPGA needs to maintain the buffer descriptor table when storing data, and when reading data, a pointer of the data buffer needs to be acquired first, and then data is extracted according to the total data length.
Due to the above disadvantages, the storage capacity of the RAM is reduced and the access speed is reduced, which affects the maximum data bandwidth of the downstream port.
Disclosure of Invention
The application provides a data transmission method and a data interface card, which can effectively improve the storage capacity and the access speed of an RAM in the data interface card and improve the maximum data bandwidth of a downlink port.
The data interface card provided by the embodiment of the invention comprises a Field Programmable Gate Array (FPGA), a special integrated circuit and a first random storage module, and the data interface card also comprises a second random storage module;
the FPGA is used for receiving first format data from an uplink interface, performing serial-parallel conversion on the first format data, and then decapsulating to extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format; packaging the effective data, the storage state information corresponding to the effective data and the port number of the downlink interface into a fixed format and caching the fixed format, storing the effective data into a first random storage module, and storing the storage state information corresponding to the effective data and the port number of the downlink interface into a second random storage module; the storage state information corresponding to the effective data comprises a data packet starting position, a data packet ending position and an effective data byte length; reading storage state information of effective data from the second random storage module, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module according to the byte length of the effective data and recovering the effective data into the data packet, and sending the data packet to the application-specific integrated circuit according to the port number of the downlink interface read from the second random storage module;
the application specific integrated circuit is used for converting the received data packet into second format data and sending the second format data to the downlink interface.
Preferably, the first random access memory module comprises 4 Random Access Memories (RAMs) and has a total bit width of 64 bits, and the second random access memory module comprises 1 RAM and has a total bit width of 8 bits.
Preferably, the first format data is ethernet data, and the second format data is optical network data.
Preferably, the FPGA comprises: the system comprises an Ethernet MAC core module, a first user logic module, an RAM controller, a second user logic module and a downstream interface;
the Ethernet MAC core module is used for receiving serial Ethernet data from an uplink interface, converting the serial Ethernet data into parallel data and extracting an effective Ethernet message;
the first user logic module is used for decapsulating the effective Ethernet message output by the Ethernet MAC core module, extracting effective data and port numbers of a downlink interface, generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format, encapsulating the effective data, the storage state information corresponding to the effective data and the port numbers of the downlink interface into a fixed format and caching the fixed format, storing the effective data in the cache into the first random storage module through the RAM controller, and storing the storage state information corresponding to the effective data in the cache and the port numbers of the downlink interface into the second random storage module;
the RAM controller is used for carrying out access control management on the first random access memory module and the second random access memory module;
the second user logic module is used for reading storage state information corresponding to the effective data from the second random storage module through the RAM controller, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module through the RAM controller according to the byte length of the effective data, converting the effective data into an interface form used by a downstream interface and sending the interface form to the downstream interface corresponding to the port number of the downstream interface read from the second random storage module;
and a downstream interface for transmitting data from the second user logic module to the ASIC in a standard interface format.
Preferably, the standard interface is a fourth layer second stage system packet interface SPI-4.2, an IP packet provided by the synchronous digital hierarchy at the first layer, or an IP packet provided by the synchronous digital hierarchy at the second layer.
Preferably, the total bit width of the first random access memory module and the second random access memory module is less than or equal to the maximum bit width supported by the RAM controller.
The embodiment of the invention also provides a data transmission method, wherein the data transmission is realized by the data interface card, and the method comprises the following steps:
A. receiving first format data from an uplink interface, performing serial-parallel conversion on the first format data, and decapsulating to extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format, packaging the effective data, the storage state information corresponding to the effective data and a port number of a downlink interface into a fixed format, and caching; the storage state information corresponding to the effective data comprises a data packet starting position, a data packet ending position and an effective data byte length;
B. the effective data in the cache is packaged and stored in a first random storage module, and the storage state information corresponding to the effective data in the cache and the port number of the downlink interface are stored in a second random storage module;
C. reading storage state information corresponding to effective data from a second random storage module, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module according to the byte length of the effective data and recovering the effective data into the data packet, and sending the data packet to an application-specific integrated circuit according to the port number of a downlink interface read from the second random storage module;
D. the application specific integrated circuit is used for converting the received data packet into second format data and sending the second format data to the downlink interface.
Preferably, the bit width of the valid data is 64 bits, and the bit width of the storage status information corresponding to the valid data is 8 bits.
Preferably, the first format data is ethernet data, and the second format data is optical network data.
Preferably, in the step a, according to the length of the valid data and the set cache format, generating and caching storage state information corresponding to the valid data, and encapsulating the valid data, the storage state information corresponding to the valid data, and the port number of the downlink interface as a fixed format is specifically implemented by:
calculating the length of a data packet which can be stored in each unit bit width of the first random memory module according to the length of the effective data and the bit width of the first random memory module, thereby calculating the data packet starting position, the data packet ending position and the effective data byte length in the storage state information corresponding to the effective data in each unit bit width of the second random memory module; and sequentially packaging the calculated initial position and the end position of the data packet according to the sum of unit bit widths of the first random storage module and the second random storage module, wherein the effective data byte length, the port number of the downlink interface and the effective data part corresponding to the effective data byte length are in a fixed format and are cached until all effective data are cached.
According to the technical scheme, the effective data and the corresponding storage state information are respectively stored by different random access memories, the storage state information corresponding to the data and the data are simultaneously obtained only by meeting the first-in first-out principle of the complete message, and the read-write bandwidth of the RAM is fully utilized, so that the invention can better meet the field with higher interface rate. Under the conditions of the same message size and the same message quantity, the total data quantity stored in the RAM is less than that of the prior technical scheme, wherein the part with reduced data quantity is a buffer descriptor table. Therefore, the RAM space for storing effective data is enlarged, and the application scene of large data volume cache can be better met; and the code of the FPGA is realized simply, and a buffer descriptor table does not need to be maintained, so that the design difficulty of the FPGA is reduced, and the development period of a product is shortened.
Drawings
FIG. 1 is a block diagram of a prior art data interface card;
FIG. 2 is a diagram illustrating a data format in the RAM 108 shown in FIG. 1;
FIG. 3 is a block diagram of a data interface card according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a data interface card according to an embodiment of the present invention to perform data transmission;
FIG. 5 is a schematic diagram of the fixed format of the cache information in the first user logic module 303 shown in FIG. 3;
FIG. 6 is a diagram illustrating the data format in the first random access module 308 and the second random access module 309 shown in FIG. 3;
fig. 7 is a diagram illustrating a data format of 66 bytes of data buffered in the first user logic module 303, which is sent to the port 1 in a specific application example.
Detailed Description
The core idea of the invention is that: the effective data and the data storage state information are stored by using different RAMs respectively, and the process of serially acquiring the storage state information and the data in the prior art is changed into the process of synchronously acquiring the storage state information and the data of the data in parallel, so that the storage bandwidth of the data is improved.
The data transmission method provided by the application comprises the following steps:
A. receiving first format data from an uplink interface, performing serial-parallel conversion on the first format data, and decapsulating to extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format, packaging the effective data, the storage state information corresponding to the effective data and a port number of a downlink interface into a fixed format, and caching; the storage state information corresponding to the effective data comprises a data packet starting position, a data packet ending position and an effective data byte length;
B. the effective data in the cache is packaged and stored in a first random storage module, and the storage state information corresponding to the effective data in the cache and the port number of the downlink interface are stored in a second random storage module;
C. reading storage state information corresponding to effective data from a second random storage module, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module according to the byte length of the effective data and recovering the effective data into the data packet, and sending the data packet to an application-specific integrated circuit according to the port number of a downlink interface read from the second random storage module;
D. the application specific integrated circuit is used for converting the received data packet into second format data and sending the second format data to the downlink interface.
In the step a, according to the length of the valid data and the set cache format, generating storage state information corresponding to the valid data, and encapsulating the valid data, the storage state information corresponding to the valid data, and the port number of the downlink interface as a fixed format is specifically implemented by:
calculating the length of a data packet which can be stored in each unit bit width of the first random memory module according to the length of the effective data and the bit width of the first random memory module, thereby calculating the data packet starting position, the data packet ending position and the effective data byte length in the storage state information corresponding to the effective data in each unit bit width of the second random memory module; and sequentially packaging the calculated initial position and the end position of the data packet according to the sum of unit bit widths of the first random storage module and the second random storage module, wherein the effective data byte length, the port number of the downlink interface and the effective data part corresponding to the effective data byte length are in a fixed format and are cached until all effective data are cached.
In order to make the technical principle, characteristics and technical effects of the technical scheme of the present application clearer, the technical scheme of the present application is explained in detail with reference to specific embodiments below.
As shown in fig. 3, the data interface card according to the embodiment of the present invention mainly includes an FPGA301, an asic 307, a first random access memory module 307 (including 4 pieces of RAM), and a second random access memory module 309 (including one piece of RAM). Wherein, FPGA301 includes:
an Ethernet MAC Core module (Ethernet MAC Core) 302, configured to complete conversion of Ethernet data from the uplink interface to an internal user interface of the FPGA, that is, complete conversion of serial Ethernet data to parallel data, extract an effective Ethernet packet, and send the Ethernet packet to the first user logic module.
A first User Logic module (User Logic (1)) 303, configured to decapsulate the effective ethernet packet output by the ethernet MAC core module 302, and extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format; the effective data, the storage state information corresponding to the effective data, and the port number of the downlink interface are packaged in a fixed format and cached, the effective data is stored in the first random access memory module 308 through the RAM controller 304, and the storage state information of the effective data and the port number of the downlink interface are stored in the second random access memory module 309. The storage state information of the valid data includes a packet start position, a packet end position, a valid data byte length, and a port number of a downlink interface in the unit bit width storage area of the second random access memory module 309.
A RAM Controller (RAM Controller) 304 for performing access control management on the first random access memory module 308 and the second random access memory module 309.
A second User Logic module (User Logic (2)) 305, configured to read storage status information of valid data from the second random access module 309 through the RAM controller 304, determine the start and end of a data packet according to the read start position and end position of the data packet, read corresponding valid data from the first random access module 308 according to the valid data byte length, convert the valid data into an interface format used by the downstream interface 306 according to the port number of the downstream interface read from the second random access module 309, and send the converted valid data to the downstream interface 306.
A downstream Interface (DOWN Stream Interface) 306 for transmitting data from the second user logic module 305 to the asic 307 in a standard Interface format, including but not limited to SPI 4.2, POS level I, POS level II, etc.
The flow of data transmission by the data interface card provided by the embodiment of the invention is shown in fig. 4, and comprises the following steps:
step 401: the data content and format cached in the first user logic module 303 is confirmed. In addition to the most basic information such as Port number (Port _ number), Valid byte length (Valid _ byte _ length), and Valid data (data), the stored data needs to be added with two additional bits — Start of packet position (SOP), End of packet position (EOP), etc. The SOP and EOP function is to identify the beginning and end of a packet.
Step 402: and the FPGA completes the generation of information related to the data storage state. The first user logic module 303 extracts valid data and a port number of a downlink interface from a data packet sent from the uplink interface, and generates storage state information SOP, EOP and a valid data byte length corresponding to the valid data according to the length of the valid data and a set cache format; and then packaged and buffered according to the buffering format shown in fig. 5. The format of the data cached in the first user logic module 303 in the data interface card according to the embodiment of the present invention is shown in fig. 5. The original RAMs 1 to 4 store valid data (64 bits), and the newly added RAM5 (8 bits) stores state information corresponding to the valid data, that is, SOP (1 bit), EOP (1 bit), port number (3 bit), and valid data byte length (3 bit). The values of the storage status information are the packet start position, the packet end position, the effective data byte length, and the port number of the downstream interface in the unit bit width storage area in the second random access memory module 309 corresponding to the effective data.
Step 403: the RAM controller 304 stores contents SOP, EOP, Port _ number, Valid _ byte _ length, which are related to the storage state information of the packet, in the second random access module 309 (see the RAM5 in fig. 6); valid data is stored in the first random access module 308 (see RAM 1-RAM 4 in fig. 6). Referring to fig. 6, valid data cached in the first user logic module 303 illustrated in fig. 5 is stored in the RAM1 to the RAM4, and the storage status information portion cached in fig. 5 is stored in the RAM5, respectively.
Step 404: the RAM controller 304 reads data from the first random access memory block 308 and the second random access memory block 309, recovers complete data packets according to SOP and EOP, sends the complete data packets to the second user logic block 305, and finally sends the data packets to the asic 307 through the downstream interface 306.
The invention is illustrated below by means of a specific application example. The existing data interface card is modified, a 5 th RAM is added on the basis of 4 RAMs of the existing data interface card, and the added 5 th RAM is used for storing the storage state information of effective data. The bit width associated with the storage status information of the data packet is calculated, and the bit width of the added 5 th RAM, that is, the format of the cache data set in the first custom logic module 304, is determined. Wherein,
port number: port _ number, X bit. X is determined according to the specific port number, and if the port number is N, the value of X is required to be the minimum natural number which is greater than or equal to log 2N. In this application example, if the port number is 8, X = 3.
Effective data byte length: valid _ byte _ length, Ybit. Y is determined according to the bit width of the RAM used for storing data, and if the bit width of the RAM used for storing data is M, Y is required to be a minimum natural number which is greater than or equal to log2 (M/8). In this application example, the bit width M is 64 (i.e. 8 bytes), then Y =3, i.e. 3 bits indicate that several bytes of the 8 bytes of the data portion are valid, for example 000 means 1 byte valid, 001 means 2 bytes valid, and so on, 111 means 8 bytes valid.
Data packet start position: SOP, 1 bit;
packet end position: EOP, 1 bit.
Assuming that the downstream port is an 8-port, the bit width of the 4-chip RAM used for storing valid data is 64 bits, and in this case, the bit width of the data packet storage status information: 3+3+2=8 bit. That is, in this case, only one RAM with 8bit width needs to be added to complete the storage of the storage state information of the data packet. Similarly, if the storage status information is more, a relatively large RAM needs to be added to store the storage status information.
And the FPGA completes the generation of information related to the data storage state. The FPGA extracts data and Port _ number from the data packet sent from the uplink interface and generates SOP, EOP and Valid _ byte _ length.
Fig. 7 shows an example of 66 bytes of data sent to channel port 1, to illustrate the data format actually buffered in the first user logic module 303. SOP =1 in fig. 7, indicating the start of this message; EOP =1 indicates the end of the message, SOP ═ EOP ═ 0 indicates the middle part of the message; port _ number =001 indicates that this packet is sent to channel Port 1; valid _ byte _ length =001 indicates that only 2 bytes of the data portion are Valid, and Valid _ byte _ length =111 indicates that the Valid data portion 8 bytes are all Valid.
The RAM controller 304 writes the above data into the random access memory. Specifically, the RAM controller 304 extracts the contents SOP, EOP, Port _ number, Valid _ byte _ length, and Valid data associated with the packet storage status information from the buffer of the first logic module 303. Then the RAM controller 304 stores the contents related to the packet storage status information in the newly added 5 th RAM; and storing valid data in the original 4 pieces of RAM. The advantage over the prior art is that the data buffer pointers and next node pointers in the buffer descriptor table are no longer calculated.
Next, the RAM controller 304 reads out data from the random access memory. Specifically, the contents in the 5 th RAM are directly read, and the contents comprise storage state information stored in the 5 th RAM and data stored in the 1 st to 4 th RAMs. The FPGA identifies the start and the end of a data packet according to the SOP read from the 5 th RAM and the EOP; restoring effective data from the data read from the 1 st to 4 th RAM according to the Valid _ byte _ length; the second user logic module 305 will put the recovered valid data onto the downstream interface 306 according to the Port _ number read from the 5 th piece of RAM and send the data to the asic 307.
The data transmission scheme provided by the application has the following beneficial effects:
1) the data access is very convenient, the data state and the data are simultaneously obtained only by meeting the first-in first-out principle of the complete message, and the read-write bandwidth of the RAM is fully utilized, so that the method can better meet the field of high interface rate.
2) Under the conditions of the same message size and the same message quantity, the total data quantity stored in the memory is less than that of the prior technical scheme, wherein the part with reduced data quantity is a buffer descriptor table. Therefore, the RAM space for storing effective data is enlarged, and the application scene of large data amount cache can be better met.
3) The code of the FPGA is simple to realize, a buffer descriptor table does not need to be maintained, the design difficulty of the FPGA is reduced, and the development period of a product is shortened.
The above description is only a preferred embodiment of the present application and should not be taken as limiting the scope of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the technical solution of the present application should be included in the scope of the present application.
Claims (10)
1. A data interface card comprises a field programmable gate array FPGA, an application specific integrated circuit and a first random storage module, and is characterized by also comprising a second random storage module;
the FPGA is used for receiving first format data from an uplink interface, performing serial-parallel conversion on the first format data, and then decapsulating to extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format; packaging the effective data, the storage state information corresponding to the effective data and the port number of the downlink interface into a fixed format and caching the fixed format, storing the effective data into a first random storage module, and storing the storage state information corresponding to the effective data and the port number of the downlink interface into a second random storage module; the storage state information corresponding to the effective data comprises a data packet starting position, a data packet ending position and an effective data byte length; reading storage state information of effective data from the second random storage module, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module according to the byte length of the effective data and recovering the effective data into the data packet, and sending the data packet to the application-specific integrated circuit according to the port number of the downlink interface read from the second random storage module;
the application specific integrated circuit is used for converting the received data packet into second format data and sending the second format data to the downlink interface.
2. A data interface card according to claim 1, wherein said first random access memory module comprises 4 pieces of RAM having a total bit width of 64 bits, and said second random access memory module comprises 1 piece of RAM having a total bit width of 8 bits.
3. A data interface card in accordance with claim 1, wherein said first format data is ethernet data and said second format data is optical network data.
4. A data interface card in accordance with claim 3, wherein said FPGA comprises: the system comprises an Ethernet MAC core module, a first user logic module, an RAM controller, a second user logic module and a downstream interface;
the Ethernet MAC core module is used for receiving serial Ethernet data from an uplink interface, converting the serial Ethernet data into parallel data and extracting an effective Ethernet message;
the first user logic module is used for decapsulating the effective Ethernet message output by the Ethernet MAC core module, extracting effective data and port numbers of a downlink interface, generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format, encapsulating the effective data, the storage state information corresponding to the effective data and the port numbers of the downlink interface into a fixed format and caching the fixed format, storing the effective data in the cache into the first random storage module through the RAM controller, and storing the storage state information corresponding to the effective data in the cache and the port numbers of the downlink interface into the second random storage module;
the RAM controller is used for carrying out access control management on the first random access memory module and the second random access memory module;
the second user logic module is used for reading storage state information corresponding to the effective data from the second random storage module through the RAM controller, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module through the RAM controller according to the byte length of the effective data, converting the effective data into an interface form used by a downstream interface and sending the interface form to the downstream interface corresponding to the port number of the downstream interface read from the second random storage module;
and a downstream interface for transmitting data from the second user logic module to the ASIC in a standard interface format.
5. A data interface card according to claim 4, wherein said standard interface is layer four, stage two system packet interface SPI-4.2, IP packets provided by the synchronous digital hierarchy at layer one or IP packets provided by the synchronous digital hierarchy at layer two.
6. The data interface card of claim 4, wherein the total bit width of said first and second random access memory modules is less than or equal to the maximum bit width supported by the RAM controller.
7. A data transmission method implemented by a data interface card according to claim 1, comprising the steps of:
A. receiving first format data from an uplink interface, performing serial-parallel conversion on the first format data, and decapsulating to extract effective data and a port number of a downlink interface; generating storage state information corresponding to the effective data according to the length of the effective data and a set cache format, packaging the effective data, the storage state information corresponding to the effective data and a port number of a downlink interface into a fixed format, and caching; the storage state information corresponding to the effective data comprises a data packet starting position, a data packet ending position and an effective data byte length;
B. the effective data in the cache is packaged and stored in a first random storage module, and the storage state information corresponding to the effective data in the cache and the port number of the downlink interface are stored in a second random storage module;
C. reading storage state information corresponding to effective data from a second random storage module, determining the start and the end of a data packet according to the read start position and the end position of the data packet, reading corresponding effective data from the first random storage module according to the byte length of the effective data and recovering the effective data into the data packet, and sending the data packet to an application-specific integrated circuit according to the port number of a downlink interface read from the second random storage module;
D. the application specific integrated circuit is used for converting the received data packet into second format data and sending the second format data to the downlink interface.
8. The method according to claim 7, wherein the bit width of the valid data is 64 bits, and the bit width of the storage status information corresponding to the valid data is 8 bits.
9. The method of claim 7, wherein the first format data is Ethernet data and the second format data is optical network data.
10. The method according to claim 7, wherein in the step a, according to a length of the valid data and a set cache format, a specific implementation method for generating storage status information corresponding to the valid data, and encapsulating the valid data, the storage status information corresponding to the valid data, and a port number of the downlink interface into a fixed format is as follows:
calculating the length of a data packet which can be stored in each unit bit width of the first random memory module according to the length of the effective data and the bit width of the first random memory module, thereby calculating the data packet starting position, the data packet ending position and the effective data byte length in the storage state information corresponding to the effective data in each unit bit width of the second random memory module; and sequentially packaging the calculated initial position and the end position of the data packet according to the sum of unit bit widths of the first random storage module and the second random storage module, wherein the effective data byte length, the port number of the downlink interface and the effective data part corresponding to the effective data byte length are in a fixed format and are cached until all effective data are cached.
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