CN102736006B - Test structure and test method for negative bias temperature instability of semiconductor device - Google Patents

Test structure and test method for negative bias temperature instability of semiconductor device Download PDF

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CN102736006B
CN102736006B CN201110084197.8A CN201110084197A CN102736006B CN 102736006 B CN102736006 B CN 102736006B CN 201110084197 A CN201110084197 A CN 201110084197A CN 102736006 B CN102736006 B CN 102736006B
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negative bias
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CN102736006A (en
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冯军宏
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Abstract

The invention discloses a test structure for negative bias temperature instability (NBTI) of a semiconductor device. The test structure includes a bias voltage output device. When grid voltages of a semiconductor device are turned from stress negative bias voltages to test voltages or from test voltages to stress negative bias voltages, the bias voltage output device outputs maintaining voltages that are less than zero to grid electrodes; therefore, during the whole NBTI test process, all grid electrodes can be connected to negative bias voltages, so that an occurrence of a recovery effect can be avoided and thus accuracy of an NBTI test result can be improved. Meanwhile, the invention also discloses a test method for negative bias temperature instability of semiconductor device. According to the method, when voltages of grid electrodes are turned from stress negative bias voltages to test voltages or from test voltages to stress negative bias voltages, maintaining voltages that are less than zero are outputted to the grid electrodes; therefore, during the whole NBTI test process, all grid electrodes can be connected to negative bias voltages, so that an occurrence of a recovery effect can be avoided and thus accuracy of an NBTI test result can be improved.

Description

The test structure of semiconductor devices negative bias thermal instability and method of testing
Technical field
The present invention relates to semiconductor test technical field, relate in particular to a kind of test structure and method of testing of semiconductor devices negative bias thermal instability.
Background technology
Along with dwindling of microelectronic component physical dimension, properties of integrated circuit is more responsive to microscopic defect, and various technologies more and more approach its basic reliability limit, and integrity problem is more and more outstanding.Wherein, negative bias thermal instability (NBTI, Negative Bias TemperatureInstability) is the key factor that affects MOS device reliability.The PMOS being caused by NBTI effect degenerates becomes the principal element that affects device lifetime gradually, and it degenerates even more serious than the NMOS life-span of being caused by hot carrier's effect.
NBTI effect is that (conventionally > 100 ℃) applies certain minus gate voltage biasing to PMOS grid and cause due at high temperature, and this situation all may run in device aging and the course of work.The impact that NBTI effect causes shows as drain saturation current and mutual conductance constantly reduces, and threshold voltage shift constantly increases, and sub-threshold slope constantly reduces.The variation of these parameters may increase the signal delay in sequential circuit, thereby causes timing drift.In Analogous Integrated Electronic Circuits, particularly in the application of some parameter matching, circuit working condition can apply asymmetrical bias stress to the transistor of coupling, thereby causes obvious parameter mismatch, and this will cause degenerating of device performance under the reduction of yield rate in ageing process and condition of work.Have mechanism prediction, when the gate oxide thickness of MOS device is less than after some, NBTI effect will surpass the impact of other various factors, become the major effect mechanism of device lifetime.
Therefore,, in order to assess exactly product and check product, in current reliability testing, generally all comprise NBTI test.
Please refer to Fig. 1 to Fig. 2, wherein, Fig. 1 is traditional NBTI test structure schematic diagram, and Fig. 2 is the added voltage schematic diagram of device grids in traditional NBTI test process.As shown in Figures 1 and 2, first traditional NBTI test adds stress negative bias Vstress at the grid g of MOS device, and now, grid g scoops out power negative bias Vstress, tagma b ground connection GND, i.e. grid voltage Vg=Vstress, bulk voltage Vb=GND; Then remove described stress negative bias Vstress, and add test voltage and carry out device electric parameter detecting, now, grid g and drain electrode d all meet test voltage Vmeasure, the equal ground connection GND of tagma b and source electrode s, i.e. Vg=Vd=Vstress, Vb=Vs=GND, wherein, Vd is drain voltage, and Vs is source voltage; And after removing described stress negative bias to before adding test voltage Vmeasure, bias voltage on described grid g is zero, be ground connection GND, conventionally this period of time of above-mentioned grounded-grid GND be called to stand-by period Twait, this is to be determined by the ardware feature of tester table.
Yet, because NBTI effect exists serious recovery (Recovery) effect, be that the electrical parameter decline that NBTI effect causes can recover 80% at most after removing current field condition, even in 1 second after current field condition removes, just can recover 50%, and above-mentioned traditional NBTI method of testing is removing stress negative bias to adding in this section of process of test voltage, grid g is ground connection GND, thereby cause traditional NB TI test to have serious recovery Effects, make the follow-up device electric parameter detecting carrying out can not reflect exactly the impact that the NBTI effect of device causes.
In order to address this problem, the measure of taking at present has:
(1) by adjusting tool parameters, shorten stand-by period Twait as far as possible, yet because stand-by period Twait is determined by board hardware, so shortening amount is limited;
(2) adopt instantaneous method of testing (On-the-fly method), in the method, the added voltage schematic diagram of device grids as shown in Figure 3, in the test process of NBTI, the voltage of device grids g is directly down to test voltage Vmeasure by stress negative bias Vstress, and without the process of ground connection GND, therefore, can avoid producing recovery Effects in NBTI test process.Yet described instantaneous method of testing is being carried out silicon chip level reliability (WLR, while WaferLevel Reliability) testing, need special source measuring unit (SMU, Power SourceMeasure Unit), described source measuring unit can not be used on traditional tester table; And for package level reliability (PLR, Package Level Reliability) test, due to the restriction of concurrent testing, this instantaneous method of testing is difficult to be applied.
Therefore, be necessary existing NBTI test to improve.
Summary of the invention
The object of the present invention is to provide a kind of test structure and method of testing of semiconductor devices negative bias thermal instability, to improve the accuracy of NBTI test result.
For addressing the above problem, the present invention proposes a kind of test structure of semiconductor devices negative bias thermal instability, wherein, described semiconductor devices comprises grid, source electrode, drain electrode and body electrode, described grid is connected with a bias voltage output unit, while adding stress negative bias or test voltage on described grid, described bias voltage output unit does not affect the voltage on described grid; Voltage on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, described bias voltage output unit maintains voltage to described grid output one, and described in maintain voltage value be less than zero.
Optionally, described bias voltage output unit comprises the first resistance, diode and second resistance of series connection successively; One termination one first bias voltage of described the first resistance, diode described in its another termination; Grid described in the termination that described the second resistance is connected with described diode, stress negative bias or test voltage described in its another termination; During the voltage of the described second resistance other end is by stress negative bias slew test voltage or by test voltage, turned to stress negative bias during, described diode is opened, in other situation, described diode disconnects.
Optionally, the computing formula that maintains voltage described in is:
V H = R 2 R 1 + R 2 V 1
Wherein, V hfor maintaining voltage, R 1be the resistance of the first resistance, R 2be the resistance of the second resistance, V 1it is the first bias voltage.
Optionally, R 2> R 1.
Optionally, R 2> 5R 1.
Optionally, the absolute value of described the first bias voltage is less than the absolute value of described test voltage, the absolute value of described test voltage is less than the absolute value of described stress negative bias, and when the absolute value of described grid voltage is less than the absolute value of described the first bias voltage, described diode is opened.
Optionally, when described grid scoops out power negative bias, described body electrode grounding; When described grid connects test voltage, described drain electrode connects test voltage, and described source electrode and described body electrode grounding.
Meanwhile, for addressing the above problem, the present invention also proposes a kind of method of testing of semiconductor devices negative bias thermal instability, and the method utilizes the test structure of above-mentioned semiconductor devices negative bias thermal instability to test, and comprises the steps:
(1) grid of described semiconductor devices is scooped out to power negative bias, make described grid under negative bias effect of stress;
(2) remove described stress negative bias, toward described grid, add and maintain voltage;
(3) maintain voltage described in removing, described grid is connect to test voltage, described semiconductor devices is carried out to electric performance test.
Compared with prior art, the test structure of semiconductor devices negative bias thermal instability provided by the invention, by increasing by a bias voltage output unit, the voltage of described bias voltage output unit on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improved the accuracy of NBTI test result.
Compared with prior art, the method of testing of semiconductor devices negative bias thermal instability provided by the invention, by the voltage on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improve the accuracy of NBTI test result.
Accompanying drawing explanation
Fig. 1 is traditional NBTI test structure schematic diagram;
Fig. 2 is the added voltage schematic diagram of device grids in traditional NBTI test process;
Fig. 3 is that the instantaneous method of testing of existing employing is carried out the added voltage schematic diagram of device grids in NBTI test process;
The NBTI test structure schematic diagram that Fig. 4 provides for the embodiment of the present invention;
The added voltage schematic diagram of device grids in the NBTI method of testing that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Test structure and the method for testing of semiconductor devices negative bias thermal instability the present invention being proposed below in conjunction with the drawings and specific embodiments are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only for convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of test structure of semiconductor devices negative bias thermal instability is provided, this structure comprises a bias voltage output unit, the voltage of described bias voltage output unit on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improved the accuracy of NBTI test result, simultaneously, the present invention also provides a kind of method of testing of semiconductor devices negative bias thermal instability, the method by the voltage on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improve the accuracy of NBTI test result.
Please refer to Fig. 4 and Fig. 5, wherein, the NBTI test structure schematic diagram that Fig. 4 provides for the embodiment of the present invention, the added voltage schematic diagram of device grids in the NBTI method of testing that Fig. 5 provides for the embodiment of the present invention.In conjunction with Fig. 4 and Fig. 5, the test structure of the semiconductor devices negative bias thermal instability that the embodiment of the present invention provides comprises a bias voltage output unit, wherein, described semiconductor devices comprises grid g, source electrode s, drain electrode d and body electrode b, described grid g is connected with described bias voltage output unit, while adding stress negative bias or test voltage on described grid g, described bias voltage output unit does not affect the voltage on described grid g; Voltage on described grid g by stress negative bias Vstress slew test voltage Vmeasure during or by test voltage Vmeasure turn to stress negative bias Vstress during, described bias voltage output unit maintains voltage to described grid g output one, and described in maintain voltage value be less than zero.
Further, described bias voltage output unit comprises the first resistance R of series connection successively 1, diode D and the second resistance R 2; Described the first resistance R 1a termination one first bias voltage V 1, diode D described in its another termination; Described the second resistance R 2grid g described in one termination of connecting with described diode D, stress negative bias Vstress or test voltage Vmeasure described in its another termination; When described the second resistance R 2the voltage of the other end by stress negative bias Vstress slew test voltage Vmeasure during or by test voltage Vmeasure turn to stress negative bias Vstress during, described diode D opens, in other situation, described diode D disconnects.
Further, the computing formula that maintains voltage described in is:
V H = R 2 R 1 + R 2 V 1
Wherein, V hfor maintaining voltage, R 1be the resistance of the first resistance, R 2be the resistance of the second resistance, V 1it is the first bias voltage.
Further, R 2> R 1, preferably, R 2> 5R 1thereby, can guarantee described the first bias voltage V 1can be added in to greatest extent described the second resistance R 2upper, described in making, maintain voltage V happroach described the first bias voltage V as far as possible 1.
Further, described the first bias voltage V 1absolute value be less than the absolute value of described test voltage Vmeasure, the absolute value of described test voltage Vmeasure is less than the absolute value of described stress negative bias Vstress, when the absolute value of described grid voltage is less than described the first bias voltage V 1absolute value time, described diode D opens.
Further, when described grid g scoops out power negative bias Vstress, described body electrode b ground connection; When described grid meets test voltage Vmeasure, described drain electrode d meets test voltage Vmeasure, and described source electrode s and described body electrode b ground connection; Thereby can measure the unit for electrical property parameters of semiconductor devices.
The principle of the test structure of the semiconductor devices negative bias thermal instability that the embodiment of the present invention provides is as follows:
When described the second resistance R 2scoop out power negative bias Vstress, or during test voltage Vmeasure, described diode D closes, therefore, the electric current of semiconductor devices is very little, is about 10 -9a, negligible, so described the second resistance R 2on voltage drop also negligible, thereby make voltage and the gate source voltage V of grid gsequate, equal stress negative bias Vstress or test voltage Vmeasure, described bias voltage output unit does not exert an influence to voltage stress biasing and the test of device;
As described gate source voltage V gsduring=GND, the absolute value that meets grid voltage is less than described the first bias voltage V 1the condition of absolute value, therefore, described diode D opens, described bias voltage output unit maintains voltage V toward the grid input of device hthereby, make described the second resistance R 2the voltage of the other end by stress negative bias Vstress slew test voltage Vmeasure during or by test voltage Vmeasure turn to stress negative bias Vstress during, therefore the bias voltage on described grid is non-vanishing all the time, can not produce recovery Effects.
Meanwhile, the method for testing of the semiconductor devices negative bias thermal instability that the embodiment of the present invention provides utilizes the test structure of above-mentioned semiconductor devices negative bias thermal instability to test, and comprises the steps:
(1) the grid g of described semiconductor devices is scooped out to power negative bias Vstress, make described grid g under negative bias effect of stress;
(2) remove described stress negative bias Vstress, toward described grid g, add and maintain voltage V h;
(3) maintain voltage V described in removing h, described grid g is met to test voltage Vmeasure, described semiconductor devices is carried out to electric performance test.
In sum, the invention provides a kind of test structure of semiconductor devices negative bias thermal instability, this structure comprises a bias voltage output unit, the voltage of described bias voltage output unit on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improved the accuracy of NBTI test result, simultaneously, the present invention also provides a kind of method of testing of semiconductor devices negative bias thermal instability, the method by the voltage on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, to described grid output one, maintain voltage, and described in maintain voltage value be less than zero, thereby make in the test process of whole NBTI, described grid is all connected to negative bias, therefore can avoid the generation of recovery Effects, improve the accuracy of NBTI test result.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.

Claims (7)

1. the test structure of a semiconductor devices negative bias thermal instability, wherein, described semiconductor devices comprises grid, source electrode, drain electrode and body electrode, it is characterized in that, described grid is connected with a bias voltage output unit, while adding stress negative bias or test voltage on described grid, described bias voltage output unit does not affect the voltage on described grid; Voltage on described grid by stress negative bias slew test voltage during or by test voltage turn to stress negative bias during, described bias voltage output unit maintains voltage to described grid output one, and described in maintain voltage value be less than zero; Wherein, described bias voltage output unit comprises the first resistance, diode and second resistance of series connection successively; One termination one first bias voltage of described the first resistance, diode described in its another termination; Grid described in the termination that described the second resistance is connected with described diode, stress negative bias or test voltage described in its another termination; During the voltage of the described second resistance other end is by stress negative bias slew test voltage or by test voltage, turned to stress negative bias during, described diode is opened, in other situation, described diode disconnects.
2. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 1, is characterized in that, described in maintain voltage computing formula be:
V H = R 2 R 1 + R 2 V 1
Wherein, V hfor maintaining voltage, R 1be the resistance of the first resistance, R 2be the resistance of the second resistance, V 1it is the first bias voltage.
3. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 2, is characterized in that, R 2>R 1.
4. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 3, is characterized in that, R 2>5R 1.
5. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 4, it is characterized in that, the absolute value of described the first bias voltage is less than the absolute value of described test voltage, the absolute value of described test voltage is less than the absolute value of described stress negative bias, when the absolute value of described grid voltage is less than the absolute value of described the first bias voltage, described diode is opened.
6. the test structure of semiconductor devices negative bias thermal instability as claimed in claim 1, is characterized in that, when described grid scoops out power negative bias, and described body electrode grounding; When described grid connects test voltage, described drain electrode connects test voltage, and described source electrode and described body electrode grounding.
7. a method of testing for semiconductor devices negative bias thermal instability, utilizes the test structure of the semiconductor devices negative bias thermal instability described in claim 1 to 6 any one to test, and it is characterized in that, the method comprises the steps:
(1) grid of described semiconductor devices is scooped out to power negative bias, make described grid under negative bias effect of stress;
(2) remove described stress negative bias, toward described grid, add and maintain voltage;
(3) maintain voltage described in removing, described grid is connect to test voltage, described semiconductor devices is carried out to electric performance test.
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CN103941172B (en) * 2013-01-22 2016-12-28 中芯国际集成电路制造(上海)有限公司 Semiconductor test apparatus and method of testing
US9404960B2 (en) 2013-09-30 2016-08-02 Globalfoundries Inc. On chip bias temperature instability characterization of a semiconductor device
CN108037438B (en) * 2017-12-13 2020-10-09 中国科学院新疆理化技术研究所 Method for testing influence of total dose irradiation on negative bias temperature instability of PMOSFET
CN111381139B (en) * 2018-12-29 2022-04-26 长鑫存储技术有限公司 Semiconductor device testing method and semiconductor device testing system
CN111381140B (en) * 2018-12-29 2022-04-15 长鑫存储技术有限公司 Semiconductor element testing method and apparatus
CN115061028B (en) * 2022-06-23 2023-03-24 四川锶未铼科技有限公司 Silicon carbide MOSFET threshold drift test circuit and test method

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