CN102710279A - 60 GHz receiver - Google Patents
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- CN102710279A CN102710279A CN2012102079451A CN201210207945A CN102710279A CN 102710279 A CN102710279 A CN 102710279A CN 2012102079451 A CN2012102079451 A CN 2012102079451A CN 201210207945 A CN201210207945 A CN 201210207945A CN 102710279 A CN102710279 A CN 102710279A
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Abstract
The invention provides a 60 GHz receiver. The 60 GHz receiver comprises a frequency multiplier and a phase-lock loop frequency synthesizer; wherein a fractional frequency module of the phase-lock loop frequency synthesizer comprises a single-mode frequency divider and a four-mode frequency divider divided by from 27 to 30, which are connected in series; the frequency multiplication value of the frequency multiplier is M; the fractional frequency ratio of the single-mode frequency divider is N; the relation between an output frequency of a voltage controlled oscillator (fVCO) and a received frequency (fRF) received by a radio-frequency receiving end is that the fVCO is equal to the fRF divides by the M plus one, and the fRF adopts the value 58.32 GHz, 60.48 GHz and 62.64 GHz or 64.8 GHz respectively; the relation of the reference frequency to generating output reference frequency fREF of the module is that the fREF is equal to 2.16 GHz divides by the value of M plus one and multiply by N. According to the 60 GHz receiver provided by the invention, the fractional frequency module of the phase-lock loop is used for receiving four-channel information with 2.16 GHz interval for the receiver to provide accurate voltage controlled oscillation frequency and the system framework can be flexibly combined and selected.
Description
Technical field
The invention belongs to the wireless receiving and dispatching machine technology, particularly the frequency synthesizer technology.
Background technology
The wireless communication system that is operated near the open bandwidth of the 7GHz of 60GHz can be realized the high data transmission rate of several Gbps.The high attenuation rate of 60GHz electromagnetic wave in atmosphere makes it be applicable to indoor short-range applications such as wireless personal local area network mechanics of communication WPAN, HDMI HDMI.The millimeter wave frequency band transceiver generally adopts III-V family technology to realize, because III-V family technology can reach good performance when high frequency.However, for the market volume production, designer and foundries have produced keen interest and have begun on silicon chip, to design millimeter wave transceiver the complementary metal oxide semiconductors (CMOS) CMOS technology of cheapness.The millimeter wave frequency band transceiver adopts CMOS technology to realize more and more.
Being used for the frequency synthesizer of local oscillations is provided is the core circuit of 60GHz transceiver.Have the phase-locked loop report that some are the 60GHz system design, such as single mode phase-locked loop and the multichannel frequency synthesizer that comprises programmable frequency divider.Though the lock-in range of some phase-locked loop can cover the 60GHz frequency range; But they all can not with the four channel carrier wave frequencies that define by IEEE 802.15.3c (communicating by letter and information exchange-local and metropolitan area network specific (special) requirements the 15.3rd part between information technology ieee standard-system: wireless medium access control MAC and the physical layer PHY standard of high-rate wireless territory net): 58.32; 60.48; 62.64 64.8GHz is compatible.
Summary of the invention
Technical problem to be solved by this invention is, provides compatible mutually with IEEE 802.15.3c standard, can accurately receive 58.32,60.48,62.64 with the receiver of these four channel carrier wave frequencies of 64.8GHz.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be, a kind of 60GHz receiver, comprises low noise amplifier, first order frequency mixer, first order variable gain amplifier, second level frequency mixer, second level variable gain amplifier, frequency multiplier, phase-locked loop frequency integrator;
Said low noise amplifier links to each other with an input of first order frequency mixer; Another input of first order frequency mixer links to each other with the output of frequency multiplier; The output of first order frequency mixer links to each other with first order variable gain amplifier input, first order variable gain amplifier output links to each other with an input of second level frequency mixer; Another input of second level frequency mixer links to each other with the output of phase-locked loop frequency integrator, and the output of second level frequency mixer links to each other with second level variable gain amplifier, the output of phase-locked loop frequency integrator also links to each other with the input of frequency multiplier;
Phase-locked loop frequency integrator comprises reference crystal oscillator, phase frequency detector, orthogonal voltage-controlled vibrator, charge pump, loop filter and frequency division module; An output of orthogonal voltage-controlled vibrator is used to export local oscillating frequency; Another output links to each other with the input of frequency division module; The frequency division module output links to each other with an input of phase frequency detector; Another input of phase frequency detector links to each other with the output of reference crystal oscillator; The output of phase frequency detector links to each other with the input of charge pump, and the electric charge delivery side of pump links to each other with the input of loop filter, and the output of loop filter links to each other with the control end of orthogonal voltage-controlled vibrator;
Frequency division module comprises the single mode frequency divider, removes 27 to 30 4 mould frequency dividers, the single mode frequency divider with connect except that 27 to 30 4 mould frequency dividers; The frequency of said frequency multiplier is M, and the frequency dividing ratio of said single mode frequency divider is N, the output frequency f of voltage controlled oscillator
VCOFrequency f with the reception of radio frequency receiving terminal
RFRelation be: f
VCO=f
RF/ (M+1), f
RFBe 58.32,60.48,62.64 or 64.8GHz; The reference frequency f of reference frequency generation module output
REFRelation be: f
REF=2.16GHz/ ((M+1) * N).
Because receiver need receive the centre frequency 58.32,60.48,62.64 and the 64.8GHz of four channels, channel frequency separation is 2.16GHz.The centre frequency of four channels is respectively 27,28,29,30 times of channel frequency separation 2.16GHz.Frequency multiplier places between first order frequency mixer and the voltage controlled oscillator to carry out first order down-conversion; The output of voltage controlled oscillator directly links to each other with second level frequency mixer and downconverts to zero intermediate frequency to carry out the second level; Realization is the accurate reception of the 60GHz frequency band signals of 2.16GHz to channel frequency separation, satisfies IEEE 802.15.3c standard.The reference frequency f that provides through the present invention
REF, frequency multiplier frequency dividing ratio N and the frequency f of voltage controlled oscillator output of frequency M, single mode frequency divider
VCORelation, can the combination selection receiver and the framework of phase-locked loop frequency integrator.
Concrete; Said 27 to the 30 4 mould frequency dividers that remove comprise that removing 3/4 dual-mode frequency divider, 2 removes 3 frequency dividers, model selection control unit; Remove 3/4 dual-mode frequency divider and 2 and remove the series connection of 3 frequency dividers, the model selection control unit links to each other with the control end that removes 3/4 dual-mode frequency divider; Be 3 when the control of model selection control unit removes the divider ratio of 3/4 dual-mode frequency divider in 9 cycles, then four mould frequency dividers are to remove 27 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 1 cycle in 9 cycles when the model selection control unit is 4, and the divider ratio in other 8 cycles is 3, and then four mould frequency dividers are to remove 28 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 2 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 7 cycles is 3, and then four mould frequency dividers are to remove 29 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 3 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 6 cycles is 3, and then four mould frequency dividers are to remove 30 state.
The invention has the beneficial effects as follows, be that receiver receives the four-way information be spaced apart 2.16GHz VCO frequency accurately is provided through frequency division module in the phase-locked loop, and system architecture is combination selection neatly.
Description of drawings
Fig. 1 is phase-locked loop frequency integrator of the present invention and receiver system structural representation;
Fig. 2 removes 27 to 30 4 mould fraction frequency device figure for embodiment;
Fig. 3 removes 27 to 30 4 mould frequency divider schematic diagrams for embodiment.
Embodiment
As shown in Figure 1, be receiver and phase-locked loop frequency integrator framework, comprise low noise amplifier, first order frequency mixer, first order variable gain amplifier, second level frequency mixer, second level variable gain amplifier, frequency multiplier, phase-locked loop frequency integrator;
Said low noise amplifier links to each other with an input of first order frequency mixer; Another input of first order frequency mixer links to each other with the output of frequency multiplier; The output of first order frequency mixer links to each other with first order variable gain amplifier input, first order variable gain amplifier output links to each other with an input of second level frequency mixer; Another input of second level frequency mixer links to each other with the output of phase-locked loop frequency integrator, and the output of second level frequency mixer links to each other with second level variable gain amplifier, the output of phase-locked loop frequency integrator also links to each other with the input of frequency multiplier; Recover raw baseband signal behind the radiofrequency signal process receiver double conversion.
Phase-locked loop frequency integrator comprises reference crystal oscillator, orthogonal voltage-controlled vibrator VCO, phase frequency detector PFD, charge pump CP, loop filter LPF and frequency division module; An output of orthogonal voltage-controlled vibrator is used to export local oscillating frequency; Another output links to each other with the input of frequency division module; The frequency division module output links to each other with an input of phase frequency detector; Another input of phase frequency detector links to each other with the output of reference crystal oscillator; The output of phase frequency detector links to each other with the input of charge pump, and the electric charge delivery side of pump links to each other with the input of loop filter, and the output of loop filter links to each other with the control end of orthogonal voltage-controlled vibrator; Frequency division module comprise frequency division be N the single mode frequency divider, remove 27 to 30 4 mould frequency dividers, the single mode frequency divider with connect except that 27 to 30 4 mould frequency dividers.Frequency division is that the single mode frequency divider of N can be one and removes the Fractional-N frequency device, also can be the frequency divider link that a frequency dividing ratio is N.
The output frequency f of voltage controlled oscillator
VCOWith reception signal frequency f
RFRelation be f
VCO=f
RF/ (M+1).The centre frequency 58.32,60.48,62.64 and the 64.8GHz of four channels is 27-30 times of channel frequency separation 2.16GHz.Therefore, four mould 27-30 frequency dividers are the core circuit of phase-locked loop frequency integrator.The relation of frequency dividing ratio N, frequency multiplier frequency M and the reference frequency of the single mode frequency divider that the voltage controlled oscillator output connects is: f
REF=2.16GHz/ ((M+1) * N), wherein 2.16GHz=2
4* 3
5* 5MHz.Therefore, can pass through M, N and f
REFThe framework of combination selection phase-locked loop frequency integrator, M, N and f
REFBe positive integer.
Such as, it is 2 that frequency multiplier frequency M is set, frequency dividing ratio N is 6, f
REFBe 120MHz.Frequency division is that the single mode frequency divider of N is one and removes 2 frequency dividers and remove the frequency division link that 3 frequency dividers are in series.Orthogonal voltage-controlled vibrator is used to produce the quadrature rectilinear oscillation signal of 20GHz, and changes output frequency according to the input voltage of control end.
Remove 2 frequency dividers in the frequency division module, remove 3 frequency dividers and connect except that 27 to 30 4 mould frequency dividers.
Removing 2 frequency dividers is used for the oscillator signal that VCO produces is presorted frequently.
Removing 3 frequency dividers is used for carrying out three frequency division to presorting the frequency signal.
Removing 27 to 30 4 mould frequency dividers is used for signal after removing 3 frequency divider frequency divisions is carried out frequency programmable dividing.
When four mould frequency dividers are that it is 19.44GHz that orthogonal voltage-controlled vibrator is stablized output frequency when removing 27 state; When four mould frequency dividers when removing 28 state, handing over voltage controlled oscillator to stablize output frequency is 20.16GHz; Just when four mould frequency dividers is when removing 29 state, and the frequency of the stable output of orthogonal voltage-controlled vibrator is 20.88GHz; When four mould frequency dividers are that the frequency that orthogonal voltage-controlled vibrator is stablized output is 21.60GHz when removing 30 state.
Phase frequency detector PFD is used for the comparison of phase-locked loop phase place and frequency, promptly compares frequency and phase place between 120MHz reference signal and the four mould output signal of frequency divider.Under the stable situation of VCO output frequency, the frequency of four mould output signal of frequency divider also is 120MHz, like four mould frequency divider operation when 27 states of removing; VCO is output as 19.44GHz, and through removing 2, removing 3 and remove after 27, the frequency behind the frequency division is 120MHz respectively; When VCO stablizes for output; PFD then can compare the reference signal of four mould output signal of frequency divider and standard, and output contains the potential pulse of distinguishing signal, with adjustment VCO.
Charge pump CP is used for the potential pulse of PFD output is converted into current impulse;
Loop filter LPF is used for the electric current of charge pump CP output is transferred to voltage and this voltage signal is carried out LPF, to VCO direct-current control voltage to be provided.
Frequency synthesizer is 20GHz four channel frequencys of 0.72GHz through the pll lock frequency interval; Like this receiver with the frequency frequency multiplication of frequency synthesizer output to the 40GHz with the 60GHz signal mixing that receives to 20GHz, the signal after the mixing again with frequency synthesizer 20GHz signal mixing to zero intermediate frequency.So this frequency synthesizer can be the four channel carrier wave frequencies of 2.16 (0.72 * 3) GHz with the frequency interval that receives: 58.32,60.48,62.64,64.8GHz is mixed to zero intermediate frequency.
Remove 27 to 30 4 mould frequency dividers, as shown in Figure 2, four mould frequency dividers comprise that one is removed 3/4 dual-mode frequency divider, two and removes 3 frequency dividers, model selection control unit, can realize removing the variation of 27 to 30 frequency dividing ratios through model selection.Remove 3/4 dual-mode frequency divider and 2 and remove the series connection of 3 frequency dividers, the model selection control unit links to each other with the control end that removes 3/4 dual-mode frequency divider; The model selection control unit comprises 2 and door and 4:1 multiplexer.
The output Q of 4:1 multiplexer links to each other with the control end MC that removes 3/4 dual-mode frequency divider, removes 3/4 dual-mode frequency divider output output signal Q
0, with the output output signal Q that removes 3 frequency dividers that links to each other except that 3/4 dual-mode frequency divider
1, another removes the output output signal Q of 3 frequency dividers
22 are removed the output of 3 frequency dividers and are connected with the 4:1 multiplexer with door through two; With remove that 3/4 dual-mode frequency divider links to each other remove 3 frequency divider outputs connect respectively the input B of 4:1 multiplexer corresponding with door and input C corresponding with door, another connect respectively except that 3 frequency divider outputs the 4:1 multiplexer input C correspondence with door and input D.
Two trigger end A0 of 4:1 multiplexer, A1 and remove the level height that 3 frequency dividers output Q1, the common decision of Q2 remove the pattern control level MC of 3/4 dual-mode frequency divider are to realize the effect of control model.Be 3 when the control of model selection control unit removes the divider ratio of 3/4 dual-mode frequency divider in 9 cycles, then four mould frequency dividers are to remove 27 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 1 cycle in 9 cycles when the model selection control unit is 4, and the divider ratio in other 8 cycles is 3, and then four mould frequency dividers are to remove 28 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 2 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 7 cycles is 3, and then four mould frequency dividers are to remove 29 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 3 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 6 cycles is 3, and then four mould frequency dividers are to remove 30 state, and are as shown in Figure 3:
Remove 27 to 30 4 mould frequency dividers and will export a fractional frequency signal, removing 3/4 dual-mode frequency divider needs 9 cycles of work, needs 3 cycles of work with 3 frequency dividers that remove that link to each other except that 3/4 dual-mode frequency divider, and another removes 3 frequency dividers and only works 1 cycle.
When MC was low level, frequency divider was for removing 3 circuit; When MC was high level, frequency divider was for removing 4 circuit.
When A0A1=00, the 4:1 multiplexer is sent to input Q with the state of input A=0 makes MC be low level in 9 cycles removing 3/4 dual-mode frequency divider always, like Fig. 3 (a) and (b); This moment, bimodulus had only 3 cycles of removing except that 3/4 frequency divider; Do not remove for 4 cycles, therefore, frequency dividing ratio is 27;
When A0A1=10, the 4:1 multiplexer is sent to input Q with the state of input B, finds out that from Fig. 3 (a), (c) Q0 is during last cycle; Q1Q2 is high level; Also be changed to high level with goalkeeper B this moment, and at this moment, MC has one to remove 4 cycles and 8 and removed for 3 cycles removing 3/4 dual-mode frequency divider; Therefore, frequency dividing ratio is 28;
When A0A1=01, the 4:1 multiplexer is sent to input Q with the state of input C, when Fig. 3 (a), (d) can find out Q0 the 7th and the 8th cycle; Q1 is a low level; Q2 is a high level, and be changed to high level with goalkeeper C this moment, therefore; MC has 2 to remove 4 cycles and 7 and removed for 3 cycles removing 3/4 dual-mode frequency divider in 9 cycles, frequency dividing ratio is 29;
When A0A1=11; The 4:1 multiplexer is sent to Q with the state of D, can find out Q0 during the 7th, 8,9 cycles from Fig. 3 (a), (e), and Q2 is a high level; Be changed to high level with goalkeeper D this moment; Therefore, MC has 3 to remove 4 cycles and 6 and removed for 3 cycles removing 3/4 dual-mode frequency divider in 9 cycles, and frequency dividing ratio is 30.
The structure of other devices is existing among the embodiment, does not give unnecessary details at this.Each frequency divider adopts large scale PMOS load transistor and small size latch transistor can obtain little propagation delay and high workload frequency.
Based on UMC 90nm CMOS process simulation, be 120MHz in reference frequency, supply voltage is under the condition of 1V.The present embodiment phase-locked loop frequency integrator can accurately produce four channel center frequencies.The double conversion superheterodyne receiver can be locked in the centre frequency by four 60GHz frequency channels of IEEE 802.15.3c definition.Emulation shows that the locking time of this phase-locked loop, power consumption was 50mW less than 3 μ s.
Claims (3)
1. a 60GHz receiver is characterized in that, comprises low noise amplifier, first order frequency mixer, first order variable gain amplifier, second level frequency mixer, second level variable gain amplifier, frequency multiplier, phase-locked loop frequency integrator;
Said low noise amplifier links to each other with an input of first order frequency mixer; Another input of first order frequency mixer links to each other with the output of frequency multiplier; The output of first order frequency mixer links to each other with first order variable gain amplifier input, first order variable gain amplifier output links to each other with an input of second level frequency mixer; Another input of second level frequency mixer links to each other with the output of phase-locked loop frequency integrator, and the output of second level frequency mixer links to each other with second level variable gain amplifier, the output of phase-locked loop frequency integrator also links to each other with the input of frequency multiplier;
Phase-locked loop frequency integrator comprises reference crystal oscillator, phase frequency detector, orthogonal voltage-controlled vibrator, charge pump, loop filter and frequency division module; An output of orthogonal voltage-controlled vibrator is used to export local oscillating frequency, and another output links to each other with the input of frequency division module, and the frequency division module output links to each other with an input of phase frequency detector, phase frequency detector in addition
An input links to each other with the output of reference crystal oscillator; The output of phase frequency detector links to each other with the input of charge pump; The electric charge delivery side of pump links to each other with the input of loop filter, and the output of loop filter links to each other with the control end of orthogonal voltage-controlled vibrator;
Frequency division module comprises the single mode frequency divider, removes 27 to 30 4 mould frequency dividers, the single mode frequency divider with connect except that 27 to 30 4 mould frequency dividers; The frequency of said frequency multiplier is M, and the frequency dividing ratio of said single mode frequency divider is N, the output frequency f of voltage controlled oscillator
VCOFrequency f with the reception of radio frequency receiving terminal
RFRelation be: f
VCO=f
RF/ (M+1), f
RFBe 58.32,60.48,62.64 or 64.8GHz; The reference frequency f of reference frequency generation module output
REFRelation be: f
REF=2.16GHz/ ((M+1) * N).
2. a kind of according to claim 1 60GHz receiver; It is characterized in that; Said 27 to the 30 4 mould frequency dividers that remove comprise that removing 3/4 dual-mode frequency divider, 2 removes 3 frequency dividers, model selection control unit; Remove 3/4 dual-mode frequency divider and 2 and remove the series connection of 3 frequency dividers, the model selection control unit links to each other with the control end that removes 3/4 dual-mode frequency divider;
Be 3 when the control of model selection control unit removes the divider ratio of 3/4 dual-mode frequency divider in 9 cycles, then four mould frequency dividers are to remove 27 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 1 cycle in 9 cycles when the model selection control unit is 4, and the divider ratio in other 8 cycles is 3, and then four mould frequency dividers are to remove 28 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 2 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 7 cycles is 3, and then four mould frequency dividers are to remove 29 state; Controlling except that 3/4 dual-mode frequency divider has the divider ratio in 3 cycles in 9 cycles when the model selection control unit is 4, and the divider ratio in other 6 cycles is 3, and then four mould frequency dividers are to remove 30 state.
3. a kind of according to claim 1 60GHz receiver is characterized in that the frequency of said frequency multiplier is 2, and the frequency dividing ratio of said single mode frequency divider is 6, the reference frequency f of reference frequency generation module output
REFBe 120GHz/ ((M+1) * N) frequency f of voltage controlled oscillator output
VCOBe 19.44GHz, 20.16GHz, 20.88GHz or 21.60GHz.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039521A (en) * | 2020-08-27 | 2020-12-04 | 珠海市一微半导体有限公司 | Four-mode frequency divider for fractional frequency division, fractional phase-locked loop and chip |
| CN112367089A (en) * | 2020-10-27 | 2021-02-12 | 上海磐启微电子有限公司 | Radio frequency transmitting device |
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| US20060271476A1 (en) * | 2001-09-26 | 2006-11-30 | First Data Corporation | Systems and methods to facilitate payment for shipped goods |
| CN102324930A (en) * | 2011-05-12 | 2012-01-18 | 西安电子科技大学 | Superspeed 8/9 bimodule prescaler based on GaAa hetero junction bipolar transistor (HBT) device |
| CN102394636A (en) * | 2011-11-24 | 2012-03-28 | 思瑞浦(苏州)微电子有限公司 | Four-module frequency divider with low noise |
-
2012
- 2012-06-21 CN CN201210207945.1A patent/CN102710279B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060271476A1 (en) * | 2001-09-26 | 2006-11-30 | First Data Corporation | Systems and methods to facilitate payment for shipped goods |
| CN102324930A (en) * | 2011-05-12 | 2012-01-18 | 西安电子科技大学 | Superspeed 8/9 bimodule prescaler based on GaAa hetero junction bipolar transistor (HBT) device |
| CN102394636A (en) * | 2011-11-24 | 2012-03-28 | 思瑞浦(苏州)微电子有限公司 | Four-module frequency divider with low noise |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112039521A (en) * | 2020-08-27 | 2020-12-04 | 珠海市一微半导体有限公司 | Four-mode frequency divider for fractional frequency division, fractional phase-locked loop and chip |
| CN112367089A (en) * | 2020-10-27 | 2021-02-12 | 上海磐启微电子有限公司 | Radio frequency transmitting device |
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