CN102710129B - High-precision DC/DC converter current limiting circuit - Google Patents
High-precision DC/DC converter current limiting circuit Download PDFInfo
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- CN102710129B CN102710129B CN201210179256.4A CN201210179256A CN102710129B CN 102710129 B CN102710129 B CN 102710129B CN 201210179256 A CN201210179256 A CN 201210179256A CN 102710129 B CN102710129 B CN 102710129B
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Abstract
The invention particularly relates to a high-precision DC/DC converter current limiting circuit, which is characterized by comprising an EA error amplifier and a current limiting compensation circuit, wherein the current limiting compensation circuit consists of a comparator and a current limiting circuit. According to the invention, high-precision current limiting is achieved via current limiting drifting caused by brand new compensation circuit compensation system duty ratio change, and further the performance of a system is ameliorated.
Description
Technical field
The invention belongs to electricity field, particularly to a kind of high accuracy DC/DC transducer current-limiting circuit.
Background technology
DC energy storage portable electric appts fast development in recent years, DC/DC class power management products demand expands increasingly,
With becoming stronger day by day of portable electric appts function, the performance requirement of DC/DC integrated power supply management system increasingly improves.Tradition
The current limit precision of DC/DC transducer is poor, changes with the change of converting system dutycycle, thus have impact in system
The peak point current precision in portion, and then have impact on power-supply system reliability of operation, or even the normal work of impact whole equipment.
Content of the invention
The mesh ground of the present invention is to provide a kind of high accuracy DC/DC transducer current-limiting circuit, realizes current limit and system work
Make dutycycle unrelated it is ensured that the work of system safety and stability.
For achieving the above object, the technical solution used in the present invention is：
A kind of high accuracy DC/DC transducer current-limiting circuit is it is characterised in that include EA error amplifier and current limit benefit
Repay circuit.
Described EA error amplifier is cascade one-stage amplifier, including seven p-type metal-oxide-semiconductors and four N-type metal-oxide-semiconductors,
Its connected mode is：The source of the drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3
Pole connects；The grid of the second p-type metal-oxide-semiconductor MP2 is connected with the input in the same direction of this error amplifier；3rd p-type metal-oxide-semiconductor MP3's
Grid is connected with the reverse input end of this error amplifier；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the source of the 3rd N-type metal-oxide-semiconductor MN3
Pole is connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 and
The drain electrode of two N-type metal-oxide-semiconductor MN2 connects；The grid of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5, the 6th p-type
The drain electrode of metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 and the 6th p-type metal-oxide-semiconductor
The source electrode of MP6 connects；The drain electrode of the 5th p-type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；7th p-type metal-oxide-semiconductor
The drain electrode of MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier；First p-type metal-oxide-semiconductor
The grid of MP1 is connected with bias voltage Vpb1；The grid of the 6th p-type metal-oxide-semiconductor MP6, the grid of the 7th p-type metal-oxide-semiconductor MP7 and biasing
Voltage Vpb2 connects；The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1；The
The grid of three N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2, the first p-type metal-oxide-semiconductor MP1's
Source electrode, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5 are connected with power vd D, the first N-type metal-oxide-semiconductor MN1
Source electrode, the source electrode of the second N-type metal-oxide-semiconductor MN2 with ground GND be connected.
Described current limit compensation circuit includes comparator and current-limiting circuit.
Described comparator includes an electric current leakage, five p-type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, and its connected mode is：0th
The drain electrode of p-type metal-oxide-semiconductor MP0, the grid of the 0th p-type metal-oxide-semiconductor MP0, the input of current source I, the grid of the 4th p-type metal-oxide-semiconductor MP4
It is connected with the grid of the first p-type metal-oxide-semiconductor MP1；The drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode and the 3rd of the second p-type metal-oxide-semiconductor MP2
The source electrode of p-type metal-oxide-semiconductor MP3 connects；The VP of input port in the same direction of this comparator is connected with the grid of the 3rd p-type metal-oxide-semiconductor MP3；Should
The reverse input end mouth VN of comparator is connected with the grid of the second p-type metal-oxide-semiconductor MP2；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the 0th N
The grid of type metal-oxide-semiconductor MN0, the drain electrode of the 0th N-type metal-oxide-semiconductor MN0 are connected with the grid of the first N-type metal-oxide-semiconductor MN1；3rd p-type MOS
The drain electrode of pipe MP3, the drain electrode of the first N-type metal-oxide-semiconductor MN1 are connected with the grid of the second N-type metal-oxide-semiconductor MN2；4th p-type metal-oxide-semiconductor MP4
Drain electrode, the drain electrode of the second N-type metal-oxide-semiconductor MN2 be connected with the output end vo ut of amplifier, the source electrode of the 0th p-type metal-oxide-semiconductor MP0, first
The source electrode of p-type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4 are connected with power vd D, the source electrode of the 0th N-type metal-oxide-semiconductor MN0,
The source electrode of one N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I are connected with ground GND.
The connected mode of described current-limiting circuit is：The in-phase input end of the first operational amplifier VO1 is connected with port Vin；
The in-phase input end of the second operational amplifier VO2 is connected with port Vo；The outfan of the first operational amplifier VO1 and the 0th N-type
The grid of metal-oxide-semiconductor MN0 connects；The outfan of the second operational amplifier VO2 is connected with the grid of the 5th N-type metal-oxide-semiconductor MN5；First
The inverting input of operational amplifier VO1, the source electrode of the 0th N-type metal-oxide-semiconductor MN0 are connected with one end of resistance R1；Second computing is put
The inverting input of big device VO2, the source electrode of the 5th N-type metal-oxide-semiconductor MN5 are connected with one end of resistance R2；First p-type metal-oxide-semiconductor MP1's
Drain electrode, the drain electrode of the grid of the first p-type metal-oxide-semiconductor MP1, the 0th N-type metal-oxide-semiconductor MN0 are connected with the grid of the second p-type metal-oxide-semiconductor MP2；
The drain electrode of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 4th p-type metal-oxide-semiconductor MP4, the drain electrode of the 5th N-type metal-oxide-semiconductor MN5 and the 3rd p-type MOS
The grid of pipe MP3 connects；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the drain electrode of the second N-type metal-oxide-semiconductor MN2, the second N-type metal-oxide-semiconductor MN2
Grid, the grid of the first N-type metal-oxide-semiconductor MN1 are connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3,
The drain electrode of the 4th N-type metal-oxide-semiconductor MN4, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with the grid of the 3rd N-type metal-oxide-semiconductor MN3；Resistance R3
One end be connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；The source electrode of the first p-type metal-oxide-semiconductor MP1, the source of the second p-type metal-oxide-semiconductor MP2
Pole, the source electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the other end of resistance R3 are connected with power vd D, electricity
The other end of resistance R1, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the source of the 3rd N-type metal-oxide-semiconductor MN3
Pole, the source electrode of the 4th N-type metal-oxide-semiconductor MN4, the other end of resistance R2 are connected with ground GND.
The present invention provides a kind of high accuracy DC/DC transducer current-limiting circuit, and it is by brand-new compensation circuit compensation system
The current limit drift that change in duty cycle leads to, thus realizing high-precision current limit, improves the performance of system.
Brief description
Fig. 1 is EA error amplifier circuit structure chart of the present invention.
Fig. 2 is comparator circuit structure chart of the present invention.
Fig. 3 is current-limiting circuit structure chart of the present invention.
Fig. 4 limits potential circuit structure chart for the present invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention will be further described.
Present embodiment describes a kind of high accuracy DC/DC transducer current-limiting circuit, including EA error amplifier and electric current limit
Compensation circuit processed.
As shown in figure 1, described EA error amplifier is cascade one-stage amplifier, including seven p-type metal-oxide-semiconductors and four
N-type metal-oxide-semiconductor, its connected mode is：The drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type MOS
The source electrode of pipe MP3 connects；The grid of the second p-type metal-oxide-semiconductor MP2 is connected with the input in the same direction of this error amplifier；3rd p-type
The grid of metal-oxide-semiconductor MP3 is connected with the reverse input end of this error amplifier；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the 3rd N-type MOS
The source electrode of pipe MN3 is connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the 4th N-type metal-oxide-semiconductor MN4
Source electrode be connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2；The grid of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5
Pole, the drain electrode of the 6th p-type metal-oxide-semiconductor MP6 are connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 and the
The source electrode of six p-type metal-oxide-semiconductor MP6 connects；The drain electrode of the 5th p-type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；7th
The drain electrode of p-type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier；First P
The grid of type metal-oxide-semiconductor MP1 is connected with bias voltage Vpb1；The grid of the 6th p-type metal-oxide-semiconductor MP6, the grid of the 7th p-type metal-oxide-semiconductor MP7
Pole is connected with bias voltage Vpb2；The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 and bias voltage
Vnb1 connects；The grid of the 3rd N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2, a P
The source electrode of type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5 are connected with power vd D, the
The source electrode of one N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2 are connected with ground GND.
Described current limit compensation circuit includes comparator and current-limiting circuit.
As shown in Fig. 2 described comparator includes an electric current leakage, five p-type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, its connection
Mode is：The drain electrode of the 0th p-type metal-oxide-semiconductor MP0, the grid of the 0th p-type metal-oxide-semiconductor MP0, the input of current source I, the 4th p-type MOS
The grid of pipe MP4 is connected with the grid of the first p-type metal-oxide-semiconductor MP1；The drain electrode of the first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2
Source electrode be connected with the source electrode of the 3rd p-type metal-oxide-semiconductor MP3；The VP of input port in the same direction of this operational amplifier and the 3rd p-type metal-oxide-semiconductor
The grid of MP3 connects；The reverse input end mouth VN of this operational amplifier is connected with the grid of the second p-type metal-oxide-semiconductor MP2；Second p-type
The drain electrode of metal-oxide-semiconductor MP2, the grid of the 0th N-type metal-oxide-semiconductor MN0, the drain electrode of the 0th N-type metal-oxide-semiconductor MN0 are with the first N-type metal-oxide-semiconductor MN1's
Grid connects；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the drain electrode of the first N-type metal-oxide-semiconductor MN1 and the grid of the second N-type metal-oxide-semiconductor MN2 connect
Connect；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4, the drain electrode of the second N-type metal-oxide-semiconductor MN2 are connected with the output end vo ut of amplifier, the 0th p-type
The source electrode of metal-oxide-semiconductor MP0, the source electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4 are connected with power vd D, the 0th N
The source electrode of type metal-oxide-semiconductor MN0, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I
It is connected with ground GND.
As shown in figure 3, the connected mode of described current-limiting circuit is：The in-phase input end of the first operational amplifier VO1 and end
Mouth Vin connects；The in-phase input end of the second operational amplifier VO2 is connected with port Vo；The outfan of the first operational amplifier VO1
It is connected with the grid of the 0th N-type metal-oxide-semiconductor MN0；The outfan of the second operational amplifier VO2 and the grid of the 5th N-type metal-oxide-semiconductor MN5
Connect；The inverting input of the first operational amplifier VO1, the source electrode of the 0th N-type metal-oxide-semiconductor MN0 are connected with one end of resistance R1；The
The inverting input of two operational amplifier VO2, the source electrode of the 5th N-type metal-oxide-semiconductor MN5 are connected with one end of resistance R2；First p-type
The drain electrode of metal-oxide-semiconductor MP1, the grid of the first p-type metal-oxide-semiconductor MP1, the drain electrode of the 0th N-type metal-oxide-semiconductor MN0 are with the second p-type metal-oxide-semiconductor MP2's
Grid connects；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 4th p-type metal-oxide-semiconductor MP4, the drain electrode of the 5th N-type metal-oxide-semiconductor MN5 with
The grid of the 3rd p-type metal-oxide-semiconductor MP3 connects；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the drain electrode of the second N-type metal-oxide-semiconductor MN2, the second N-type
The grid of metal-oxide-semiconductor MN2, the grid of the first N-type metal-oxide-semiconductor MN1 are connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3；3rd p-type metal-oxide-semiconductor
The drain electrode of MP3, the grid of the drain electrode, the grid of the 4th N-type metal-oxide-semiconductor MN4 and the 3rd N-type metal-oxide-semiconductor MN3 of the 4th N-type metal-oxide-semiconductor MN4
Connect；One end of resistance R3 is connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；The source electrode of the first p-type metal-oxide-semiconductor MP1, the second p-type MOS
The source electrode of pipe MP2, the source electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the other end of resistance R3 and power supply
VDD connects, the other end of resistance R1, the source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the 3rd N-type MOS
The source electrode of pipe MN3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4, the other end of resistance R2 are connected with ground GND.
As Fig. 4, in the high accuracy DC/DC transducer current-limiting circuit described by this programme, V voltage is produced by block (clamp)
Raw clamp voltage, this voltage is changed by the change with Vin and Vo, and system duty cycle is directly proportional to input and output voltageThe linear compensation realized by input and output pressure reduction can
Compensate the current limit change that change in duty cycle causes with good.
It is more than that the present invention is illustrated, this programme is not solely restricted in above example, in this programme
Any change made under inventive concept falls within the scope of the present invention.
Claims (2)
1. a kind of high accuracy DC/DC transducer current-limiting circuit it is characterised in that：Compensate including EA error amplifier and current limit
Circuit, current limit compensation circuit includes comparator and current-limiting circuit, and the connected mode of wherein current-limiting circuit is：First computing is put
The in-phase input end of big device VO1 is connected with port Vin；The in-phase input end of the second operational amplifier VO2 is connected with port Vo；The
The outfan of one operational amplifier VO1 is connected with the grid of the 0th N-type metal-oxide-semiconductor MN0；The outfan of the second operational amplifier VO2
It is connected with the grid of the 5th N-type metal-oxide-semiconductor MN5；The inverting input of the first operational amplifier VO1, the source of the 0th N-type metal-oxide-semiconductor MN0
Pole is connected with one end of resistance R1；The inverting input of the second operational amplifier VO2, the source electrode of the 5th N-type metal-oxide-semiconductor MN5 and electricity
One end of resistance R2 connects；The drain electrode of the first p-type metal-oxide-semiconductor MP1, the grid of the first p-type metal-oxide-semiconductor MP1, the 0th N-type metal-oxide-semiconductor MN0
Drain electrode is connected with the grid of the second p-type metal-oxide-semiconductor MP2；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 4th p-type metal-oxide-semiconductor MP4,
The drain electrode of the 5th N-type metal-oxide-semiconductor MN5 is connected with the grid of the 3rd p-type metal-oxide-semiconductor MP3；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the 2nd N
The drain electrode of type metal-oxide-semiconductor MN2, the grid of the second N-type metal-oxide-semiconductor MN2, the grid of the first N-type metal-oxide-semiconductor MN1 and the 3rd N-type metal-oxide-semiconductor MN3
Drain electrode connect；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4, the grid of the 4th N-type metal-oxide-semiconductor MN4
It is connected with the grid of the 3rd N-type metal-oxide-semiconductor MN3；One end of resistance R3 is connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；First p-type
The source electrode of metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2, the source electrode of the 3rd p-type metal-oxide-semiconductor MP3, the 4th p-type metal-oxide-semiconductor MP4
Source electrode, the other end of resistance R3 are connected with power vd D, the other end of resistance R1, the source electrode of the first N-type metal-oxide-semiconductor MN1, the second N-type
The source electrode of metal-oxide-semiconductor MN2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4, the other end of resistance R2 and ground
GND connects；Described EA error amplifier is cascade one-stage amplifier, including seven p-type metal-oxide-semiconductors and four N-type metal-oxide-semiconductors,
Its connected mode is：The source of the drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3
Pole connects；The grid of the second p-type metal-oxide-semiconductor MP2 is connected with the input in the same direction of this error amplifier；3rd p-type metal-oxide-semiconductor MP3's
Grid is connected with the reverse input end of this error amplifier；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the source of the 3rd N-type metal-oxide-semiconductor MN3
Pole is connected with the drain electrode of the first N-type metal-oxide-semiconductor MN1；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 and
The drain electrode of two N-type metal-oxide-semiconductor MN2 connects；The grid of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5, the 6th p-type
The drain electrode of metal-oxide-semiconductor MP6 is connected with the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 and the 6th p-type metal-oxide-semiconductor
The source electrode of MP6 connects；The drain electrode of the 5th p-type metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；7th p-type metal-oxide-semiconductor
The drain electrode of MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4 are connected with the output port Vout of this error amplifier；First p-type metal-oxide-semiconductor
The grid of MP1 is connected with bias voltage Vpb1；The grid of the 6th p-type metal-oxide-semiconductor MP6, the grid of the 7th p-type metal-oxide-semiconductor MP7 and biasing
Voltage Vpb2 connects；The grid of the first N-type metal-oxide-semiconductor MN1, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1；The
The grid of three N-type metal-oxide-semiconductor MN3, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2, the first p-type metal-oxide-semiconductor MP1's
Source electrode, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5 are connected with power vd D, the first N-type metal-oxide-semiconductor MN1
Source electrode, the source electrode of the second N-type metal-oxide-semiconductor MN2 with ground GND be connected.
2. a kind of high accuracy DC/DC transducer current-limiting circuit as claimed in claim 1 it is characterised in that：Described comparator bag
Include an electric current leakage, five p-type metal-oxide-semiconductors and three N-type metal-oxide-semiconductors, its connected mode is：The drain electrode of the 0th p-type metal-oxide-semiconductor MP0,
The grid of zero p-type metal-oxide-semiconductor MP0, the input of current source I, the grid of the 4th p-type metal-oxide-semiconductor MP4 and the first p-type metal-oxide-semiconductor MP1's
Grid connects；The source electrode of the drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3 is even
Connect；The VP of input port in the same direction of this comparator is connected with the grid of the 3rd p-type metal-oxide-semiconductor MP3；The reverse input end mouth of this comparator
VN is connected with the grid of the second p-type metal-oxide-semiconductor MP2；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the grid of the 0th N-type metal-oxide-semiconductor MN0,
The drain electrode of zero N-type metal-oxide-semiconductor MN0 is connected with the grid of the first N-type metal-oxide-semiconductor MN1；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the first N-type
The drain electrode of metal-oxide-semiconductor MN1 is connected with the grid of the second N-type metal-oxide-semiconductor MN2；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4, the second N-type metal-oxide-semiconductor
The drain electrode of MN2 is connected with the output end vo ut of amplifier, the source electrode of the 0th p-type metal-oxide-semiconductor MP0, the source electrode of the first p-type metal-oxide-semiconductor MP1,
The source electrode of the 4th p-type metal-oxide-semiconductor MP4 is connected with power vd D, the source electrode of the 0th N-type metal-oxide-semiconductor MN0, the source of the first N-type metal-oxide-semiconductor MN1
Pole, the source electrode of the second N-type metal-oxide-semiconductor MN2, the outflow end of current source I are connected with ground GND.
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| CN201210179256.4A CN102710129B (en) | 2012-05-30 | 2012-05-30 | High-precision DC/DC converter current limiting circuit |
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| CN201210179256.4A CN102710129B (en) | 2012-05-30 | 2012-05-30 | High-precision DC/DC converter current limiting circuit |
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| CN102710129B true CN102710129B (en) | 2017-02-08 |
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| JP2010154633A (en) * | 2008-12-25 | 2010-07-08 | Nanopower Solution Kk | Dc-dc conversion power supply |
| CN102290991A (en) * | 2011-05-27 | 2011-12-21 | 武汉大学 | Current model frequency compensating device of DC-DC (direct current-direct current) converter |
| CN202586736U (en) * | 2012-05-30 | 2012-12-05 | 西安航天民芯科技有限公司 | High-precision current limiting circuit of DC/DC (Direct Current/Direct Current) converter |
-
2012
- 2012-05-30 CN CN201210179256.4A patent/CN102710129B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2519284Y (en) * | 2001-10-11 | 2002-10-30 | 华为技术有限公司 | Mutual complementing differential peak value detecting circuit |
| CN1845431A (en) * | 2006-04-20 | 2006-10-11 | 南京航空航天大学 | Control circuit for carrying out current limitation on peak current controlled DC-DC transformer |
| JP2010154633A (en) * | 2008-12-25 | 2010-07-08 | Nanopower Solution Kk | Dc-dc conversion power supply |
| CN102290991A (en) * | 2011-05-27 | 2011-12-21 | 武汉大学 | Current model frequency compensating device of DC-DC (direct current-direct current) converter |
| CN202586736U (en) * | 2012-05-30 | 2012-12-05 | 西安航天民芯科技有限公司 | High-precision current limiting circuit of DC/DC (Direct Current/Direct Current) converter |
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| CN102710129A (en) | 2012-10-03 |
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