CN102709245A - Method for preparing double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor) - Google Patents

Method for preparing double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor) Download PDF

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CN102709245A
CN102709245A CN2012101360202A CN201210136020A CN102709245A CN 102709245 A CN102709245 A CN 102709245A CN 2012101360202 A CN2012101360202 A CN 2012101360202A CN 201210136020 A CN201210136020 A CN 201210136020A CN 102709245 A CN102709245 A CN 102709245A
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CN102709245B (en
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黄晓橹
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Shanghai Huali Microelectronics Corp
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Abstract

The invention provides a method for preparing a double-layer SOI (Silicon on Insulator) mixed crystal orientation rear grid type inverted mode SiNWFET (Silicon Nano Wire Field Effect Transistor). A PMOSFET (P-channel Metal-Oxide-Semiconductor Field Effect Transistor) adopts a surface crystal orientation silicon layer (110) and an NMOSFET (N-channel Metal-Oxide-Semiconductor Field Effect Transistor) adopts a surface crystal orientation silicon layer (100). In a low-temperature stripping technology, a crack tends to grow along with the increase of a crystal orientation (100), so that silicon layer stripping is easy to carry out along the crystal orientation (100) and a layer transferring process is convenient to realize.

Description

The method for preparing grid type inversion mode SiNWFET behind the double-deck SOI crystallographic orientation
Technical field
The present invention relates to the semiconductor field effect transistor technical field, relate in particular to a kind of processing step for preparing grid type inversion mode SiNWFET behind the double-deck SOI crystallographic orientation.
Background technology
Through dwindle transistorized size improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in the microelectronics industry development always.Current; The physical gate of field-effect transistor is long near 20nm; Gate medium also only has several oxygen atom bed thickness; Improve performance through the size of dwindling conventional field effect transistor and faced some difficulties, this mainly is because of short-channel effect under the small size and grid leakage current transistorized switch performance to be degenerated.
Nano-wire field effect transistor (NWFET, Nanowire MOSFET) is expected to address this problem.On the one hand; Little channel thickness and width make the grid of NWFET more approach the various piece of raceway groove; Help the enhancing of transistor gate modulation capability, and their mostly adopt and enclose the grid structure, grid is modulated raceway groove from a plurality of directions; Further the enhanced modulation ability is improved the subthreshold value characteristic.Therefore, NWFET can suppress short-channel effect well, makes transistor size be able to further dwindle.On the other hand, NWFET utilizes the rill road of self and encloses the grid structure and improve the grid modulation forces and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced impurity discrete distribution and Coulomb scattering in the raceway groove.For the 1-dimention nano wire channel, because quantum limitation effect, charge carrier so carrier transport receives surface scattering and channel laterally influence little, can obtain higher mobility away from surface distributed in the raceway groove.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Because Si material and technology are occupied dominant position in semi-conductor industry, compare the easier and current process compatible of the making of silicon nanowires field-effect transistor (SiNWFET) with other materials.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.Making for the Si nano wire; The former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technology; The latter is mainly based on gas-liquid-solid (VLS) growth mechanism of metal catalytic, in the growth course with catalyst granules as nucleating point.At present, the silicon nanowires of process route preparation from bottom to top not too is fit to the preparation of SiNWFET owing to its randomness, and the SiNW in the therefore present silicon nanowires field-effect transistor mainly is through top-down process route preparation.Simultaneously, existing nano-wire field effect transistor also has the defective of himself.
A kind of structural representation of composite material inversion mode cylinder all-around-gate CMOS field effect transistor is disclosed among the U.S. Pat 20110254101A1.Said all-around-gate CMOS field effect transistor is round by gate regions 500 ' full raceway groove 301 ', the 401 ' cross section that surrounds.
A kind of structural representation of hybrid orientation inversion mode all-around-gate CMOS field-effect transistor is disclosed among the U.S. Pat 20110254102A1.Said all-around-gate CMOS field effect transistor is a racetrack by gate regions 500 ' full raceway groove 301 ', the 401 ' cross section that surrounds.
The transistorized structural representation of a kind of composite material inversion mode all-around-gate CMOS field effect is disclosed among the U.S. Pat 20110248354A1.Said all-around-gate CMOS field effect transistor is a racetrack by gate regions 500 ' full raceway groove 301 ', the 401 ' cross section that surrounds.
All adopt the MOSFET of inversion mode crystallographic orientation in the above-mentioned open file; All there is following defective in it: (1) nmos area 300 ' and PMOS district 400 ' shared same gate regions 500 '; The CMOS structure of clamping type can only be realized, NMOS and PMOS isolating construction can't be realized; (2) nmos area 300 ' and PMOS district 400 ' shared same gate regions 500 ' can't carry out gate work-function adjusting and the adjusting of resistance rate respectively to NMOS and PMOS; (3) realizing carrying out the source respectively to NMOS and PMOS, to leak the technology difficulty of ion injection big.
Summary of the invention
The present invention be directed in the prior art; Conventional semiconductor nanowire MOS FET can't realize NMOS and PMOS isolating construction; Can't carry out gate work-function respectively to NMOS and PMOS and regulate with the resistance rate and regulate, and realize that carrying out the source respectively to NMOS and PMOS leaks defectives such as technology difficulty that ion injects is big a kind of SOI of preparation is provided the upward method of grid type inversion mode SiNWFET behind the bilayer isolation crystallographic orientation.
The present invention provides a kind of method for preparing grid type inversion mode SiNWFET behind the double-deck SOI crystallographic orientation to achieve these goals, comprises following sequential steps:
Step 1: the channel region N type ion that successively forms on SiGe layer, Si layer and SiGe layer and the soi wafer at the SOI top layer injects:
Step 2: device is carried out photoetching process, and etching forms the fin-shaped active area, utilizes the selective etch technology to remove the SiGe layer in the fin-shaped active area, forms the silicon nanowires of SiNWFET raceway groove;
Step 3: deposit dielectric layer on device, adopt cmp to remove unnecessary spacer medium material;
Step 4: the PMOS of lower floor is carried out injection of source-drain area ion and annealing,
Step 5: on the spacer medium layer above the silicon nanowires of SiNWFET raceway groove, carry out photoetching and selective etch and form gate trench, expose silicon nanowires in the said gate trench;
Step 6: device is carried out the gate oxidation layer process; At grid oxic horizon deposit grid material, adopt cmp to remove unnecessary grid material again, device is carried out metal, the semiconducting alloy PROCESS FOR TREATMENT formation SiNW of lower floor inversion mode PMOSFET structure;
Step 7: the ILD layer of the deposition PMOSFET of lower floor on device, at the ILD laminar surface, Si bonding pad and following has prepared has (110)/the support chip low-temperature bonding of < 110>SiNW PMOSFET handles, and makes to form one (110) surface orientation Si layer on the ILD layer;
Step 8: on the Si layer that last step forms, repeat above-mentioned steps 1 to 6 described step, form upper strata SiNW inversion mode NMOSFET structure, said Si layer selects for use P type ion to carry out the ion doping of raceway groove;
Step 9: draw the PMOSFET of lower floor and each port of upper strata NMOSFET through the metal interconnected technology in road, back.
In a preferred embodiment of the invention, be included in top layer silicon surface extension layer of surface crystal orientation SiGe or Ge layer in the wherein said step 1, adopt germanium oxidation concentration method that wafer is carried out oxidation processes and form the SiGe layer, remove the SiO on the SiGe layer 2Layer exposes the SiGe layer.
In a preferred embodiment of the invention, the SiGe layer in the wherein said removal fin-shaped active area adopts time normal pressure chemical vapour phase processes, with 600 ~ 800 ℃ H 2Carry out selective etch with the HCl mist, wherein the dividing potential drop of HCl is greater than 300 torr.
In a preferred embodiment of the invention, the cross sectional shape of the silicon nanowires of wherein said SiNWFET raceway groove is circular, horizontal racetrack or vertical racetrack.
In a preferred embodiment of the invention, wherein said grid oxic horizon process using furnace oxidation, quick oxidation or atomic layer deposition technology are at SiNW and substrate and source and drain areas surface formation SiO 2Perhaps SiON (adding nitrogen atmosphere) or high K medium layer are (like HfO 2, Al 2O 3, ZrO 2Perhaps its mixture etc.), perhaps their mixed layer.
In a preferred embodiment of the invention, wherein said grid material is selected polysilicon, amorphous silicon, metal oxide or its composition for use, and said metal oxide is the metal oxide of aluminium or titanium or tantalum.
In a preferred embodiment of the invention, each step is carried out under low temperature environment in the wherein said step 8.
In a preferred embodiment of the invention, wherein said ILD layer is SiO 2The low k silicon dioxide layer of the carbon containing of layer or microcellular structure.
Through grid type inversion mode SiNWFET behind the bilayer isolation crystallographic orientation of method formation PMOSFET of lower floor provided by the invention and upper strata NMOSFET structure; The first semiconductor nanowires MOSFET of formed double-deck isolation of semiconductor nanowire MOS FET and the second semiconductor nanowires MOSFET are separated through the spacer medium interlayer; Can fully independently carry out process debugging, and the device integrated level is high.Simultaneously, it is PMOSFET that the present invention adopts the first semiconductor nanowires MOSFET, and the second semiconductor nanowires MOSFET is the structural design of NMOSFET.PMOSFET adopts (110) surface orientation silicon layer among the present invention, and NMOSFET adopts (100) surface orientation silicon layer.In the low temperature lift-off technology, along with the pressure increase of hydrogen, the crack is more prone to the growth along (100) crystal orientation, therefore carries out silicon layer more easily along (100) crystal orientation and peels off, and has made things convenient for the layer transfer process realization.
Description of drawings
Fig. 1 (a) is the plan structure sketch map of the double-deck isolation of semiconductor nanowire MOS of the present invention FET.
Fig. 1 (b) is depicted as the sectional structure sketch map of Fig. 1 (a) along X-X ' direction.
Fig. 1 (c) is depicted as the sectional structure sketch map of Fig. 1 (a) along Y-Y ' direction.
Fig. 2 is the perspective view of the double-deck isolation of semiconductor nanowire MOS of the present invention FET.
Fig. 3 is the perspective view of the double-deck isolation of semiconductor nanowire MOS of the present invention FET through the formed complete field-effect transistor of follow-up semiconductor preparing process.
Fig. 4 is the structural representation behind the present invention the forms double-deck SiGe layer.
Fig. 5 (a) and Fig. 5 (b) are respectively the sectional structure sketch map along X-X ' direction and Y-Y ' direction after etching of the present invention is removed the SiGe layer in the fin-shaped Si active area.
Fig. 6 is SiNW schematic cross-section among the present invention.
Sectional structure sketch map after Fig. 7 (a) and Fig. 7 (b) are respectively deposit spacer medium layer among the present invention and remove unnecessary isolation dielectric material along X-X ' direction and Y-Y ' direction.
Fig. 8 is for carrying out source-drain area ion implantation technology sketch map to the PMOS of lower floor among the present invention.
Fig. 9 (a) and Fig. 9 (b) are respectively among the present invention the sectional structure sketch map along X-X ' direction and Y-Y ' direction that forms lower floor's silicon nanowires behind the gate trench.
Figure 10 (a) and Figure 10 (b) are respectively the sectional structure sketch map along X-X ' direction and Y-Y ' direction after cmp among the present invention removes unnecessary grid material.
The sectional structure sketch map along X-X ' direction and Y-Y ' direction of Figure 11 after for the ILD layer of the PMOSFET of deposit lower floor among the present invention.
Figure 12 has the process schematic representation of (110)/< 110>SiNW PMOSFET support chip low-temperature bonding for Si bonding pad among the present invention and preparation.
Figure 13 is the cross-sectional view after low-temperature bonding is accomplished among the present invention.
Figure 14 (a) and Figure 14 (b) are respectively the sectional structure sketch map along X-X ' direction and Y-Y ' direction behind the formation upper strata NMOSFET among the present invention.
Embodiment
The present invention provides grid type inversion mode SiNWFET preparation method behind a kind of double-deck SOI crystallographic orientation.Promptly the channel region of two-layer MOSFET is the silicon nanowires with different surfaces crystal orientation up and down.Because in the low temperature lift-off technology; Along with the increase of Hydrogen Vapor Pressure, the growth along (100) crystal orientation is tended in the crack more, therefore carries out silicon layer more easily along (100) crystal orientation and peels off; So adopt lower floor's PMOSFET+ upper strata NMOSFET pattern, realize to make things convenient for layer transfer process.
Theoretically, bilevel SiNWFET can adopt the silicon nanowires of any surface orientation, and according to people's such as Yang M achievement in research, the electron mobility of (100)/< 110>is maximum, and the hole mobility of (110)/< 110>is maximum.Therefore; Preferably, we are with the silicon nanowires of (100) surface orientation channel material as NMOSFET, and the channel direction of NMOSFET is < 110 >; With the silicon nanowires of (110) surface orientation channel material as PMOSFET, and the channel direction of PMOSFET is < 110 >.
By the technology contents, the structural feature that specify the invention, reached purpose and effect, will combine embodiment and conjunction with figs. to specify below.
Adopting top layer silicon is the soi wafer of (110) surface orientation silicon layer, carries out top layer Si Ge preparation earlier.SiGe or Ge layer in top layer silicon surface extension one deck (110) surface orientation.Utilize germanium oxidation concentration method, carry out oxidation processes at crystal column surface, at this moment, Ge can be concentrated to following Si layer downwards, make the Si layer become the SiGe layer, and the upper strata is SiO 2Layer, wet method is removed the SiO on surface 2Layer so just makes top layer silicon be converted into top layer germanium silicon.Once more, extension one deck Si layer and SiGe layer on top layer Si Ge layer, thereby the structure of formation SiGe layer, Si layer and SiGe layer, structure is as shown in Figure 4.In the process of the double-deck germanium silicon layer of preparation, can when the epitaxy Si layer, carry out N type ion doping, also can after forming double-deck germanium silicon layer, carry out N type ion doping.
Device is carried out optical lithography or electron beam lithography technology, and etching forms the fin-shaped active area.Utilize the selective etch technology to remove the SiGe layer in the fin-shaped Si active area, for example adopt 600 ~ 800 ℃ H 2With the HCl mist, utilize time normal pressure chemical gas phase etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300 Torr.Till SiGe layer between the Si active area of Y-Y ' direction is all removed totally, make the SiGe layer segment of X-X ' direction keep (this zone is source, drain region), form the silicon nanowires of SiNWFET raceway groove, structure is like Fig. 5 (a) with (b).Thermal oxidation technology is carried out oxidation to fin-shaped active area and substrate and source and drain areas surface, and the controlled oxidation time, wet processing is removed fin-shaped active area and the substrate SiO surperficial with source and drain areas then 2, at this moment the fin-shaped active area possibly form circle, horizontal racetrack or vertical racetrack along the sectional view of Y-Y ' direction, and cross section is as shown in Figure 6, thereby forms follow-up silicon nanowires as the SiNWFET raceway groove.
Like Fig. 7 (a) with structure (b), the deposit dielectric layer is (like SiO on device 2), adopt cmp (CMP) to remove unnecessary spacer medium material.As shown in Figure 8, the PMOS of lower floor is carried out the source-drain area ion inject and annealing process.On the spacer medium layer above the silicon nanowires of SiNWFET raceway groove, carry out photoetching and selective etch and form gate trench, expose silicon nanowires in the gate trench, like Fig. 9 (a) with (b) shown in the generalized section of silicon nanowires.
Like Figure 10 (a) with (b), device is being carried out the gate oxidation layer process, as adopting furnace oxidation (Furnace Oxidation), rapid thermal oxidation (RTO), ald (ALD), at SiNW and substrate and source and drain areas surface formation SiO 2Perhaps SiON (adding nitrogen atmosphere) or high K medium layer are (like HfO 2, Al 2O 3, ZrO 2Perhaps its mixture etc.), perhaps their mixed layer.Deposit grid material on grid oxic horizon can be polysilicon, amorphous silicon, metallic compound (being preferably the metallic compound of aluminium or titanium or tantalum) or its combination again.Adopt cmp to remove unnecessary grid material.Device is carried out metal, the semiconducting alloy PROCESS FOR TREATMENT formation MOSFET of lower floor, be (110)/< 110>SiNW inversion mode PMOSFET structure.
Shown in figure 11, the ILD layer of the deposition PMOSFET of lower floor can be the SiO2 layer on device, in order to reduce the capacitively coupled effect between the device layer up and down, also can hang down the k silicon dioxide layer for the carbon containing with microcellular structure.Wherein, in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness after CMP, preferably, can adopt FACMP (Fixed Abrasive CMP), make surface roughness less than 10nm.
Shown in figure 12; At the ILD laminar surface; Si bonding pad and following has prepared has (110)/and the support chip low-temperature bonding of < 110>SiNW PMOSFET handles; Make to form one (100) surface orientation Si layer on the ILD layer, this technology detailed process sees that application number is 201210090253.3 Chinese patent, and the structure after low-temperature bonding is finished dealing with is shown in figure 13.
Before carrying out once more on the Si layer that forms from forming the process of SiGe layer to metal, semiconducting alloy PROCESS FOR TREATMENT, thereby be formed into upper strata SiNW inversion mode NMOSFET structure.Wherein be that with step difference before the Si layer selects for use P type ion to carry out the ion doping of raceway groove.
In addition, because the PMOSFET of lower floor prepared completion, in order not influence the performance of layer device and metal, semiconducting alloy down, follow-up upper strata NMOSFET prepares in the process must adopt low temperature method,＜400 ℃ of general requirements.Adopting low-temperature epitaxy technology and germanium oxidation concentration method, make original silicon layer be converted into the germanium silicon layer.Low-temperature epitaxy one deck Si layer and SiGe layer in order to reduce follow-up heat budget as far as possible, directly carry out raceway groove P type ion doping when the epitaxy Si layer again, do not need the follow-up channel ion injection technology of carrying out again like this, form structure like Figure 14 (a) with (b).
After forming upper strata inversion mode NMOSFET structure, draw the PMOSFET of lower floor and each port of upper strata NMOSFET through the metal interconnected technology in road, back.
See also Fig. 1 (a), Fig. 1 (b), Fig. 1 (c), Fig. 1 (a) is depicted as the plan structure sketch map of the double-deck isolation of semiconductor nanowire MOS FET of the inventive method formation.Fig. 1 (b) is depicted as the sectional structure sketch map of Fig. 1 (a) along X-X ' direction.Fig. 1 (c) is depicted as the sectional structure sketch map of Fig. 1 (a) along Y-Y ' direction.Said double-deck isolation of semiconductor nanowire MOS FET 1 comprises Semiconductor substrate 10; The first semiconductor nanowires MOSFET 11; The second semiconductor nanowires MOSFET 12; Be arranged on the spacer medium layer 13 between said first semiconductor nanowires MOSFET 11 and the said second semiconductor nanowires MOSFET12; Be arranged on the oxygen buried layer 14 between said first semiconductor nanowires MOSFET 11 and the said Semiconductor substrate 10; Be arranged on first insulating medium layer 113 between first source area 110, first drain region 111 and the first grid polar region 112 of the said first semiconductor nanowires MOSFET 11; Be arranged on second insulating medium layer 123 between second source area 120, second drain region 121 and the second grid district 122 of the said second semiconductor nanowires MOSFET 12; Be arranged between between said spacer medium layer 13 and the said oxygen buried layer 14 and the 3rd insulating medium layer 114 that is positioned at the said first semiconductor nanowires MOSFET, 11 1 sides and links to each other with said first source area 110, first drain region 111 and first grid polar region 112; Be towards the 4th insulating medium layer 124 that is provided with and is connected with said the 3rd insulating medium layer 114, and be separately positioned on first conductive layer 115 between said spacer medium layer 13 and said first source area 110, first drain region 111 and the first grid polar region 112 and be separately positioned on second conductive layer 125 that differs from said spacer medium layer 13 1 side in second source area 120, second drain region 121 and second grid district 122 with said second source area 120, second drain region 121 and second grid district 122.
In conjunction with consulting Fig. 1 (a), Fig. 1 (b) and Fig. 1 (c), the perspective view for the double-deck isolation of semiconductor nanowire MOS of the present invention FET 1 shown in Figure 2.The first semiconductor nanowires MOSFET 11 further comprise laterally through said first grid polar region 112 and be arranged on said first source area 110 with said first drain region 111 between first semiconductor nanowires 116, and ring wraps and is arranged on said first semiconductor nanowires, 116 outsides and the first grid oxide layer 117 between said first semiconductor nanowires 116 and said first grid polar region 112.
The second semiconductor nanowires MOSFET 12 of the double-deck isolation of semiconductor nanowire MOS of the present invention FET 1 further comprise laterally through said second grid district 122 and be arranged on said second source area 120 with said second drain region 121 between second semiconductor nanowires 126, and ring wraps and is arranged on said second semiconductor nanowires, 126 outsides and second gate oxide 127 between said second semiconductor nanowires 126 and said second grid district 122.Said first semiconductor nanowires 116 is spatially stacked with said second semiconductor nanowires 126, and the cross section structure with circle, horizontal track shape or vertical racetrack.
First source area 110, first drain region 111 perpendicular to the width of said first semiconductor nanowires 116 diameter greater than first semiconductor nanowires 116; Said second source area 120, second drain region 121 perpendicular to the width of second semiconductor nanowires 126 diameter greater than second semiconductor nanowires 126, so the double-deck isolation of semiconductor nanowire MOS of the present invention FET 1 be when overlooking in the middle of the roomy fin-shaped in thin two ends.Because the first semiconductor nanowires MOSFET 11 is PMOSFET, the second semiconductor nanowires MOSFET 12 is NMOSFET, and PMOSFET adopts (110) surface orientation silicon layer among the present invention, and NMOSFET adopts (100) surface orientation silicon layer.Because in the low temperature lift-off technology; Increase along with Hydrogen Vapor Pressure; The growth along (100) crystal orientation is tended in the crack more, therefore carries out silicon layer more easily along (100) crystal orientation and peels off, so lower floor's PMOSFET+ upper strata NMOSFET pattern can make things convenient for layer transfer process to realize.
First insulating medium layer 113 is being set to avoid the phase mutual interference between first source area 110, first drain region 111 and the first grid polar region 112 between first source area 110, first drain region 111 and the first grid polar region 112.Second insulating medium layer 123 is being set to avoid the phase mutual interference between second source area 120, second drain region 121 and the second grid district 122 between second source area 120, second drain region 121 and the second grid district 122.Between the first semiconductor nanowires MOSFET 11 and Semiconductor substrate 10, oxygen buried layer 14 is set, the said first semiconductor nanowires MOSFET 11 is isolated with said Semiconductor substrate 10, effectively reduce leakage current, thereby improve device performance.
Perspective view for the formed complete field-effect transistor of the follow-up semiconductor preparing process of process shown in Figure 3.The first semiconductor nanowires MOSFET 11 can draw electrode through the 4th insulating medium layer 124 from first conductive layer 115, to form the first source electrode 118a, first drain electrode 118b and the first grid 119 respectively.The said second semiconductor nanowires MOSFET 12 can draw electrode through second conductive layer 125 that is positioned in second source area 120, second drain region 121 and the second grid district 122, to form the second source electrode 128a, second drain electrode 128b and the second grid 129 respectively.
In sum, the first semiconductor nanowires MOSFET and the second semiconductor nanowires MOSFET of the double-deck isolation of semiconductor nanowire MOS of the present invention FET are separated through the spacer medium interlayer, can fully independently carry out process debugging, and the device integrated level are high.Simultaneously, it is PMOSFET that the present invention adopts the first semiconductor nanowires MOSFET, and the second semiconductor nanowires MOSFET is that the structural design of NMOSFET can make things convenient for layer transfer process to realize, and is applicable to forward position nano-device technical field.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims (9)

1. a method for preparing grid type inversion mode SiNWFET behind the double-deck SOI crystallographic orientation is characterized in that, comprises following sequential steps:
Step 1: the channel region N type ion that successively forms on SiGe layer, Si layer and SiGe layer and the soi wafer at the SOI top layer injects:
Step 2: device is carried out photoetching process, and etching forms the fin-shaped active area, removes the SiGe layer in the fin-shaped active area, forms the silicon nanowires of SiNWFET raceway groove;
Step 3: deposit dielectric layer on device;
Step 4: the PMOS of lower floor is carried out injection of source-drain area ion and annealing,
Step 5: on the spacer medium layer above the silicon nanowires of SiNWFET raceway groove, carry out photoetching and selective etch and form gate trench, expose silicon nanowires in the said gate trench;
Step 6: device is being carried out the gate oxidation layer process, at SiNW and substrate and source and drain areas surface formation SiO 2Or SiON or high K medium layer or its mixed layer; At grid oxic horizon deposit grid material, device is carried out metal, the semiconducting alloy PROCESS FOR TREATMENT formation SiNW of lower floor inversion mode PMOSFET structure again;
Step 7: the ILD layer of the deposition PMOSFET of lower floor on device, at the ILD laminar surface, Si bonding pad and following has prepared has (110)/the support chip low-temperature bonding of < 110>SiNW PMOSFET handles, and makes to form one (100) surface orientation Si layer on the ILD layer;
Step 8: on the Si layer that last step forms, repeat above-mentioned steps 1 to 6 described step, form upper strata SiNW inversion mode NMOSFET structure, said Si layer selects for use P type ion to carry out the ion doping of raceway groove;
Step 9: draw the PMOSFET of lower floor and each port of upper strata NMOSFET through the metal interconnected technology in road, back.
2. method according to claim 1 is characterized in that, is included in top layer silicon surface extension one deck (110) surface orientation SiGe or Ge layer in the said step 1, adopts germanium oxidation concentration method that wafer is carried out oxidation processes and forms the SiGe layer, removes the SiO on the SiGe layer 2Layer exposes the SiGe layer.
3. method according to claim 1 is characterized in that, the SiGe layer in the said removal fin-shaped active area adopts time normal pressure chemical vapour phase processes, with 600 ~ 800 ℃ H 2Carry out selective etch with the HCl mist, wherein the dividing potential drop of HCl is greater than 300 torr.
4. method according to claim 1 is characterized in that, the cross sectional shape of the silicon nanowires of said SiNWFET raceway groove is circular, horizontal racetrack or vertical racetrack.
5. method according to claim 1 is characterized in that, said grid oxic horizon process using furnace oxidation, quick oxidation or atomic layer deposition technology.
6. method according to claim 5 is characterized in that, said high K medium layer is HfO 2, Al 2O 3, ZrO 2Or its mixture material.
7. method according to claim 1 is characterized in that, said grid material is selected polysilicon, amorphous silicon, metal oxide or its composition for use, and said metal oxide is the metal oxide of aluminium or titanium or tantalum.
8. method according to claim 1 is characterized in that, each step is carried out under low temperature environment in the said step 8.
9. method according to claim 1 is characterized in that, said ILD layer is SiO 2The low k silicon dioxide layer of the carbon containing of layer or microcellular structure.
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