CN102683283B - Method for preparing double-layer isolation mixed crystal orientation strain silicon nanowire complementary metal oxide semiconductor (CMOS) - Google Patents
Method for preparing double-layer isolation mixed crystal orientation strain silicon nanowire complementary metal oxide semiconductor (CMOS) Download PDFInfo
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Abstract
The invention provides a method for preparing a double-layer isolation mixed crystal orientation strain silicon nanowire complementary metal oxide semiconductor (CMOS). A channel region where an upper metal oxide semiconductor field effect transistor (MOSFET) and a lower MOSFET are formed is provided with silicon nanowires (SiNW) with different surface crystal orientations, wherein the lower MOSFET is a P-channel mental oxide semiconductor field effect transistor (PMOSFET) with pressure stress in the SiNW along a source and drain direction, and the upper MOSFET is an N-channel mental oxide semiconductor field effect transistor (NMOSFET) with tensile stress in the SiNW along the source and drain direction.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to a kind of double-deck isolation mixed crystal orientation strain silicon nanowires CMOS preparation method.
Background technology
By dwindling transistorized size, improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in microelectronics industry development always.The long 20nm that approached of physical gate of current field-effect transistor, gate medium also only has several oxygen atom bed thickness, by dwindling the size of conventional field effect transistor, improve performance and faced some difficulties, this is mainly because short-channel effect and grid leakage current degenerate transistorized switch performance under small size.
Nano-wire field effect transistor (NWFET, Nanowire MOSFET) is expected to address this problem.On the one hand, little channel thickness and width make the grid of NWFET closer to the various piece of raceway groove, contribute to the enhancing of transistor gate modulation capability, and they mostly adopt and enclose grid structure, grid is modulated raceway groove from multiple directions, further enhanced modulation ability, improves Sub-Threshold Characteristic.Therefore, NWFET can suppress short-channel effect well, and transistor size is further dwindled.On the other hand, NWFET utilizes the rill road of self and encloses grid Structure Improvement grid modulation power and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced the discrete distribution of impurity and Coulomb scattering in raceway groove.For 1-dimention nano wire channel, due to quantum limitation effect, in raceway groove charge carrier away from surface distributed, therefore carrier transport be subject to surface scattering and channel laterally electric field influence little, can obtain higher mobility.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Due to Si material and technique, in semi-conductor industry, occupy dominant position, compare with other materials, the making of silicon nanowires field-effect transistor (SiNWFET) more easily with current process compatible.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.Making for Si nano wire, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technique, the latter is gas-liquid-solid (VLS) growth mechanism based on metal catalytic mainly, usings catalyst granules as nucleating point in growth course.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of SiNWFET due to its randomness, and therefore the SiNW in current silicon nanowires field-effect transistor is prepared by top-down process route.
Current, in advanced semiconductor device manufacture, introduce strain engineering very general, the MOSFET that is <110> for channel direction, when channel direction has tensile stress, can effectively increase the current driving ability of NMOSFET, and when channel direction has compression, can effectively increase the current driving ability of PMOSFET.
As a same reason, for state-of-the-art semiconductor nanowires field-effect transistor (Nanowire Field Effect Transistor, NWFET), if introduce strain engineering in its nanowire length direction (being channel direction), also the current driving ability of NWFET will be increased greatly.The people such as Masumi Saitoh have reported in for <110>NW nFET, to introduce after stress engineering and (have adopted stress memory technique in IEDM2010 paper " Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement ", SMT), current driving ability has increased 58%.
All-around-gate crystallographic orientation cmos fet transistor arrangement is disclosed in US Patent No. 20110254058A1, US20110254099A1, US20110254101A1, US20110254013A1, US20110254102A1, US20110254100A1, US20110248354A1, but they have following common defects: NMOS and PMOS to share same grid layer, can only realize the CMOS structure of clamping type, cannot realize NMOS and PMOS isolating construction, and in actual cmos circuit, there is a large amount of NMOS and PMOS isolating construction.NMOS and PMOS share same grid layer, cannot carry out respectively gate work-function adjusting and the adjusting of resistance rate for NMOS and PMOS.In technique, be difficult to realize for NMOS and PMOS and carry out respectively source leakage Implantation.
Summary of the invention
The present invention is directed to the defect existing in prior art, propose a kind of novel bilayer isolation mixed crystal orientation strain silicon nanowires CMOS preparation method, effectively overcoming prior art defect simultaneously, can keep again same high device integration density.In addition, can effectively increase carrier mobility, and then increase cmos current driving force.
To achieve these goals, the invention provides a kind of double-deck isolation mixed crystal orientation strain silicon nanowires CMOS preparation method, comprise following sequential steps:
Step 1: top layer silicon is contained to soi wafer that foreign ion and surface orientation are (110) and carry out the region that photoetching and etching define silicon nanowires field-effect transistor, till being etched to and exposing oxygen buried layer, remove the photoresistance and/or the hard mask that in photoetching and etching process, stay.
Step 2: employing wet etching is removed the part oxygen buried layer below SOI top layer silicon chip, makes below, silicon nanowires region have cavity layer, and wherein leakage pad position in top silicon layer source is connected with oxygen buried layer below.
Step 3: adopt thermal oxidation technology and wet-etching technology to remove the oxide layer on surface, silicon nanowires district in top silicon layer, preparation forms silicon nanowires, deposit insulating medium layer on device, makes to fill dielectric in the layer of cavity, silicon wafer layer below; Insulating medium layer is polished, make the source of NWFET leak the insulating medium layer that liner top forms 20 ~ 200nm.
Step 4: insulating medium layer is carried out to photoetching and selective etch, and etching is removed the dielectric of the area of grid of NWFET, exposes SiNW, till being etched to and exposing oxygen buried layer.
Step 5: device is carried out to gate oxidation layer process, at SiNW and substrate and source and drain areas surface formation SiO
2, SiON, Si
3n
4, high K medium layer or its mixing grid oxide layer; Deposit grid material on grid oxic horizon, grinds and removes unnecessary grid material again.
Step 6: device is carried out to photoetching and etching, pad regions is leaked in source etched open, be etched to and leave bottom silicon thin layer; Remove photoresistance, in the source etching, leak cushion region selective epitaxial growth SiGe, carry out source simultaneously and leak unit's position doping.
Step 7: device is carried out to source and leak annealing process and autoregistration metallic silicon/germanium-silicon alloy technique, thereby prepare the surface orientation strained silicon nano wire PMOSFET of lower floor (110), deposit insulating medium layer with isolation PMOSFET and NMOSFET at device surface.
Step 8: (100) surface orientation silicon and the support chip that has been prepared with (110)/<110> SiNW PMOSFET are carried out to low-temperature bonding processing, make to form (100) silicon layer on insulating medium layer, if at this moment upper strata silicon layer thickness not, can carry out low-temperature epitaxy growth silicon layer to increase upper strata silicon layer thickness.
Step 9: repeat the step described in above-mentioned steps 1 to 7 on the silicon layer forming in step 8, form upper strata (100) surface orientation strained silicon nano wire NMOSFET, cushion region selective epitaxial growth SiC is leaked in source in the NMOSFET process of upper strata.
Step 10: draw the PMOSFET of lower floor and each port of upper strata NMOSFET by the metal interconnected technique in rear road.
In a preferred embodiment provided by the invention, the soi wafer that described top layer contains foreign ion is selected to soi wafer is carried out Implantation formation or form foreign ion in forming soi wafer process.
In a preferred embodiment provided by the invention, the cross sectional shape of described silicon nanowires is circular, horizontal racetrack or longitudinal racetrack.
In a preferred embodiment provided by the invention, in the described PMOSFET of lower floor preparation process, the chemical mol ratio of the Ge in epitaxial growth SiGe is 1% ~ 100%, and the chemical mol ratio of the Ge in preferred epitaxial growth SiGe is 10 ~ 50%.
In a preferred embodiment provided by the invention, in the described PMOSFET of lower floor preparation process, B, BF, BF are selected in the doping of leakage one's own department or unit, source
2or its hybrid ionic.
In a preferred embodiment provided by the invention, in the NMOSFET preparation process of described upper strata, the chemical mol ratio of the C in epitaxial growth SiC is 0.01 ~ 10%.The chemical mol ratio of C in preferred epitaxial growth SiC is 0.1 ~ 5%.
In a preferred embodiment provided by the invention, in the NMOSFET preparation process of described upper strata, P, As or its hybrid ionic are selected in the doping of leakage one's own department or unit, source.
In a preferred embodiment provided by the invention, in described step 9, each step is carried out being less than under the environment of 500 ℃.
In a preferred embodiment provided by the invention, described high K medium layer is HfO
2, ZrO
2, La
2o
3, Al
2o
3, TiO
2, SrTiO
3, LaAlO
3, Y
2o
3, HfO
xn
y, ZrO
xn
y, La
2o
xn
y, Al
2o
xn
y, TiO
xn
y, SrTiO
xn
y, LaAlO
xn
y, Y
2o
xn
ya kind of or composition material.
The invention provides a kind of double-deck isolation mixed crystal orientation strain silicon nanowires CMOS preparation method, the channel region that forms upper and lower two-layer MOSFET is the silicon nanowires with different surfaces crystal orientation, and wherein the MOSFET of lower floor is PMOSFET, and upper strata MOSFET is NMOSFET.Owing to introducing stress mechanism, in the raceway groove of the PMOSFET of lower floor, along source, leak direction and introduce compression, thereby increase the mobility in PMOSFET charge carrier hole; In the raceway groove of upper strata NMOSFET, along source, leak direction and introduce tensile stress, thereby increase the mobility of NMOSFET carrier electrons.Owing to introducing stress mechanism, effectively increase the current driving ability of CMOS.
Accompanying drawing explanation
Fig. 1 is the soi wafer structural profile schematic diagram that preparation is used.
Fig. 2 (a) and Fig. 2 (b) are vertical view and the profiles of preparing device architecture after silicon nanowires in the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS.
Fig. 3 is SiNW schematic cross-section in the present invention.
Fig. 4 is that in the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS, cavity, silicon layer below layer is filled the structural profile schematic diagram after dielectric.
Fig. 5 (a) and Fig. 5 (b) are vertical view and the profiles that dielectric that in the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS, etching is removed area of grid exposes device after SiNW.
Fig. 6 (a) and Fig. 6 (b) be in the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS in groove the vertical view of device and profile after deposition of gate material.
Fig. 7 has deposited between levels the structural profile schematic diagram of device after spacer medium layer in the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS.
Fig. 8 be in the present invention Si bonding pad be prepared with the technique generalized section that (110)/<110> SiNW PMOSFET support chip carries out low-temperature bonding.
Fig. 9 is the cross-section structure generalized section of low-temperature bonding after completing in the present invention.
Figure 10 is the cross-section structure generalized section forming in the present invention after the NMOSFET of upper strata.
Figure 11 (a) and Figure 11 (b) are that after completing in the present invention, the metal interconnected technique in road is drawn the sectional structure schematic diagram along X-X ' direction and Y-Y ' direction after the PMOSFET of lower floor and each port of upper strata NMOSFET.
Figure 12 is the plan structure schematic diagram of the double-deck isolation of the present invention mixed crystal orientation strain silicon nanowires CMOS.
Embodiment
The invention provides a kind of double-deck isolation mixed crystal orientation strain silicon nanowires CMOS preparation method.The channel region that is upper and lower two-layer MOSFET is the silicon nanowires with different surfaces crystal orientation.Wherein, the MOSFET of lower floor can be PMOSFET, and upper strata MOSFET can be NMOSFET.In the raceway groove of the PMOSFET of lower floor, along source, leak direction and introduce compression, thereby increase the mobility in PMOSFET charge carrier hole; In the raceway groove of upper strata NMOSFET, along source, leak direction and introduce tensile stress, thereby increase the mobility of NMOSFET carrier electrons.By the introducing of stress mechanism, effectively increase the current driving ability of CMOS.
Theoretically, bilevel SiNWFET can adopt the silicon nanowires of any surface orientation, according to the people's such as Yang M achievement in research, (100) electron mobility of/<110> is maximum, and the hole mobility of (110)/<110> is maximum.Therefore, preferably, we using the silicon nanowires of (100) surface orientation as the channel material of NMOSFET, and the channel direction of NMOSFET is <110>, using the silicon nanowires of (110) surface orientation as the channel material of PMOSFET, and the channel direction of PMOSFET is <110>.
By describe in detail the invention technology contents, structural feature, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.
As shown in Figure 1, the soi wafer of selecting top layer to contain foreign ion, wherein top layer silicon is (110) surface orientation, and oxygen buried layer thickness is 10nm ~ 1000nm, and top silicon layer thickness is 10nm ~ 200nm.Prepare inversion mode PMOSFET, channel dopant ion is donor impurity, prepares accumulation pattern PMOSFET, and channel dopant ion is acceptor impurity.The soi wafer that top layer contains foreign ion can be by the original foreign ion that comprises in Implantation or top silicon layer, as the channel doping ion of follow-up NWFET.
The soi wafer that top layer is contained to foreign ion carries out photoetching and etching (can adopt PR mask, also can adopt Hard mask) define the region of silicon nanowires field-effect transistor, in the middle of forming, be silicon nanowires region, liner (Pad) is leaked in the source that both sides are NWFET.Till being etched to and exposing oxygen buried layer, can fall part oxygen buried layer by over etching.Remove the photoresistance and/or the hard mask that in photoetching and etching process, stay.
Adopt wet etching to remove the part oxygen buried layer below silicon nanowires region in SOI top layer silicon, make silicon wafer layer below have cavity layer, wherein leakage pad position in silicon wafer layer source is connected with oxygen buried layer below.
Adopt thermal oxidation technology and wet-etching technology to remove the oxide layer of silicon nanowires area surfaces, preparation forms silicon nanowires, and concrete structure is as shown in Fig. 2 (a) and Fig. 2 (b).According to the difference of silicon nanowires region etching width and thickness, the cross sectional shape of the silicon nanowires that forms is also different, has circle, laterally track type and longitudinal three kinds of track types, and concrete structure as shown in Figure 3.
On device, deposit insulating medium layer (as SiO
2layer), make the cavity layer of silicon layer below fill dielectric, CMP polishes insulating medium layer, and making the dielectric layer thickness of the leakage liner top, source of NWFET is 10nm ~ 2000nm, forms structure as shown in Figure 4.
As shown in Fig. 5 (a) and Fig. 5 (b), to insulating medium layer carry out photoetching, selective etch (can adopt PR mask, also can adopt Hard mask) by the area of grid etching of NWFET out, etch away the dielectric of area of grid, expose SiNW, and till etching into oxygen buried layer always.
Device being carried out to grid oxygen technique, can prepare SiO by thermal oxidation or depositing operation
2or SiON or Si
3n
4or the grid oxide layer of preparing hafnium or its combination by depositing operation, wherein, hafnium can be HfO
2, ZrO
2, La
2o
3, Al
2o
3, TiO
2, SrTiO
3, LaAlO
3, Y
2o
3, HfO
xn
y, ZrO
xn
y, La
2o
xn
y, Al
2o
xn
y, TiO
xn
y, SrTiO
xn
y, LaAlO
xn
y, Y
2o
xn
ya kind of or composition material.Deposition of gate material on grid oxic horizon again, grid material can be polysilicon, amorphous silicon, metal or its combination.Adopt CMP to grind and remove unnecessary grid material, form structure as shown in Fig. 6 (a) and Fig. 6 (b).
Device is carried out to photoetching, etching, and that pad regions is leaked in source is etched open.Can adopt Hard mask, preferably, adopt Si
3n
4, SiON, a kind of or its combination in TiN.Be etched to and leave bottom silicon thin layer; Inculating crystal layer as follow-up epitaxy Si Ge.
Remove photoresistance, in the source etching, leak cushion region selective epitaxial growth (SEG, Selective Epitaxial Growth) SiGe, wherein the chemical mol ratio of Ge is 1% ~ 100%, preferably, is 10% ~ 50%.Meanwhile, carry out source leakage in-situ doped, preferably, doping B, BF, BF
2ion.If grid material adopts polysilicon or amorphous silicon, must retain Hard mask to avoid in area of grid generation epitaxial growth in this step, if grid material adopts metal, before this step, can remove Hard mask.Because this its preparation process makes to have had between source-drain area and grid dielectric isolation, and ultimate source drain region and top, gate regions be same plane, therefore do not need grid curb wall technique, simplified technological process.If last step is to retain Hard mask, at this moment removes and carry out source after Hard mask and leak annealing process.
Device is carried out to autoregistration metallic silicon/germanium-silicon alloy technique, complete the preparation of the surface orientation strained silicon nano wire PMOSFET of lower floor (110).Because source and drain areas adopts e-SiGe, they have action of compressive stress to channel region along channel direction, can effectively increase hole mobility, and then increase PMOSFET current driving ability.
At device surface, deposit dielectric (as SiO
2), to isolate NMOSFET and the PMOSFET of upper strata and lower floor, form structure as shown in Figure 7.
As shown in Figure 8 and Figure 9, (100) surface orientation silicon and the support chip that has been prepared with (110)/<110> SiNW PMOSFET are carried out to low-temperature bonding processing, make to form (100) silicon layer on insulating medium layer, if at this moment upper strata silicon layer thickness not, can carry out low-temperature epitaxy growth silicon layer to increase upper strata silicon layer thickness.Wherein, low-temperature epitaxy (100) silicon layer be can carry out in-situ doped, as the channel doping ion of follow-up NMOSFET.
Because the PMOSFET of lower floor has been prepared, in order not affect the performance of lower layer device and metallic silicon alloy, in the NMOSFET preparation process of follow-up upper strata, must adopt low temperature method, General Requirements is lower than carrying out under 500 ℃ of environment.Upper strata (100) silicon layer of preparing based on above-mentioned low-temperature bonding technique, preparation upper strata strained silicon nano wire NMOSFET.Technological process and the PMOSFET of lower floor prepare basic identical, do not repeat here.Wherein, leak cushion region selective epitaxial growth SiC in the source etching, wherein the chemical mol ratio of C is 0.01% ~ 10%, preferably, is 0.1% ~ 5%.Meanwhile, carry out source leakage in-situ doped, preferred doping P, As ion.
Leaking in impurity heat treatment for source, due to the requirement to lower layer device temperature control, preferably adopt Laser Anneal method, can realize the local Anneal of layer device, and can not have influence on the performance of lower layer device.
Complete after autoregistration metallic silicon alloy technique, prepared by upper strata (100) surface orientation strained silicon nano wire NMOSFET, form structure as shown in figure 10.Because source and drain areas adopts e-SiC, they have tensile stress effect to channel region along channel direction, can effectively increase electron mobility, and then increase NMOSFET current driving ability.
By the metal interconnected technique in rear road, draw the PMOSFET of lower floor and each port of upper strata NMOSFET, cross-section structure is as shown in Figure 11 (a) and Figure 11 (b).Figure 12 is bilayer after having prepared isolation mixed crystal orientation strain silicon nanowires CMOS structure schematic top plan view, wherein the SiGe drain region of the SiGe source region of the PMOSFET of 110Wei lower floor, the PMOSFET of 111Wei lower floor, the PMOSFET of 112Wei lower floor grid layer, 120 be upper strata NMOSFET SiC source region, 121 for the SiC drain region of upper strata NMOSFET, 122 be that upper strata NMOSFET grid layer, 126 is double stacked SiNW fin-shaped active area.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (8)
1. a double-deck isolation mixed crystal orientation strain silicon nanowires CMOS preparation method, is characterized in that, comprises following sequential steps:
Step 1: top layer silicon is contained to soi wafer that foreign ion and surface orientation are (110) and carry out the region that photoetching and etching define silicon nanowires field-effect transistor, till being etched to and exposing oxygen buried layer, remove the photoresistance and/or the hard mask that in photoetching and etching process, stay;
Step 2: employing wet etching is removed the part oxygen buried layer below SOI top layer silicon chip, makes below, silicon nanowires region have cavity layer, and wherein leakage pad position in top silicon layer source is connected with oxygen buried layer below;
Step 3: adopt thermal oxidation technology and wet-etching technology to remove the oxide layer on surface, silicon nanowires district in top silicon layer, preparation forms silicon nanowires, deposit insulating medium layer on device, makes to fill dielectric in the layer of cavity, silicon wafer layer below; Insulating medium layer is polished, make the source of NWFET leak the insulating medium layer that liner top forms 20～200nm;
Step 4: insulating medium layer is carried out to photoetching and selective etch, and etching is removed the dielectric of the area of grid of NWFET, exposes SiNW, till being etched to and exposing oxygen buried layer;
Step 5: device is carried out to gate oxidation layer process, at SiNW and substrate and source and drain areas surface formation SiO
2, SiON, Si
3n
4, high K medium layer or its mixing grid oxide layer; Deposit grid material on grid oxic horizon, grinds and removes unnecessary grid material again;
Step 6: device is carried out to photoetching and etching, pad regions is leaked in source etched open, be etched to and leave bottom silicon thin layer; Remove photoresistance, in the source etching, leak cushion region selective epitaxial growth SiGe, carry out source simultaneously and leak unit's position doping;
Step 7: device is carried out to source and leak annealing process and autoregistration metallic silicon/germanium-silicon alloy technique, thereby prepare the surface orientation strained silicon nano wire PMOSFET of lower floor (110), deposit insulating medium layer with isolation PMOSFET and NMOSFET at device surface;
Step 8: (100) surface orientation silicon and the support chip that has been prepared with (110)/<110>SiNW PMOSFET are carried out to low-temperature bonding processing, make to form on insulating medium layer (100) silicon layer;
Step 9: repeat the step described in above-mentioned steps 1 to 7 on the silicon layer forming in step 8, form upper strata (100) surface orientation strained silicon nano wire NMOSFET, cushion region selective epitaxial growth SiC is leaked in source in the NMOSFET process of upper strata;
Step 10: draw the PMOSFET of lower floor and each port of upper strata NMOSFET by the metal interconnected technique in rear road;
Wherein, described high K medium layer is HfO
2, ZrO
2, La
2o
3, Al
2o
3, TiO
2, SrTiO
3, LaAlO
3, Y
2o
3, HfO
xn
y, ZrO
xn
y, La
2o
xn
y, Al
2o
xn
y, TiO
xn
y, SrTiO
xn
y, LaAlO
xn
y, Y
2o
xn
ya kind of or composition material.
2. preparation method according to claim 1, is characterized in that, the soi wafer that described top layer contains foreign ion is selected to soi wafer is carried out Implantation formation or form foreign ion in forming soi wafer process.
3. preparation method according to claim 1, is characterized in that, the cross sectional shape of described silicon nanowires is circular, horizontal racetrack or longitudinal racetrack.
4. preparation method according to claim 1, is characterized in that, in the described PMOSFET of lower floor preparation process, the chemical mol ratio of the Ge in epitaxial growth SiGe is 1～100%.
5. preparation method according to claim 1, is characterized in that, in the described PMOSFET of lower floor preparation process, B, BF, BF are selected in the doping of leakage one's own department or unit, source
2or its hybrid ionic.
6. preparation method according to claim 1, is characterized in that, in the NMOSFET preparation process of described upper strata, the chemical mol ratio of the C in epitaxial growth SiC is 0.01～10%.
7. preparation method according to claim 1, is characterized in that, in the NMOSFET preparation process of described upper strata, P, As or its hybrid ionic are selected in the doping of leakage one's own department or unit, source.
8. preparation method according to claim 1, is characterized in that, in described step 9, each step is carried out being less than under the environment of 500 ℃.
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