CN102708839B - Method for synchronously displaying signals in batch on spliced wall - Google Patents
Method for synchronously displaying signals in batch on spliced wall Download PDFInfo
- Publication number
- CN102708839B CN102708839B CN201210223456.5A CN201210223456A CN102708839B CN 102708839 B CN102708839 B CN 102708839B CN 201210223456 A CN201210223456 A CN 201210223456A CN 102708839 B CN102708839 B CN 102708839B
- Authority
- CN
- China
- Prior art keywords
- control register
- register
- combination
- configuration parameter
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The invention discloses a method for synchronously displaying signals in batch on a spliced wall. A FPGA (Field Programmable Gate Array) logic processing unit on the spliced wall is equipped with two levels of registers, namely a temporary register and an effective control register, wherein the effective control register is used for storing the configuration parameter of the current batch of signals, and the temporary register is used for storing the configuration parameter of the next batch of signals. Before signal switching, the data of the signals to be displayed is prestored in the temporary register, and after the prestoring operation, the data in the temporary register is latched to the effective control register through a synchronous control register so that the FPGA logic processing unit of the spliced wall perform the processing and display operations according to the data in the effective control register. By adoption of the prestoring mode, the time that the effective control register obtains data is greatly saved, the phenomenon of asynchronous image display in different signal windows is avoided, and the user experience is improved.
Description
Technical field
The present invention relates to combination display technique field, particularly relate to the method for a kind of combination batch signal simultaneous display.
Background technology
In order to meet the various demands of user, the signal source of large-screen splicing wall is more and more diversified.For the ease of operation, usually will show the operation setting of multiple signal for batch display mode signal at combination control end simultaneously.When being switched to another batch display mode signal from one batch display mode signal, in large-screen splicing wall, multiple signal window parameter being configured and occurring time delay, the phenomenons such as Signal aspects window is asynchronous, Hua Ping, blue screen will be caused.
Summary of the invention
Based on above-mentioned situation, the present invention proposes the method for a kind of combination batch signal simultaneous display, with the batch of simultaneous display on combination signal.
A method for combination batch signal simultaneous display, comprises step:
At the fpga logic processing unit configuration temporary register of combination, effectively control register and synchro control register;
The configuration parameter of present lot signal preserved by described effective control register;
Described temporary register preserves the configuration parameter of next batch signal according to the control command received;
After the preservation work of described temporary register completes, described synchro control register triggers the latch between described temporary register and described effective control register, and the configuration parameter preserved in described temporary register is updated to described effective control register by described latch;
The fpga logic processing unit of combination to process signal source according to the configuration parameter in described effective control register and shows.
Preferably, also configure display and control register at the fpga logic processing unit of combination,
Described display and control register, after receiving described control command, controls the fpga logic processing unit of combination, makes combination show image freeze by the mode reading and writing same two field picture;
After the configuration parameter preserved in described temporary register is updated to described effective control register by described latch, described display and control register controls the fpga logic processing unit of combination, is activated the image of combination display by the mode of circulation read-write two field picture.
Preferably, described temporary register also carries out pre-service to the configuration parameter of the next batch signal preserved.
Preferably, described synchro control register adopts the mode sending enable signal to trigger described latch.
The method of combination batch signal simultaneous display of the present invention, the fpga logic processing unit of combination is configured with two-stage register, i.e. temporary register and effective control register.Wherein, effective control register is for preserving the configuration parameter of present lot signal, and temporary register is for preserving the configuration parameter of next batch signal.Before signal switching, by the data pre-storage of signal to be shown in temporary register, after the operation that prestores completes, adopt synchro control register again by latches data in temporary register to effective control register, make the fpga logic processing unit of combination carry out processing according to the data in effective control register and show.Owing to have employed the mode prestored, greatly save the time that effective controller register obtains data, avoided the nonsynchronous phenomenon of different windows display image, improve Consumer's Experience.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method for combination of the present invention batch signal simultaneous display;
Relation schematic diagram between each register of Fig. 2 to be the present invention be combination fpga logic processing unit configuration.
Embodiment
Traditional technology, the fpga logic processing unit of combination is only provided with one-level register, and it is longer to this register write data used time for causing image to show nonsynchronous basic reason.The present invention, from the angle reducing the register data write time, solves the nonsynchronous problem of combination batch Signal aspects.The present invention is explained in detail below in conjunction with accompanying drawing and embodiment.
The method of combination batch signal simultaneous display of the present invention, as shown in Figure 1, comprises step:
Step S1, at the fpga logic processing unit configuration temporary register of combination, effectively control register and synchro control register;
The configuration parameter of present lot signal preserved by step S2, described effective control register;
Step S3, described temporary register preserve the configuration parameter of next batch signal according to the control command received;
After the preservation work of step S4, described temporary register completes, described synchro control register triggers the latch between described temporary register and described effective control register, and the configuration parameter preserved in described temporary register is updated to described effective control register by described latch;
The fpga logic processing unit of step S5, combination to process signal source according to the configuration parameter in described effective control register and shows.
The fpga logic processing unit of combination controls the display effect of combination, as shown in Figure 2, the present invention is that fpga logic processing unit is configured with temporary register, effectively control register and synchro control register, be connected by a latch between temporary register with effective control register, the Enable Pin of latch is connected with synchro control register.Wherein, the configuration parameter of the in store present lot signal of effective control register, fpga logic processing unit to process picture signal according to the data in this register and shows on combination.When needs by present lot signal switching to next batch signal time, operating personnel send control command to fpga logic unit, and temporary register preserves the configuration parameter of next batch signal according to control command.After the preservation work of all temporary registers all completes, synchro control register sends enable signal to latch, and latch is triggered, by the latches data in temporary register to effective control register.Fpga logic processing unit reads data new in effective control register, simultaneous display next batch signal on combination.
In order to improve simultaneous display effect further, the present invention is also configured with display and control register at the fpga logic processing unit of combination, for controlling the static or movable of combination display image.Specific practice is: display and control register, after receiving above-mentioned control command, controls the fpga logic processing unit of combination, makes combination show image freeze by the mode reading and writing same two field picture; After the configuration parameter preserved in temporary register is updated to effective control register by latch, display and control register controls the fpga logic processing unit of combination, is activated the image of combination display by the mode of circulation read-write two field picture.So, the effect that user sees from combination is, last batch signal synchronism switching is to next batch signal.
As a preferred embodiment, temporary register also carries out pre-service to the configuration parameter of the next batch signal preserved, and as the computing of algorithm, to reduce the processing time of fpga logic processing unit, accelerates the simultaneous display of image.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (3)
1. a method for combination batch signal simultaneous display, is characterized in that, comprise step:
At the fpga logic processing unit configuration temporary register of combination, effectively control register and synchro control register;
The configuration parameter of present lot signal preserved by described effective control register;
Described temporary register preserves the configuration parameter of next batch signal according to the control command received;
After the preservation work of described temporary register completes, described synchro control register triggers the latch between described temporary register and described effective control register, and the configuration parameter preserved in described temporary register is updated to described effective control register by described latch;
The fpga logic processing unit of combination to process signal source according to the configuration parameter in described effective control register and shows,
Display and control register is also configured at the fpga logic processing unit of combination,
Described display and control register, after receiving described control command, controls the fpga logic processing unit of combination, makes combination show image freeze by the mode reading and writing same two field picture;
After the configuration parameter preserved in described temporary register is updated to described effective control register by described latch, described display and control register controls the fpga logic processing unit of combination, is activated the image of combination display by the mode of circulation read-write two field picture.
2. the method for combination batch signal simultaneous display according to claim 1, it is characterized in that, described temporary register also carries out pre-service to the configuration parameter of the next batch signal preserved.
3. the method for combination batch signal simultaneous display according to claim 1, it is characterized in that, described synchro control register adopts the mode sending enable signal to trigger described latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210223456.5A CN102708839B (en) | 2012-06-29 | 2012-06-29 | Method for synchronously displaying signals in batch on spliced wall |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210223456.5A CN102708839B (en) | 2012-06-29 | 2012-06-29 | Method for synchronously displaying signals in batch on spliced wall |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102708839A CN102708839A (en) | 2012-10-03 |
| CN102708839B true CN102708839B (en) | 2014-12-24 |
Family
ID=46901545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210223456.5A Expired - Fee Related CN102708839B (en) | 2012-06-29 | 2012-06-29 | Method for synchronously displaying signals in batch on spliced wall |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102708839B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375792B (en) * | 2014-10-14 | 2017-11-03 | 浙江宇视科技有限公司 | A kind of synchronous method of figure layer change |
| CN106331591B (en) * | 2015-06-26 | 2019-08-20 | 杭州海康威视数字技术股份有限公司 | The method for synchronously switching and device of monitored picture |
| CN110248222B (en) * | 2018-11-21 | 2023-03-17 | 浙江大华技术股份有限公司 | Method, device and system for synchronously displaying multiple windows |
| CN112995531B (en) * | 2019-12-13 | 2023-02-10 | 浙江宇视科技有限公司 | Synchronous splicing display method and device, decoding splicing controller and medium |
| CN113473082A (en) * | 2021-06-28 | 2021-10-01 | 青岛信芯微电子科技股份有限公司 | Reference monitor and method for switching video mode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034521A (en) * | 2007-04-05 | 2007-09-12 | 深圳安凯微电子技术有限公司 | Method for updating image frame parameter |
| CN101404151A (en) * | 2008-08-04 | 2009-04-08 | 广东威创视讯科技股份有限公司 | Multi-screen splicing apparatus and method |
| CN102376293A (en) * | 2010-08-19 | 2012-03-14 | 上海济丽信息技术有限公司 | Image mosaic processor on basis of FPGA (Field Programmable Gata Array) and image mosaic method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3636148B2 (en) * | 2002-03-07 | 2005-04-06 | セイコーエプソン株式会社 | Display driver, electro-optical device, and display driver parameter setting method |
| JP5119655B2 (en) * | 2006-12-13 | 2013-01-16 | 株式会社日立製作所 | Multi-screen display device |
-
2012
- 2012-06-29 CN CN201210223456.5A patent/CN102708839B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034521A (en) * | 2007-04-05 | 2007-09-12 | 深圳安凯微电子技术有限公司 | Method for updating image frame parameter |
| CN101404151A (en) * | 2008-08-04 | 2009-04-08 | 广东威创视讯科技股份有限公司 | Multi-screen splicing apparatus and method |
| CN102376293A (en) * | 2010-08-19 | 2012-03-14 | 上海济丽信息技术有限公司 | Image mosaic processor on basis of FPGA (Field Programmable Gata Array) and image mosaic method |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2003-263134A 2003.09.19 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102708839A (en) | 2012-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102708839B (en) | Method for synchronously displaying signals in batch on spliced wall | |
| US8384738B2 (en) | Compositing windowing system | |
| TWI559222B (en) | Techniques to transmit commands to a target device | |
| US20190043435A1 (en) | Electronic device and method for adjusting refresh rate of display screen | |
| CN104750451A (en) | Splicing device and splicing display system | |
| WO2016078254A1 (en) | Display method and terminal, storage medium | |
| WO2015161578A1 (en) | Window management method and device | |
| CN107624194B (en) | For operating the device and method of the timing controller of display | |
| WO2019015095A1 (en) | Dual-system based handwriting writing and display method and system, and storage medium and device | |
| WO2015165013A1 (en) | Method for displaying data on screen and display control apparatus | |
| JP2016194562A (en) | Display driver, display device, and display device system | |
| US9761202B2 (en) | Seamless video transitions | |
| US20210193010A1 (en) | Frame-level resynchronization between a display panel and a display source device for full and partial frame updates | |
| US11249640B2 (en) | Electronic apparatus and controlling method thereof | |
| CN109189359A (en) | A kind of main resolution ratio input control method of display equipment, system and storage medium | |
| KR101641311B1 (en) | External connect display port switchable display circuit | |
| CN105843576B (en) | A kind of combination windows switching method and device | |
| US9958980B2 (en) | Driving method and driving device of touch control display | |
| US11275924B2 (en) | Eye-protection mode processing method, device, terminal and computer-readable storage medium in fingerprint recognition mode | |
| US8497877B2 (en) | Electronic device and method of switching display images | |
| CN107197182A (en) | A kind of method, device and the TV of display screen menu on TV | |
| US20150121284A1 (en) | Method for information processing and electronic apparatus thereof | |
| CN104079855A (en) | Digital video device and method for reading EDID of HDMI | |
| CN104679306A (en) | Electronic device with double touch display devices and picture display method thereof | |
| CN102682729B (en) | Rapid rectangle drawing method of liquid crystal display (LCD) controller based on complex programmable logic device (CPLD) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 510670 Guangdong city of Guangzhou province Kezhu Guangzhou high tech Industrial Development Zone, Road No. 233 Patentee after: VTRON GROUP Co.,Ltd. Address before: 510663 Guangzhou province high tech Industrial Development Zone, Guangdong, Cai road, No. 6, No. Patentee before: VTRON TECHNOLOGIES Ltd. |
|
| CP03 | Change of name, title or address | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141224 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |