CN104375792B - A kind of synchronous method of figure layer change - Google Patents
A kind of synchronous method of figure layer change Download PDFInfo
- Publication number
- CN104375792B CN104375792B CN201410541890.7A CN201410541890A CN104375792B CN 104375792 B CN104375792 B CN 104375792B CN 201410541890 A CN201410541890 A CN 201410541890A CN 104375792 B CN104375792 B CN 104375792B
- Authority
- CN
- China
- Prior art keywords
- layer
- write
- ddr
- enable
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The present invention provides a kind of figure layer change synchronous method, and this method is changed applied to single screen figure layer, and this method includes：During figure layer change, if being related to issuing for figure layer change Mating parameters, then before CPU issues figure layer change Mating parameters, CPU issues correspondence figure layer and writes enable shutdown signal, DDR write management module receive this write enable shutdown signal after, based on frame so that correspondence figure layer write enable switch be closed；After the completion of figure layer change Mating parameters are issued, DDR writes management module and writes enable switch based on frame opening correspondence figure layer；And DDR write management module based on frame cause correspondence figure layer write enable switch be closed when, base map refresh module carry out base map refresh operation.The program solves the problem of flower screen occurs in single screen in figure layer change.
Description
Technical field
The present invention relates to image display technology field, more particularly to a kind of synchronous method of figure layer change.
Background technology
First, video synthesis platform form is introduced
Video synthesis platform has extensive use in fields such as safety monitoring, commander, emergency schedulings.Video synthesis platform can
There is provided the access such as simulation monitoring image, IP monitoring images, SDI monitoring images, EPON monitoring images, conference terminal image, management,
Storage and large-size screen monitors such as show at the integrated application, please join Fig. 1.
Monitoring image access species is a lot, such as SDI, VGA, HDMI, optical port, power port, IP, non-IP etc.；Send aobvious screen
Curtain combines also a lot, such as 3*3,4*3,4*4,6*3.To be flexibly adapted to various configurations, on hardware state, video synthesis is put down
The design of frame-type card insert type is usually taken in platform, please join shown in Fig. 2.
Input card, output board card are inserted on switching backplane, and data exchange, such as Fig. 3 are carried out by switching backplane.It is shown.
2nd, video synthesis platform figure layer conversion introduction to business
Video synthesis platform has the figure layers such as windowing, the roaming of the window that disappears, window, window scaling, window stack change business, with
Lower combination Fig. 4 is explained.
Fig. 4 shows 9 pieces of physics screens (video synthesis platform can support more physics screens), this 9 pieces of screens can be thought
It is specific as follows as into one piece of big " virtual " screen, various image changing operations are carried out in the big virtual screen of this block：
Windowing：Image window is operated from scratch；
Disappear window：Image window is from the operation having to nothing；
Roaming：Existing window leaves origin-location, is shown to other positions；
Scaling：Existing window changes original size and shown；
Lamination：Multiple windows overlays are shown.
3rd, graphic service is managed --- and DDR reads to spell operation with writing spelling operation
Multi-source image send the aobvious various displays for needing DDR to participate in, image being realized by caching, generally there is two kinds of operation sides
Formula, reads to spell operation with writing spelling operation.
Read spell operation, it is therefore named conceive exactly multiway images are read out from DDR, then complete splicing.In Fig. 5,4 road figures
As to realize lamination, 4 road images first can be write 4 pieces of DDR sections, address is read in then control, is read and is participated in from 4 block piece areas
The part of splicing, realizes lamination.Read to spell operation address complex management, DDR capacity requirements are big.
Spelling operation is write, it is therefore named to conceive completion splicing when exactly writing DDR, turn into a complete pair when DDR is read
Image reading.In Fig. 6,4 width images can be put into DDR sections according to stacking order successively, by the starting for controlling each image
Write address completes splicing, when image reading, as long as regarding complete image reading as.Write the letter of spelling mode DDR address administrations
Single, DDR capacity requirements are small.
4th, switching stationary problem is introduced
Switch stationary problem to introduce：Figure layer is in normal display, and user needs to change figure layer, such as open a window, the window that disappears, roaming,
Laminated layer sequence adjustment etc., correspondingly CPU can issue parameter to each business board.Because parameter is a lot, and need to be distributed at bottom
Module is managed, but CPU configuration bus downloading speed is limited, therefore in Altered Graphs layer operation, can generally there is the feelings shown in Fig. 7
Condition：
(1) part of module first comes into force parameter, such as module 1, module n.
(2) part of module I effect parameter, such as module n, module m.
(3) for certain two field picture, there is the possibility that the old and new's parameter coexists, such as X+1 frames, cause image to show of short duration flower
Screen.
(4) for the image across screen display, the picture of " diminution+roaming " shields across two up and down in such as Fig. 4, if
Just the two screens are on two pieces of output boards, once the configuration start and end time of two output boards is inconsistent, will cause half
Width image first updates, half images evening more news.
The content of the invention
In view of this, the present invention provides a kind of figure layer change synchronous method.
Applied to single screen figure layer change synchronous method be：During figure layer change, if being related to figure layer changes supporting ginseng
Several issues, then before CPU issues figure layer change Mating parameters, CPU issues correspondence figure layer and writes enable shutdown signal, DDR
Write-in management module receive this write enable shutdown signal after, based on frame so that correspondence figure layer write enable switch in close
State；After the completion of figure layer change Mating parameters are issued, DDR writes management module and writes enable based on frame opening correspondence figure layer
Switch；Also, DDR write management module based on frame cause correspondence figure layer write enable switch be closed when, base map
Refresh module carries out base map refresh operation.
Changing synchronous method applied to multi-screen figure layer includes：Each screen correspondence one FPGA, each FPGA include respective
DDR writes management module and base map refresh module；During figure layer change, if being related to issuing for figure layer change Mating parameters,
Then before CPU issues figure layer change Mating parameters, CPU issues correspondence figure layer and writes enable shutdown signal, then issues each DDR and write
Enter the shared heartbeat pulse of management module, each DDR write-ins management module is detected after heartbeat pulse at the same time, based on frame closing pair
That answers figure layer writes enable switch；After the completion of figure layer change Mating parameters are issued, the enable of writing that CPU issues correspondence figure layer is opened
Signal, then the shared heartbeat pulse of each DDR write-ins management module is issued, each DDR write-ins management module detects heartbeat at the same time
After pulse, the enable of writing for opening correspondence figure layer based on frame is switched；Also, correspondence is caused based on frame in each DDR write-in management modules
When writing enable switch closing of figure layer, each FPGA base map brush lower module carries out base map refresh operation.
Compared to prior art, the synchronous method of single screen figure layer change solves single screen in figure layer change and flower screen occurs
The problem of；The synchronous method of multi-screen figure layer change, on the basis of single screen scheme, is controlled by shared heartbeat pulse, realized
The synchronization that multi-screen figure layer updates so that user has good experience.
Brief description of the drawings
Fig. 1 is a kind of video synthesis platform.
Fig. 2 is a kind of video synthesis platform framework card insert type design drawing.
Fig. 3 is that a kind of video synthesis platform back plane exchanges schematic diagram.
Fig. 4 is video synthesis platform figure layer change business exemplary plot.
Fig. 5 is to read to spell operation chart.
Fig. 6 is to write spelling operation chart.
Fig. 7 is that parameter issues and flows to schematic diagram with image transmitting.
Fig. 8 is a kind of hardware design block diagram of the embodiment of the present invention.
Fig. 9 is that figure layer of the present invention stacks order switching exemplary plot.
Figure 10 is the another hardware design block diagram of the embodiment of the present invention.
Figure 11 is the supporting operational flowcharts of CPU and FPGA during figure layer change.
Embodiment
Based on the technical problem mentioned in background technology, the present invention program is mainly solved in figure layer handoff procedure, single
Screen occurs without colored screen；And in figure layer handoff procedure, across the figure layer synchronized update of screen display.Below by specific embodiment
Describe in detail.
It please join the hardware design block diagram of the embodiment of the present invention shown in Fig. 8, the hardware design figure is used for single screen figure layer and changes control
System.FPGA output boards in figure include DDR and write management module.In embodiments of the present invention, the DDR writes management module and had
Control the enable switch that each figure layer writes；When carry out figure layer change operation when, CPU will issue correspondence figure layer write enable open or
The signal that person closes, DDR write-ins management module receive carry out that corresponding diagram layer writes enable after the CPU signal beat on or off
Close.The FPGA also includes base map refresh module, and the base map that the base map refresh module is used for when figure layer is changed refreshes.There is DDR to write
Enter after enable switch and base map refresh module that management module controls the write-in of each figure layer, it is single when carrying out figure layer change
Screen there will not be the phenomenon that flower shields.Illustrated below by way of a specific example.
It please join Fig. 9, Fig. 9 gives the example of single physics screen " figure layer stacks order and changed " operation.In this example embodiment, DDR
Caching is divided to two sections：One read tablet area, one write section；The section of writing of ping-pong operation, i.e. this frame is taken to write in reading and writing section
Afterwards, as the read tablet area of lower frame；Relative, after this frame read tablet area is run through, section is write as lower frame；Read-write operation is entered based on frame
Row change.
Under normal circumstances, read-write section content is consistent.Such as Fig. 9, write section and stacked according to figure layer sequence number 1,2,3,4, DDR writes
Interface then sequentially inputs figure layer with 1,2,3,4, and DDR reads interface and reads the image spliced from DDR read tablets area.
In this example, figure layer change refers to the change that figure layer 2 stacks order.Indicate that figure layer 2 is folded when sending instructions under user
Put forward after sequence change, what CPU issued figure layer 2 writes enable shutdown signal, DDR write management module receive CPU this write enable
The enable of writing of the figure layer 2 operated is closed after shutdown signal.It must be based on frame during closing to be operated, otherwise figure layer disappears
When colored screen occurs.When closing figure layer 2 writes enable, base map refresh module starts base map and refreshed, if not refreshing base map can cause
The figure layer operated is remained in DDR sections, so must be covered with base map, now DDR writes the figure layer write-in of interface
Order is 0 (base map), 1,3,4.In above process, while writing enable if turned off figure layer 2, base map refresh module is sufficiently fast
Carry out base map refreshing, DDR writes interface, and write sequence is 0 (base map), 1,3,4 figure layer immediately, then write will not in section by DDR
There is the situation that figure layer 2 is remained, that is, be not in that Fig. 9 the 2nd arranges content shown in the 1st piece " DDR writes section content transitions ".Only
After closing figure layer 2 writes enable, base map refreshing startup is not fast enough, and when refreshing not fast enough, just occurs that Fig. 9 the 2nd arranges the 1st piece
Content shown in " DDR writes section content transitions ".But actually such case can not possibly occur substantially.In the present embodiment, use
FPGA realizes that figure layer writes opening/closing function of enable, and writes startup base map refreshing while enable is closed, because figure layer is write
Enable after closing, release DDR write performances, the performance of release is sufficient for fast refresh base map, so being not in substantially
Fig. 9 the 2nd arranges the content shown in the 1st piece " DDR writes section content transitions ".Because ping-pong operation is taken in DDR read-writes, section content is write
Transition is completed in a frame in, and during which read tablet area still maintains former content, and the 2nd piece is arranged with reference to the 2nd, is completed when writing the frame in of section one
After transition, according to ping-pong operation principle, section content transforming is write for read tablet area content, the 2nd piece is arranged with reference to the 3rd, so read operation
The content of reading please join the 3rd arrange shown on the 2nd piece, screen for the 3rd content for arranging the 3rd piece.So showing on said process, screen
The content shown will be changed into three figure layers from four figure layers, be not in that figure layer 2 remains and causes visually to think that figure layer change is different
Normal situation occurs.
Enable is write in figure layer 2 to be closed, when DDR writes section refreshing base map, CPU stacks matching somebody with somebody for order change by figure layer is issued
Cover parameter (such as figure layer 2 needs which position etc. be stacked on).Although issuing the Mating parameters and figure layer step-out,
Closed due to writing to enable, so chaotic image can not possibly be written in DDR cachings, so can't see colored screen on screen.
After the completion of the Mating parameters are issued, it is meant that in place, figure layer and parameter are synchronized for each parameter.CPU is issued
Figure layer 2 writes the opening signal of enable, and DDR writes management module after the CPU signal is received, writing for figure layer 2 is opened based on frame
Enable, the figure layer write sequence of write-in interface is 1,3,4,2, DDR write the content update deposited in a frame time section be 1,
3rd, 4,2 lamination picture, then completes figure layer and stacks order switching.4 tomographic images will be normally displayed on screen, wherein figure layer
2 are moved to top layer.
Above-mentioned figure layer stacks issuing for order change Mating parameters and generally completed in the same frame time that base map refreshes；And
That figure layer 2 is opened after the completion of parameter is issued writes enable, so when showing that the image for lacking figure layer 2 only continues a frame on screen
Between, user is not felt by all.
Above-mentioned figure layer, which stacks order change, can regard disappear window operation and the combination of lamination operation as.So for the window behaviour that disappears
Make, can essentially be summarized as：When need to disappear window when, what CPU issued the figure layer for the window that needs to disappear writes enable shutdown signal, and DDR writes
Enter management module receiving after this writes enable shutdown signal, closed the enable of writing of the figure layer for the window that needs to disappear based on frame, base map
Refresh module carries out base map refresh operation simultaneously.And for lamination operation, can be carried out on the basis of the window operation that disappears by CPU
Lamination Mating parameters are issued, after the completion of the lamination Mating parameters are issued, and the enable of writing that CPU issues the figure layer for needing lamination is beaten
ON signal, DDR write management module receive this write enable opening signal after, the writing for figure layer of lamination will be needed based on frame to be made
It can open.
The concrete operations mode changed according to above-mentioned figure layer, we can draw includes windowing, roaming, scaling for other
The embodiment of change, be specially：
When needing windowing, CPU carries out issuing for windowing Mating parameters；After the completion of the windowing Mating parameters are issued, CPU
Issue the figure layer that needs to open a window writes enable opening signal, and DDR writes management module and received after this writes enable opening signal,
The enable of writing for needing the figure layer opened a window is opened based on frame.
When needing figure layer to roam, what CPU issued the figure layer that needs to roam writes enable shutdown signal, DDR write-in management moulds
Block receive this write enable shutdown signal after, based on frame will need roam figure layer write enable close, base map refresh module
Base map refresh operation is carried out simultaneously, and CPU carries out issuing for roaming Mating parameters；After the completion of the roaming Mating parameters are issued,
What CPU issued the figure layer that needs to roam writes enable opening signal, and DDR writes management module and writes enable opening signal receiving this
Afterwards, the enable of writing for needing the figure layer roamed is opened based on frame.
When needing figure layer to scale, what CPU issued the figure layer that needs to scale writes enable shutdown signal, DDR write-in management moulds
Block receive this write enable shutdown signal after, based on frame will need scale figure layer write enable close, base map refresh module
Base map refresh operation is carried out simultaneously, and CPU zooms in and out issuing for Mating parameters；After the completion of the scaling Mating parameters are issued, CPU
Issue the figure layer that needs to scale writes enable opening signal, and DDR writes management module and received after this writes enable opening signal,
The enable of writing for needing the figure layer scaled is opened based on frame.
From above figure layer change operation it is seen that, single screen figure layer change during, it is necessary to as follows
Perform：If being related to issuing for figure layer change Mating parameters, before CPU issues figure layer change Mating parameters, CPU issues correspondence
Figure layer writes enable shutdown signal, and DDR writes management module and received after this writes enable shutdown signal, based on frame so that correspondence
The enable switch of writing of figure layer is closed；After the completion of figure layer change Mating parameters are issued, DDR write-in management module bases
The enable of writing for opening correspondence figure layer in frame is switched；Also, writing management module based on frame in DDR causes correspondence figure layer to write enable
When switch is closed, base map refresh module carries out base map refresh operation.So, when would not occur spending screen on individual screen
Phenomenon, what user saw will be smooth figure layer change.
Figure layer on multi-screen is changed, namely is changed across the figure layer of screen, it is necessary on the basis of the change of single screen figure layer, increase
The link of one heartbeat pulse detection.The heartbeat pulse is that all FPGA output boards are shared, and each plate can be detected in synchronization
To heartbeat.
It please join the multi-screen figure layer change control hardware design block diagram shown in Figure 10.The hardware design block diagram is defeated with 2 FPGA
Ejecting plate, 2 physics screens and 4 figure layers are shown as example across screen display.Relative to the single screen figure layer change control hardware design shown in Fig. 8
Block diagram, Figure 10 mainly adds the CPLD for producing heartbeat pulse.The generation of the heartbeat pulse is controlled by CPU.The heart
The DDR write-ins management module that jump pulse is distributed on each FPGA output boards, each FPGA output boards by backboard shares the heartbeat pulse,
DDR write-ins management module on each FPGA output boards can synchronously detect heartbeat.Certainly, if CPU can produce heartbeat arteries and veins
Punching can be without setting CPLD.
The concrete operations changed on multi-screen figure layer, can be performed as follows：During figure layer change, if relating to
And figure layer changes issuing for Mating parameters, then before CPU issues figure layer change Mating parameters, CPU issues writing for correspondence figure layer
Shutdown signal is enabled, then issues the shared heartbeat pulse of each DDR write-ins management module, each DDR write-ins management module is examined at the same time
Measure after heartbeat pulse, the enable of writing for closing correspondence figure layer based on frame is switched；After the completion of figure layer change Mating parameters are issued,
What CPU issued correspondence figure layer writes enable opening signal, then issues the shared heartbeat pulse of each DDR write-ins management module, and each DDR writes
Enter management module to detect after heartbeat pulse at the same time, the enable of writing for opening correspondence figure layer based on frame is switched；Also, in each DDR
Write-in management module causes when writing enable switch closing of correspondence figure layer based on frame, and each FPGA base map brush lower module carries out base map
Refresh operation.
CPU issue correspondence figure layer write enable close/open signal after, the signal will by each DDR write management module
Receive, but the time that each DDR write-ins management module receives the signal may be inconsistent, so each DDR write-in management moulds
Block does not enter the close/open of row write enable based on frame immediately after the signal is received, and is to wait for after heartbeat pulse arrives again
Enter the close/open of row write enable based on frame.According to described previously, heartbeat pulse can be write by each DDR in the same time and manage
Module is received, so each DDR write-ins management module will write enable in same time close/open.Each DDR writes management module
Closed in the same time after writing enable, the base map that the base map refresh module on each FPGA is carried out refreshes, CPU issues figure layer change and matched somebody with somebody
Covering the operation of parameter will start, so the associative operation being related on each FPGA is all synchronous.So ensure that multi-screen shows
The synchronization that diagram layer updates.
The detailed process of each figure layer change operation is described in detail down again below：
When needing windowing, CPU carries out issuing for windowing Mating parameters；After the completion of the windowing Mating parameters are issued, CPU
Issue the figure layer that needs open a window writes enable opening signal, then issues the shared heartbeat pulse of each DDR write-ins management module, respectively
DDR write-ins management module is detected after heartbeat pulse at the same time, and the writing for figure layer that being opened based on frame needs to open a window enables switch.
When need to disappear window when, what CPU issued the window figure layer that needs to disappear writes enable shutdown signal, then issues each DDR write-ins management
The shared heartbeat pulse of module, each DDR write-ins management module is detected after heartbeat pulse at the same time, and being closed based on frame needs the window that disappears
The enable of writing of figure layer is switched, and each FPGA base map refresh module carries out base map refresh operation.
When needing figure layer to roam, what CPU issued roaming figure layer writes enable shutdown signal, then issues each DDR write-ins management
The shared heartbeat pulse of module, each DDR write-ins management module is detected after heartbeat pulse at the same time, and roaming figure layer is closed based on frame
Write enable switch, each FPGA base map refresh module carries out base map refresh operation；CPU carries out issuing for roaming Mating parameters；
After the completion of the roaming Mating parameters are issued, what CPU issued roaming figure layer writes enable opening signal, then issues each DDR write-ins pipe
The shared heartbeat pulse of module is managed, each DDR write-ins management module is detected after heartbeat pulse at the same time, and Roaming figure is opened based on frame
The enable of writing of layer is switched.
When needing figure layer to scale, what CPU issued scaling figure layer writes enable shutdown signal, then issues each DDR write-ins management
The shared heartbeat pulse of module, each DDR write-ins management module is detected after heartbeat pulse at the same time, and scaling figure layer is closed based on frame
Write enable switch, each FPGA base map refresh module carries out base map refresh operation；CPU zooms in and out issuing for Mating parameters；
After the completion of the scaling Mating parameters are issued, what CPU issued scaling figure layer writes enable opening signal, then issues each DDR write-ins pipe
The shared heartbeat pulse of module is managed, each DDR write-ins management module is detected after heartbeat pulse at the same time, and scaling figure is opened based on frame
The enable of writing of layer is switched.
When needing figure layer lamination, CPU issue stack figure layer write enable shutdown signal, then issue each DDR write-ins management
The shared heartbeat pulse of module, each DDR write-ins management module is detected after heartbeat pulse at the same time, is closed based on frame and is stacked figure layer
Write enable switch, each FPGA base map refresh module carries out base map refresh operation；CPU carries out issuing for lamination Mating parameters；
After the completion of the lamination Mating parameters are issued, what CPU issued lamination figure layer writes enable opening signal, then issues each DDR write-ins pipe
The shared heartbeat pulse of module is managed, each DDR write-ins management module is detected after heartbeat pulse, opened based on frame and stack figure at the same time
The enable of writing of layer is switched.
On the above-mentioned window that disappears, scaling, roaming, lamination across screen figure layer change operation can showing with further reference to Figure 11
Example.But Figure 11 only provides FPGA processing procedure；Other FPGA processing procedure is identical with the FPGA in Figure 11.From figure
As can be seen that whole process FPGA, i.e. FPGA DDR write-ins management module are responsible for detecting heartbeat, it is based on when detecting after heartbeat
Frame beats opening/closing and writes enable.For CPU, operation logic is very simple：Issue and write enable and close → issue heartbeat pulse → renewal
Parameter (size, coordinate, laminated layer sequence etc.) → parameter, which is issued, to be completed → issue write enable open → issue heartbeat pulse.
The present invention program writes the opening and closing of enable based on figure layer, and base map refreshes, the control issued of figure layer change parameter
System, realizes the purpose that single screen figure layer becomes less flower screen.Further, on the basis of single screen scheme, shared heartbeat arteries and veins is passed through
Punching control, realizes the synchronization of multi-screen figure layer renewal so that user has good experience.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (5)
1. a kind of synchronous method of figure layer change, this method is changed applied to single screen figure layer, it is characterised in that this method includes：
During figure layer change, if being related to issuing for figure layer change Mating parameters, issue the figure layer in CPU and change supporting ginseng
Before number, what CPU issued correspondence figure layer writes enable shutdown signal, and DDR writes management module and writes enable shutdown signal receiving this
Afterwards, based on frame so that the enable switch of writing of correspondence figure layer is closed；After the completion of figure layer change Mating parameters are issued,
DDR is write management module and switched based on the enable of writing that frame opens correspondence figure layer；
Also, DDR write management module based on frame cause correspondence figure layer write enable switch be closed when, base map brush
New module carries out base map refresh operation；
The DDR write-in management modules are opened writing for correspondence figure layer based on frame and enabled after switch, figure layer data write-in DDR cachings
Write section, the DDR caching also include read tablet area, the reading and writing section uses ping-pong operation based on frame.
2. the synchronous method of figure layer change as claimed in claim 1, it is characterised in that the figure layer, which becomes, to be further included windowing, disappears
Window, figure layer roaming, figure layer scaling and figure layer lamination；
When needing windowing, CPU carries out issuing for windowing Mating parameters；After the completion of the windowing Mating parameters are issued, CPU is issued
The figure layer of windowing is needed to write enable opening signal, DDR writes management module and received after this writes enable opening signal, is based on
Frame opens the enable of writing for needing the figure layer opened a window；
When need to disappear window when, what CPU issued the figure layer for the window that needs to disappear writes enable shutdown signal, and DDR writes management module and received
Write after enable shutdown signal, closed the enable of writing of the figure layer for the window that needs to disappear based on frame, base map refresh module is carried out simultaneously to this
Base map refresh operation；
When needing figure layer to roam, what CPU issued the figure layer that needs to roam writes enable shutdown signal, and DDR write-ins management module exists
Receive this to write after enable shutdown signal, closed the enable of writing for needing the figure layer roamed based on frame, base map refresh module is simultaneously
Base map refresh operation is carried out, CPU carries out issuing for roaming Mating parameters；After the completion of the roaming Mating parameters are issued, CPU is issued
The figure layer of roaming is needed to write enable opening signal, DDR writes management module and received after this writes enable opening signal, is based on
Frame opens the enable of writing for needing the figure layer roamed；
When needing figure layer to scale, what CPU issued the figure layer that needs to scale writes enable shutdown signal, and DDR write-ins management module exists
Receive this to write after enable shutdown signal, closed the enable of writing for needing the figure layer scaled based on frame, base map refresh module is simultaneously
Base map refresh operation is carried out, CPU zooms in and out issuing for Mating parameters；After the completion of the scaling Mating parameters are issued, CPU is issued
The figure layer of scaling is needed to write enable opening signal, DDR writes management module and received after this writes enable opening signal, is based on
Frame opens the enable of writing for needing the figure layer scaled；
When needing figure layer lamination, what CPU issued the figure layer that needs lamination writes enable shutdown signal, and DDR write-ins management module exists
Receive this to write after enable shutdown signal, the enable of writing of the figure layer of lamination will be needed to close based on frame, base map refresh module is simultaneously
Base map refresh operation is carried out, CPU carries out issuing for lamination Mating parameters；After the completion of the lamination Mating parameters are issued, CPU is issued
The figure layer of lamination is needed to write enable opening signal, DDR writes management module and received after this writes enable opening signal, is based on
Frame will need the enable of writing of the figure layer of lamination to open.
3. a kind of synchronous method of figure layer change, this method is changed applied to multi-screen figure layer, wherein one FPGA of each screen correspondence, often
Individual FPGA includes respective DDR and writes management module and base map refresh module, it is characterised in that this method includes：
During figure layer change, if being related to issuing for figure layer change Mating parameters, issue the figure layer in CPU and change supporting ginseng
Before number, what CPU issued correspondence figure layer writes enable shutdown signal, then issues the shared heartbeat pulse of each DDR write-ins management module, respectively
DDR write-ins management module is detected after heartbeat pulse at the same time, and the enable of writing for closing correspondence figure layer based on frame is switched；In the figure layer
After the completion of change Mating parameters are issued, what CPU issued correspondence figure layer writes enable opening signal, then issues each DDR write-ins management mould
The shared heartbeat pulse of block, each DDR write-ins management module is detected after heartbeat pulse at the same time, and correspondence figure layer is opened based on frame
Write enable switch；
Also, when writing enable switch closing of correspondence figure layer, each FPGA base map are caused based on frame in each DDR write-in management modules
Brush lower module carries out base map refresh operation；
Each DDR write-in management modules are opened writing for correspondence figure layer based on frame and enabled after switch, and the figure layer data write-in is each
What DDR was cached writes section, and each DDR cachings also include read tablet area, and the reading and writing section uses ping-pong operation based on frame.
4. the synchronous method of figure layer change as claimed in claim 3, it is characterised in that the figure layer, which becomes, to be further included windowing, disappears
Window, figure layer roaming, figure layer scaling and figure layer lamination；
When needing windowing, CPU carries out issuing for windowing Mating parameters；After the completion of the windowing Mating parameters are issued, CPU is issued
Need the figure layer opened a window writes enable opening signal, then issues the shared heartbeat pulse of each DDR write-ins management module, and each DDR writes
Enter management module to detect after heartbeat pulse at the same time, the enable of writing that the figure layer for needing to open a window is opened based on frame is switched；
When need to disappear window when, what CPU issued the window figure layer that needs to disappear writes enable shutdown signal, then issues each DDR write-ins management module
Shared heartbeat pulse, each DDR write-ins management module is detected after heartbeat pulse at the same time, and being closed based on frame needs the window figure layer that disappears
Write enable switch, each FPGA base map refresh module carries out base map refresh operation；
When needing figure layer to roam, what CPU issued roaming figure layer writes enable shutdown signal, then issues each DDR write-ins management module
Shared heartbeat pulse, each DDR write-ins management module is detected after heartbeat pulse at the same time, and writing for roaming figure layer is closed based on frame
Switch is enabled, each FPGA base map refresh module carries out base map refresh operation；CPU carries out issuing for roaming Mating parameters；When this
After the completion of roaming Mating parameters are issued, what CPU issued roaming figure layer writes enable opening signal, then issues each DDR write-ins management mould
The shared heartbeat pulse of block, each DDR write-ins management module is detected after heartbeat pulse at the same time, and roaming figure layer is opened based on frame
Write enable switch；
When needing figure layer to scale, what CPU issued scaling figure layer writes enable shutdown signal, then issues each DDR write-ins management module
Shared heartbeat pulse, each DDR write-ins management module is detected after heartbeat pulse at the same time, and writing for scaling figure layer is closed based on frame
Switch is enabled, each FPGA base map refresh module carries out base map refresh operation；CPU zooms in and out issuing for Mating parameters；When this
After the completion of scaling Mating parameters are issued, what CPU issued scaling figure layer writes enable opening signal, then issues each DDR write-ins management mould
The shared heartbeat pulse of block, each DDR write-ins management module is detected after heartbeat pulse at the same time, and scaling figure layer is opened based on frame
Write enable switch；
When needing figure layer lamination, CPU issue stack figure layer write enable shutdown signal, then issue each DDR write-ins management module
Shared heartbeat pulse, each DDR write-ins management module is detected after heartbeat pulse at the same time, is closed based on frame and is stacked writing for figure layer
Switch is enabled, each FPGA base map refresh module carries out base map refresh operation；CPU carries out issuing for lamination Mating parameters；When this
After the completion of lamination Mating parameters are issued, what CPU issued lamination figure layer writes enable opening signal, then issues each DDR write-ins management mould
The shared heartbeat pulse of block, each DDR write-ins management module is detected after heartbeat pulse at the same time, is opened based on frame and is stacked figure layer
Write enable switch.
5. the synchronous method of figure layer change as described in claim 3 or 4, it is characterised in that the shared heartbeat pulse is
What CPU was produced, or control what CPLD was produced by CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410541890.7A CN104375792B (en) | 2014-10-14 | 2014-10-14 | A kind of synchronous method of figure layer change |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410541890.7A CN104375792B (en) | 2014-10-14 | 2014-10-14 | A kind of synchronous method of figure layer change |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104375792A CN104375792A (en) | 2015-02-25 |
| CN104375792B true CN104375792B (en) | 2017-11-03 |
Family
ID=52554746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410541890.7A Active CN104375792B (en) | 2014-10-14 | 2014-10-14 | A kind of synchronous method of figure layer change |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104375792B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111263208B (en) * | 2018-11-30 | 2022-11-04 | 杭州海康威视数字技术股份有限公司 | Picture synthesis method and device, electronic equipment and storage medium |
| CN110750748A (en) * | 2019-10-24 | 2020-02-04 | 杭州网景汇网络科技有限公司 | Webpage display method |
| CN112835660A (en) * | 2019-11-23 | 2021-05-25 | 西安诺瓦星云科技股份有限公司 | Media layer display method, device and system and storage medium |
| CN110888618B (en) * | 2019-11-28 | 2022-09-20 | 苏州长风航空电子有限公司 | Cross-screen display method of airborne display system based on FPGA |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6041349A (en) * | 1996-02-29 | 2000-03-21 | Hitachi, Ltd. | System management/network correspondence display method and system therefor |
| CN101034521A (en) * | 2007-04-05 | 2007-09-12 | 深圳安凯微电子技术有限公司 | Method for updating image frame parameter |
| CN102708839A (en) * | 2012-06-29 | 2012-10-03 | 广东威创视讯科技股份有限公司 | Method for synchronously displaying signals in batch on spliced wall |
| CN103021376A (en) * | 2012-11-26 | 2013-04-03 | 广东威创视讯科技股份有限公司 | Method and system for controlling multi-signal image window display |
| CN203084706U (en) * | 2013-01-21 | 2013-07-24 | 西安建艺设计制作策划有限公司 | Multi-screen information interactive demonstrating system |
-
2014
- 2014-10-14 CN CN201410541890.7A patent/CN104375792B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6041349A (en) * | 1996-02-29 | 2000-03-21 | Hitachi, Ltd. | System management/network correspondence display method and system therefor |
| CN101034521A (en) * | 2007-04-05 | 2007-09-12 | 深圳安凯微电子技术有限公司 | Method for updating image frame parameter |
| CN102708839A (en) * | 2012-06-29 | 2012-10-03 | 广东威创视讯科技股份有限公司 | Method for synchronously displaying signals in batch on spliced wall |
| CN103021376A (en) * | 2012-11-26 | 2013-04-03 | 广东威创视讯科技股份有限公司 | Method and system for controlling multi-signal image window display |
| CN203084706U (en) * | 2013-01-21 | 2013-07-24 | 西安建艺设计制作策划有限公司 | Multi-screen information interactive demonstrating system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104375792A (en) | 2015-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104363508B (en) | A kind of image split-joint method and device that prevent video from retracting | |
| CN104375792B (en) | A kind of synchronous method of figure layer change | |
| US10235964B2 (en) | Splicing display system and display method thereof | |
| CN105739934B (en) | Multi-screen splicing display processing method and equipment | |
| CN101442653B (en) | Multichannel video play and large screen display method | |
| CN103021378B (en) | A kind of device for multi-screen mosaic display and method | |
| US20100302130A1 (en) | Image display system, image display device, and image display method | |
| CN106981272B (en) | Backlight driving method, device and the display panel of display panel | |
| CN103236243B (en) | A kind of display device and televisor | |
| CN104469211B (en) | A kind of combination caption presentation method and device | |
| CN101710276A (en) | Method and device for setting and unlocking screensaver | |
| CN104980666B (en) | Video switcher and switching method thereof | |
| CN109272923B (en) | Subtitle rolling display method and system based on multi-screen equipment and storage medium | |
| CN110347363A (en) | Image based on display infinitely cuts splicing | |
| CN104112441B (en) | The removing method of aberration between a kind of multiple source splice displaying system and display screen seam | |
| CN107197356A (en) | A kind of method, device and the TV of display screen menu on television | |
| CN109783043A (en) | A kind of method, apparatus that display frequency is shown and display | |
| CN111782163B (en) | Image display method and apparatus | |
| CN109922230A (en) | Synchronous broadcast method, control method for playing back and the device of dynamic content | |
| CN203012698U (en) | Split joint screen synchronous playing device | |
| CN102918584B (en) | The graphic processing method of 3-D view and relational graph treating apparatus thereof | |
| CN102176756A (en) | Method, device and displayer for displaying stereo images | |
| CN102929810A (en) | Splicing displaying unit address setting method in spliced wall | |
| WO2011099296A1 (en) | Three-dimensional video image display device | |
| CN210466363U (en) | Image infinite cutting and splicing technology based on display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |