CN104375792A - Layer changing synchronizing method - Google Patents
Layer changing synchronizing method Download PDFInfo
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- CN104375792A CN104375792A CN201410541890.7A CN201410541890A CN104375792A CN 104375792 A CN104375792 A CN 104375792A CN 201410541890 A CN201410541890 A CN 201410541890A CN 104375792 A CN104375792 A CN 104375792A
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- layer
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- ddr
- writes
- administration module
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
Abstract
The invention provides a layer changing synchronizing method. The method is applied to single screen layer changing. The method includes the steps that in the layer changing process, if layer changing supporting parameter sending is related, a writing enabling closing signal of the corresponding layer is send by a CPU before the CPU sends the layer changing supporting parameters, and after a DDR write-in management module receives the writing enabling closing signal, a writing enabling switch of the corresponding layer is made to be in the closed state based on frames; after layer changing supporting parameter sending is finished, the DDR write-in management module opens the writing enabling switch of the corresponding layer based on the frames; besides, when the writing enabling switch of the corresponding layer is in the closed state through the DDR write-in management module based on the frames, a base map refreshing module conducts base map refreshing operation. By means of the scheme, the problem of single screen crashing in the layer changing process is solved.
Description
Technical field
The present invention relates to
figurepicture display technique field, particularly relates to one
figurelayer changes synchronous method.
Background technology
One, video synthesis platform form is introduced
Video synthesis platform has widespread use in fields such as safety monitoring, commander, emergency schedulings.Video synthesis platform can provide simulation monitoring
figurepicture, IP monitoring
figurepicture, SDI monitoring
figurepicture, EPON monitoring
figurepicture, conference terminal
figurepicture waits the integrated applications such as access, management, storage and large-size screen monitors display, please join
figure1.
Monitoring
figurepicture access kind is a lot, as SDI, VGA, HDMI, Guang Kou, electric mouth, IP, non-IP etc.; Send aobvious screen combination also a lot, as 3*3,4*3,4*4,6*3 etc.For adapting to various configurations neatly, on hardware state, video synthesis platform takes frame-type card insert type to design usually, please join
figureshown in 2.
Input card, output board card are inserted on switching backplane, carry out exchanges data by switching backplane, as
figure3.Shown in.
Two, video synthesis platform
figurelayer conversion introduction to business
Video synthesis platform has windowing, the roaming of the window that disappears, window, window convergent-divergent, window stack etc.
figurelayer changes business, below in conjunction with
figure4 make an explanation.
figure4 show 9 pieces of physics screen (video synthesis platform can support that more physics shields), these 9 pieces of screens can be imagined as one piece of large " virtual " screen, the large virtual screen of this block be carried out various
figurepicture alter operation, specific as follows:
Window:
figureas the operation that window grows out of nothing;
Disappear window:
figureas window from the operation had to nothing;
Roaming: there is window and left origin-location, to other position display;
Convergent-divergent: there is window and changed original size display;
Lamination: multiple windows overlay display.
Three,
figurepicture service management---DDR reads spelling operation and writes spelling to operate
Multi-source
figurepicture send to show needs DDR to participate in, and realizes by buffer memory
figurethe various displays of picture, have two kinds of modes of operation usually, read spelling operation and write spelling to operate.
Read spelling operation, therefore named to conceive be exactly multichannel
figurepicture reads out from DDR, then completes splicing.
figurein 5,4 tunnels
figurepicture will realize lamination, can first 4 tunnels
figurepicture write 4 pieces of DDR sections, then control to read address, read the part participating in splicing, realize lamination from 4 pieces of sections.Read to spell operation address complex management, DDR capacity requirement is large.
Write spelling operation, therefore named conceive when being exactly write DDR complete splicing, become complete one secondary time DDR reads
figurepicture reads.
figurein 6,4 width
figurepicture can put into DDR section according to stacking order, successively by controlling every width
figurethe initial write address of picture completes splicing,
figuretime picture reads, as long as regard complete as
figurepicture reads.Write spelling mode DDR address administration simple, DDR capacity requirement is little.
Four, switch stationary problem to introduce
Switch stationary problem to introduce:
figurelayer is when normally showing, and user needs to change
figurelayer, as window of windowing, disappear, roaming, laminated layer sequence adjustment etc., correspondingly CPU can issue parameter to each business board.Because parameter is a lot, and need to be distributed to bottom layer treatment module, but the configuration bus downloading speed of CPU is limited, therefore in change
figureduring layer operation, generally can exist
figuresituation shown in 7:
(1) part of module first comes into force parameter, as module 1, module n.
(2) part of module I imitates parameter, as module n, module m.
(3) to certain frame
figure, there is the possibility that the old and new's parameter coexists, as X+1 frame, cause in picture
figurethe of short duration flower screen of picture display.
(4) for show across screen display
figurepicture, as
figure" reduce+roam " in 4
figuresheet is across upper and lower two screens, if just in time these two screens, on two pieces of output boards, once the configuration start and end time of two output boards is inconsistent, will cause half range
figurepicture first upgrades, half range
figureas more news in evening.
Summary of the invention
In view of this, the invention provides one
figurelayer changes synchronous method.
Be applied to single screen
figurethe synchronous method that layer changes is:
figurein layer change process, if relate to
figurelayer changes issuing of Mating parameters, then issue this at CPU
figurebefore layer changes Mating parameters, CPU issues correspondence
figurelayer write enable shutdown signal, DDR writes administration module receiving after this writes enable shutdown signal, makes correspondence based on frame
figurethe enable switch of writing of layer is in closed condition; At this
figureafter layer change Mating parameters has issued, DDR has write administration module and has opened correspondence based on frame
figurelayer write enable switch; Further, write administration module at DDR and make correspondence based on frame
figurelayer write enable switch when being in closed condition, the end
figurerefresh module carries out the end
figurerefresh operation.
Be applied to multi-screen
figurelayer changes synchronous method and comprises: the corresponding FPGA of each screen, each FPGA comprise respective DDR and write administration module and the end
figurerefresh module; ?
figurein layer change process, if relate to
figurelayer changes issuing of Mating parameters, then issue this at CPU
figurebefore layer changes Mating parameters, CPU issues correspondence
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes corresponding based on frame
figurelayer write enable switch; At this
figureafter layer change Mating parameters has issued, CPU has issued correspondence
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, opens correspondence based on frame
figurelayer write enable switch; Further, write administration module at each DDR and make correspondence based on frame
figurelayer write enable switch close time, the end of each FPGA
figurebrush lower module carries out the end
figurerefresh operation.
Compared to prior art, single screen
figurethe synchronous method that layer changes solves
figureduring layer changes there is the problem of flower screen in single screen; Multi-screen
figurethe synchronous method that layer changes, on the basis of single screen scheme, is controlled by the heartbeat pulse shared, achieves multi-screen
figureit is synchronous that layer upgrades, and makes user have good experience.
Accompanying drawing explanation
figure1 is a kind of video synthesis platform.
figure2 is the designs of a kind of video synthesis platform framework card insert type
figure.
figure3 is that a kind of video synthesis platform back plane exchanges signal
figure.
figure4 is video synthesis platforms
figurelayer changes business example
figure.
figure5 is read spelling operation signal
figure.
figure6 is write spelling operation signal
figure.
figure7 be parameter issue with
figurepicture transport stream is to signal
figure.
figure8 is a kind of hardware design frames of the embodiment of the present invention
figure.
figure9 is the present invention
figurethe stacked sequence that puts forward switches example
figure.
figure10 is the another hardware design frames of the embodiment of the present invention
figure.
figure11 are
figurethe supporting operating process of CPU and FPGA in layer change process
figure.
Embodiment
Based on the technical matters mentioned in background technology, the present invention program mainly solves
figurein layer handoff procedure, there is not flower screen in single screen; And
figurein layer handoff procedure, show across screen display
figurelayer synchronized update.Describe in detail below by specific embodiment.
Please join
figureembodiment of the present invention hardware design frame shown in 8
figure, this hardware design
figurefor single screen
figurelayer Variation control.
figurein FPGA output board comprise DDR write administration module.In embodiments of the present invention, this DDR write administration module have control each
figurethe enable switch of layer write; When carry out
figureduring layer alter operation, CPU will issue correspondence
figurelayer writes the enable signal of opening or closing, and DDR writes after administration module receives this signal of CPU and carries out correspondence
figurelayer writes enable opening or closing.This FPGA also comprises the end
figurerefresh module, this end
figurerefresh module is used for
figureend when layer changes
figurerefresh.There is DDR to write administration module and controlled each
figurethe enable switch of layer write and the end
figureafter refresh module, carrying out
figurewhen layer changes, single screen there will not be the phenomenon of flower screen.Be described below by way of a concrete example.
Please join
figure9,
figure9 give single physics screen "
figurethe stacked sequence that puts forward changes " example that operates.In this example embodiment, DDR buffer memory divides two sections: read tablet district, one write section; Ping-pong operation is taked in reading and writing section, namely this frame write after section writes, as the read tablet district of lower frame; Relative, after this frame read tablet district runs through, write section as lower frame; Read-write operation changes based on frame.
Under normal circumstances, section content is read and write consistent.As
figure9, write section according to
figuresequence numbers 1,2,3,4 stacks, and DDR writes interface then with 1,2,3,4 order inputs
figurelayer, DDR reads interface and will to have spliced
figurepicture reads from DDR read tablet district.
In this example,
figurewhat layer change related to is
figurelayer 2 stacks the change of order.When the instruction that sends instructions under user
figureafter the order that stacks layer 2 changes, CPU issues
figurelayer 2 write enable shutdown signal, DDR writes administration module and will operate after this receiving CPU writes enable shutdown signal
figurelayer 2 write enable closedown.Must operate based on frame during closedown, otherwise
figurelayer there will be flower screen when disappearing.Close
figurewhen layer 2 is write enable, the end
figurerefresh module starts the end
figurerefresh, if do not refresh the end
figurecan cause operating
figurelayer remains in DDR section, so must use the end
figurecover, now DDR writes interface
figurelayer write sequence was the 0 (end
figure), 1,3,4.In above process, if closed
figurelayer 2 write enable while, the end
figurethe carrying out end that refresh module is enough fast
figurerefresh, DDR write interface immediately write sequence be the 0 (end
figure), 1,3,4
figurelayer, then DDR writes in section and there will not be
figurethe situation that layer 2 is residual, namely there will not be
figure9 the 2nd arrange the content shown in the 1st piece " DDR writes section content transitions ".Only have when closing
figurelayer 2 write enable after, the end
figurerefresh and start not soon, and when refreshing fast not, just there will be
figure9 the 2nd arrange the content shown in the 1st piece " DDR writes section content transitions ".But in fact this situation can not occur substantially.In the present embodiment, realize with FPGA
figurelayer writes enable opening/closing function, and starts the end while writing enable closedown
figurerefresh, because
figureafter layer writes enable closedown, release DDR write performance, the performance of release is enough to meet at the bottom of fast refresh
figure, so substantially there will not be
figure9 the 2nd arrange the content shown in the 1st piece " DDR writes section content transitions ".Because ping-pong operation is taked in DDR read-write, write section content transitions to complete in a frame, period read tablet district still maintains former content, arrange the 2nd piece with reference to the 2nd, after writing and completing transition in the frame of section one, according to ping-pong operation principle, writing section content transforming is read tablet district content, arrange the 2nd piece with reference to the 3rd, so the content that read operation reads please join the 3rd arrange the 2nd piece, what screen showed is the 3rd content arranging the 3rd piece.So said process, the content that screen shows will by four
figurelayer becomes three
figurelayer, there will not be
figurelayer 2 is residual and cause visually thinking
figurelayer changes abnormal situation and occurs.
?
figurelayer 2 writes enable being closed, and DDR writes at the bottom of the refreshing of section
figuretime, CPU will issue
figurestacked put forward sequence change Mating parameters (such as
figurelayer 2 needs to be stacked on which position etc.).Although issue this Mating parameters with
figurelayer step-out, but owing to writing enable closedown, so confusion
figurepicture can not be written in DDR buffer memory, so screen be can't see flower screen.
After this Mating parameters has issued, mean putting in place of each parameter,
figurelayer and parameter synchronous.CPU issues
figurelayer 2 writes enable opening signal, and DDR writes administration module after receiving this signal of CPU, opens based on frame
figurewriting of layer 2 is enable, write interface
figurelayer write sequence is 1,3,4,2, the DDR lamination pictures writing that the content update deposited in a frame time section is 1,3,4,2, so complete
figurethe stacked sequence that puts forward switches.On screen 4 layers
figurepicture will be normally displayed, wherein
figurelayer 2 is moved to top layer.
Above-mentioned
figurethe stacked sequence that puts forward changes issuing usually the end of at of Mating parameters
figurecomplete in the same frame time refreshed; And namely open after parameter has issued
figurewriting of layer 2 is enable, so display lacks on screen
figurelayer 2
figurepicture only continue a frame time, user experience at all less than.
Above-mentioned
figurethe stacked sequence that puts forward changes the combination can regarding disappear window operation and lamination operation as.So for the window operation that disappears, in fact can be summarized as: when needs disappear window, CPU issues the window that needs to disappear
figurelayer write enable shutdown signal, DDR writes administration module and is receiving after this writes enable shutdown signal, based on frame by the window that needs to disappear
figurelayer write enable closedown, the end
figurerefresh module carries out the end simultaneously
figurerefresh operation.And for lamination operation, on the basis disappearing window operation, issuing of lamination Mating parameters can be carried out by CPU, after this lamination Mating parameters has issued, CPU issues has needed lamination
figurelayer write enable opening signal, DDR writes administration module and receiving after this writes enable opening signal, will need lamination based on frame
figurelayer write enable opening.
According to above-mentioned
figurethe concrete operations mode that layer changes, we can draw other are comprised window, roam, embodiment that convergent-divergent changes, be specially:
When needs are windowed, CPU carries out windowing issuing of Mating parameters; After this Mating parameters of windowing has issued, CPU issues have been needed to window
figurelayer write enable opening signal, DDR writes administration module and receiving after this writes enable opening signal, will need to window based on frame
figurelayer write enable opening.
Work as needs
figurelayer roaming time, CPU issue need roaming
figurelayer write enable shutdown signal, DDR writes administration module and receiving after this writes enable shutdown signal, will need roaming based on frame
figurelayer write enable closedown, the end
figurerefresh module carries out the end simultaneously
figurerefresh operation, CPU carries out roaming issuing of Mating parameters; After this roaming Mating parameters has issued, CPU issue need roaming
figurelayer write enable opening signal, DDR writes administration module and receiving after this writes enable opening signal, will need roaming based on frame
figurelayer write enable opening.
Work as needs
figureduring layer convergent-divergent, CPU issues needs convergent-divergent
figurelayer write enable shutdown signal, DDR writes administration module and receiving after this writes enable shutdown signal, will need convergent-divergent based on frame
figurelayer write enable closedown, the end
figurerefresh module carries out the end simultaneously
figurerefresh operation, CPU carries out issuing of convergent-divergent Mating parameters; After this convergent-divergent Mating parameters has issued, CPU issues has needed convergent-divergent
figurelayer write enable opening signal, DDR writes administration module and receiving after this writes enable opening signal, will need convergent-divergent based on frame
figurelayer write enable opening.
From more than
figurethe operation that layer changes is not difficult to find, in single screen
figurein layer change process, need to perform in the following manner: if relate to
figurelayer changes issuing of Mating parameters, then issue this at CPU
figurebefore layer changes Mating parameters, CPU issues correspondence
figurelayer write enable shutdown signal, DDR writes administration module receiving after this writes enable shutdown signal, makes correspondence based on frame
figurethe enable switch of writing of layer is in closed condition; At this
figureafter layer change Mating parameters has issued, DDR has write administration module and has opened correspondence based on frame
figurelayer write enable switch; Further, write administration module at DDR and make correspondence based on frame
figurelayer write enable switch when being in closed condition, the end
figurerefresh module carries out the end
figurerefresh operation.Like this, when individual screen occurring the phenomenon of flower screen, what user saw will be smooth
figurelayer changes.
About multi-screen
figurelayer change, also namely across screen
figurelayer changes, and needs in single screen
figureon the basis that layer changes, increase the link that a heartbeat pulse detects.This heartbeat pulse is that all FPGA output boards are shared, and each plate can detect heartbeat at synchronization.
Please join
figuremulti-screen shown in 10
figurelayer Variation control hardware design frame
figure.This hardware design frame
figurewith 2 FPGA output boards, 2 physics shield and 4
figurelayer is shown as example across screen.Relative to
figuresingle screen shown in 8
figurelayer Variation control hardware design frame
figure,
figure10 mainly add the CPLD for generation of heartbeat pulse.The generation of this heartbeat pulse is controlled by CPU.This heartbeat pulse is distributed to each FPGA output board by backboard, and the DDR on each FPGA output board writes administration module and shares this heartbeat pulse, and the DDR on each FPGA output board writes administration module synchronously can detect heartbeat.Certainly, if CPU can produce heartbeat pulse can arrange CPLD.
About multi-screen
figurethe concrete operations that layer changes, can perform in the following manner:
figurein layer change process, if relate to
figurelayer changes issuing of Mating parameters, then issue this at CPU
figurebefore layer changes Mating parameters, CPU issues correspondence
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes corresponding based on frame
figurelayer write enable switch; At this
figureafter layer change Mating parameters has issued, CPU has issued correspondence
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, opens correspondence based on frame
figurelayer write enable switch; Further, write administration module at each DDR and make correspondence based on frame
figurelayer write enable switch close time, the end of each FPGA
figurebrush lower module carries out the end
figurerefresh operation.
CPU is issuing correspondence
figurelayer write enable close/open signal after, this signal will be write administration module by each DDR and receive, but the time that each DDR write administration module receives this signal may be inconsistent, do not carry out writing enable close/open based on frame immediately so each DDR writes administration module after receiving this signal, but wait for that heartbeat pulse carries out writing enable close/open based on frame after arriving again.Described in above, heartbeat pulse can be write administration module by each DDR at one time and receive, and will close/open write enable at one time so each DDR writes administration module.Each DDR write administration module close at one time write enable after, the end on each FPGA
figurethe end that refresh module is carried out
figurerefresh, CPU issues
figurelayer changes the operation of Mating parameters all by startup, so the associative operation that each FPGA relates to is all synchronous.This ensures that there multihead display
figureit is synchronous that layer upgrades.
Describe in detail lower each below again
figurethe detailed process of layer alter operation:
When needs are windowed, CPU carries out windowing issuing of Mating parameters; After this Mating parameters of windowing has issued, CPU issues have been needed to window
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, and opening based on frame needs to window
figurelayer write enable switch.
When needs disappear window, CPU issues needs the window that disappears
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes need the window that disappears based on frame
figurelayer write enable switch, the end of each FPGA
figurerefresh module carries out the end
figurerefresh operation.
Work as needs
figureduring layer roaming, CPU issues roaming
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes roaming based on frame
figurelayer write enable switch, the end of each FPGA
figurerefresh module carries out the end
figurerefresh operation; CPU carries out roaming issuing of Mating parameters; After this roaming Mating parameters has issued, CPU has issued roaming
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, opens roaming based on frame
figurelayer write enable switch.
Work as needs
figureduring layer convergent-divergent, CPU issues convergent-divergent
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes convergent-divergent based on frame
figurelayer write enable switch, the end of each FPGA
figurerefresh module carries out the end
figurerefresh operation; CPU carries out issuing of convergent-divergent Mating parameters; After this convergent-divergent Mating parameters has issued, CPU has issued convergent-divergent
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, opens convergent-divergent based on frame
figurelayer write enable switch.
Work as needs
figureduring layer laminate, CPU issues and stacks
figurelayer write enable shutdown signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, closes stack based on frame
figurelayer write enable switch, the end of each FPGA
figurerefresh module carries out the end
figurerefresh operation; CPU carries out issuing of lamination Mating parameters; After this lamination Mating parameters has issued, CPU has issued lamination
figurelayer write enable opening signal, then issue each DDR and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, opens stack based on frame
figurelayer write enable switch.
About the above-mentioned window that disappears, convergent-divergent, roaming, lamination across screen
figurelayer alter operation can be with further reference to
figurethe example of 11.But
figure11 processing procedures only providing a FPGA; The processing procedure of other FPGA and
figurefPGA in 11 is identical.From
figurein can find out, whole process FPGA, namely FPGA DDR write administration module be responsible for detect heartbeat, write enable based on frame opening/closing after heartbeat being detected.For CPU, operation logic is very simple: issue and write enable closedown → issue heartbeat pulse → undated parameter (size, coordinate, laminated layer sequence etc.) → parameter and issued → issued to write and enablely open → issue heartbeat pulse.
The present invention program based on
figurelayer writes enable opening and closing, the end
figurerefresh,
figurethe control issued of layer change parameter, achieves single screen
figurelayer changes the object of not flower screen.Further, on the basis of single screen scheme, controlled by the heartbeat pulse shared, achieve multi-screen
figureit is synchronous that layer upgrades, and makes user have good experience.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. layer changes a synchronous method, and the method is applied to single screen layer and changes, and it is characterized in that, the method comprises:
In layer change process, if relate to layer to change issuing of Mating parameters, then before CPU issues this layer change Mating parameters, what CPU issued corresponding layer writes enable shutdown signal, DDR writes administration module receiving after this writes enable shutdown signal, makes the enable switch of writing of corresponding layer be in closed condition based on frame; Change after Mating parameters issued in this layer, what DDR write that administration module opens corresponding layer based on frame writes enable switch;
Further, DDR write administration module based on frame make corresponding layer write enable switch be in closed condition time, base map refresh module carries out base map refresh operation.
2. layer as claimed in claim 1 changes synchronous method, it is characterized in that, described layer change comprise window, the roaming of the window that disappears, layer, layer convergent-divergent and figure layer laminate;
When needs are windowed, CPU carries out windowing issuing of Mating parameters; After this Mating parameters of windowing has issued, what CPU issued the layer needing to window has write enable opening signal, and DDR writes administration module and receiving after this writes enable opening signal, based on frame the layer needing to window is write enable opening;
When needs disappear window, what CPU issued the layer of the window that needs to disappear writes enable shutdown signal, DDR writes administration module and is receiving after this writes enable shutdown signal, and based on frame the layer of the window that needs to disappear write enable closedown, base map refresh module carries out base map refresh operation simultaneously;
When needs layer is roamed, CPU issue need roaming layer write enable shutdown signal, DDR writes administration module and is receiving after this writes enable shutdown signal, based on frame by need roaming layer write enable closedown, base map refresh module carries out base map refresh operation simultaneously, and CPU carries out roaming issuing of Mating parameters; After this roaming Mating parameters has issued, CPU issue need the layer of roaming write enable opening signal, DDR writes administration module and is receiving after this writes enable opening signal, writes enable opening based on frame by what need the layer of roaming;
When needs layer convergent-divergent, CPU issue need the layer of convergent-divergent write enable shutdown signal, DDR writes administration module and is receiving after this writes enable shutdown signal, enable closedown is write by what need the layer of convergent-divergent based on frame, base map refresh module carries out base map refresh operation simultaneously, and CPU carries out issuing of convergent-divergent Mating parameters; After this convergent-divergent Mating parameters has issued, CPU issue need the layer of convergent-divergent write enable opening signal, DDR writes administration module and is receiving after this writes enable opening signal, writes enable opening based on frame by what need the layer of convergent-divergent;
When needs figure layer laminate, CPU issue need the layer of lamination write enable shutdown signal, DDR writes administration module and is receiving after this writes enable shutdown signal, enable closedown is write by what need the layer of lamination based on frame, base map refresh module carries out base map refresh operation simultaneously, and CPU carries out issuing of lamination Mating parameters; After this lamination Mating parameters has issued, CPU issue need the layer of lamination write enable opening signal, DDR writes administration module and is receiving after this writes enable opening signal, writes enable opening based on frame by what need the layer of lamination.
3. layer as claimed in claim 1 or 2 changes synchronous method, it is characterized in that, described DDR write administration module based on frame open corresponding layer write enable switch after, this figure layer data write DDR buffer memory write section, this DDR buffer memory also comprises read tablet district, and this reading and writing section adopts ping-pong operation based on frame.
4. layer changes a synchronous method, and the method is applied to multi-screen layer and changes, and wherein the corresponding FPGA of each screen, each FPGA comprise respective DDR write administration module and base map refresh module, and it is characterized in that, the method comprises:
In layer change process, if relate to layer to change issuing of Mating parameters, then before CPU issues this layer change Mating parameters, what CPU issued corresponding layer writes enable shutdown signal, issue each DDR again and write the shared heartbeat pulse of administration module, each DDR writes after administration module detects heartbeat pulse at the same time, and that closes corresponding layer based on frame writes enable switch; After this layer change Mating parameters has issued, what CPU issued corresponding layer writes enable opening signal, issue each DDR again and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, and that opens corresponding layer based on frame writes enable switch;
Further, each DDR write administration module based on frame make corresponding layer write enable switch close time, the base map brush lower module of each FPGA carries out base map refresh operation.
5. layer as claimed in claim 4 changes synchronous method, it is characterized in that, described layer change comprise window, the roaming of the window that disappears, layer, layer convergent-divergent and figure layer laminate;
When needs are windowed, CPU carries out windowing issuing of Mating parameters; After this Mating parameters of windowing has issued, CPU issue need window layer write enable opening signal, issue each DDR again and write the shared heartbeat pulse of administration module, after each DDR write administration module detects heartbeat pulse at the same time, that opens the layer needing to window based on frame writes enable switch;
When needs disappear window, what CPU issued the window layer that needs to disappear writes enable shutdown signal, issue each DDR again and write the shared heartbeat pulse of administration module, after each DDR write administration module detects heartbeat pulse at the same time, that closes based on frame the window layer that needs to disappear writes enable switch, and the base map refresh module of each FPGA carries out base map refresh operation;
When needs layer is roamed, CPU issue roaming layer write enable shutdown signal, issue each DDR again and write the shared heartbeat pulse of administration module, after each DDR write administration module detects heartbeat pulse at the same time, based on frame close roaming layer write enable switch, the base map refresh module of each FPGA carries out base map refresh operation; CPU carries out roaming issuing of Mating parameters; After this roaming Mating parameters has issued, CPU issue roaming layer write enable opening signal, issue each DDR again and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, and that opens roaming layer based on frame writes enable switch;
When needs layer convergent-divergent, what CPU issued convergent-divergent layer writes enable shutdown signal, issue each DDR again and write the shared heartbeat pulse of administration module, after each DDR write administration module detects heartbeat pulse at the same time, that closes convergent-divergent layer based on frame writes enable switch, and the base map refresh module of each FPGA carries out base map refresh operation; CPU carries out issuing of convergent-divergent Mating parameters; After this convergent-divergent Mating parameters has issued, what CPU issued convergent-divergent layer writes enable opening signal, issue each DDR again and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, and that opens convergent-divergent layer based on frame writes enable switch;
When needs figure layer laminate, CPU issue stack layer write enable shutdown signal, issue each DDR again and write the shared heartbeat pulse of administration module, after each DDR write administration module detects heartbeat pulse at the same time, based on frame close stack layer write enable switch, the base map refresh module of each FPGA carries out base map refresh operation; CPU carries out issuing of lamination Mating parameters; After this lamination Mating parameters has issued, what CPU issued lamination layer writes enable opening signal, issue each DDR again and write the heartbeat pulse that administration module shares, each DDR writes after administration module detects heartbeat pulse at the same time, based on frame open stack layer write enable switch.
6. the layer as described in claim 4 or 5 changes synchronous method, it is characterized in that, described each DDR write administration module based on frame open corresponding layer write enable switch after, what described figure layer data write each DDR buffer memory writes section, each DDR buffer memory also comprises read tablet district, and described reading and writing section adopts ping-pong operation based on frame.
7. the layer as described in claim 4 or 5 changes synchronous method, it is characterized in that, described shared heartbeat pulse is that CPU produces, or produced by CPU control CPLD.
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