CN102700012A - Method for reducing silicon chip damaged layers during multi-wire cutting - Google Patents
Method for reducing silicon chip damaged layers during multi-wire cutting Download PDFInfo
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- CN102700012A CN102700012A CN201210168209XA CN201210168209A CN102700012A CN 102700012 A CN102700012 A CN 102700012A CN 201210168209X A CN201210168209X A CN 201210168209XA CN 201210168209 A CN201210168209 A CN 201210168209A CN 102700012 A CN102700012 A CN 102700012A
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Abstract
The invention relates to a method for reducing silicon chip damaged layers during multi-wire cutting, wherein a multi-wire cutting machine is adopted to cut a silicon bar, the moving speed of a worktable is 0.30-0.35mm/min, the wire moving speed is 15+/-1m/s when cutting, the wire moving speed is reduced to 12+/-1m/s when 1/5-1/3 of the silicon bar is cut, and the wire moving speed is reduced to 10+/-1m/s when 1/5-1/3 of the silicon bar is uncut. With the adoption of the method for reducing silicon chip damaged layers during multi-wire cutting, the vertical pressure is reduced by controlling the ratio of the speed of the worktable and the wire moving speed, thereby reducing the vertical pressure to obtain the silicon chip with relatively low surface damage, so that the yield is enhanced, the capacity is improved, and the cost is reduced.
Description
Technical field
The invention belongs to the cutting technique technical field of crystal silicon cell sheet, relate in particular to a kind of method that reduces multiline cut silicon chips damage layer.
Background technology
In recent years solar energy generation technology is widelyd popularize, and the processing of crystal silicon chip is important link in the production of solar module, and the machining accuracy of silicon chip, surface roughness and whole integrality are related to follow-up conversion efficiency and yields.Adopt the mode of free abrasive to carry out multi-thread cutting at present, cutting efficiency is had a revolutionary change on the one hand; On the other hand, at silicon warp, stria and surface damage very significantly improvement is arranged also.The damage layer of silicon chip is big more, just can have influence on guardian technique index---the conversion efficiency in the subsequent manufacturing processes more.Therefore, how to reduce the damage of silicon chip surface, the pressure at right angle that the crystal when just reducing to cut is suffered is that the quality of silicon chip or yield rate, electrical property are all had very important meaning.
Summary of the invention
The technical problem that the present invention will solve is: cause silicon chip damage layer major end item rate and the low technical problem of electrical property when overcoming prior art cutting silicon rod; A kind of method that reduces multiline cut silicon chips damage layer is provided; Reduce silicon chip damage layer to greatest extent; The silicon chip quality is provided, improves conversion efficiency.
The technical solution adopted for the present invention to solve the technical problems is: a kind of method that reduces multiline cut silicon chips damage layer; Adopt multi-line cutting machine that silicon rod is cut; Moving speed of table is 0.30 ~ 0.35mm/min; The steel wire Trace speed is 15 ± 1m/s when going into cutter, and the steel wire Trace speed is reduced to 12 ± 1m/s when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 Trace speed of steel wire when not cutting reduce to 10 ± 1m/s.
Translational speed when described workbench is gone into cutter is 0.30mm/min, and moving speed of table is upgraded to 0.32mm/min when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 moving speed of table when not cutting be upgraded to 0.35mm/min.
The invention has the beneficial effects as follows; The method of reduction multiline cut silicon chips damage layer of the present invention reduces pressure at right angle, to obtain the lower silicon chip of surface damage through the ratio of the control speed of table and steel wire Trace speed; Yields increases; Production capacity increases, and cost reduces, and the scanning type electron microscope observation obtains the damage layer below 5 μ m.
The specific embodiment
A kind of method that reduces multiline cut silicon chips damage layer; Adopt multi-line cutting machine that silicon rod is cut; Moving speed of table is 0.30 ~ 0.35mm/min; The steel wire Trace speed is 15 ± 1m/s when going into cutter, and the steel wire Trace speed is reduced to 12 ± 1m/s when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 Trace speed of steel wire when not cutting reduce to 10 ± 1m/s.
Translational speed when workbench is gone into cutter is 0.30mm/min, and moving speed of table is upgraded to 0.32mm/min when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 moving speed of table when not cutting be upgraded to 0.35mm/min.
Claims (2)
1. one kind is reduced the method that multiline cut silicon chips damages layer; Adopt multi-line cutting machine that silicon rod is cut; It is characterized in that: moving speed of table is 0.30-0.35mm/min; The steel wire Trace speed is 15 ± 1m/s when going into cutter, and the steel wire Trace speed is reduced to 12 ± 1m/s when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 Trace speed of steel wire when not cutting reduce to 10 ± 1m/s.
2. the method for reduction multiline cut silicon chips damage layer as claimed in claim 1; It is characterized in that: the translational speed when described workbench is gone into cutter is 0.30mm/min; Moving speed of table is upgraded to 0.32mm/min when silicon rod is accomplished 1/5 ~ 1/3 cutting, when silicon rod also surplus 1/5 ~ 1/3 moving speed of table when not cutting be upgraded to 0.35mm/min.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201210168209XA CN102700012A (en) | 2012-05-28 | 2012-05-28 | Method for reducing silicon chip damaged layers during multi-wire cutting |
Applications Claiming Priority (1)
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CN201210168209XA CN102700012A (en) | 2012-05-28 | 2012-05-28 | Method for reducing silicon chip damaged layers during multi-wire cutting |
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CN102700012A true CN102700012A (en) | 2012-10-03 |
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CN201210168209XA Pending CN102700012A (en) | 2012-05-28 | 2012-05-28 | Method for reducing silicon chip damaged layers during multi-wire cutting |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107718333A (en) * | 2017-08-24 | 2018-02-23 | 天津市环欧半导体材料技术有限公司 | A kind of technique of 60um diameters Buddha's warrior attendant wire cutting silicon |
CN110039672A (en) * | 2019-04-25 | 2019-07-23 | 内蒙古中环协鑫光伏材料有限公司 | A kind of processing technology of hexagon silicon single crystal rod |
CN112157831A (en) * | 2020-07-30 | 2021-01-01 | 长治高测新材料科技有限公司 | Semiconductor silicon slicing diamond wire cutting process for power device |
CN114603728A (en) * | 2020-12-03 | 2022-06-10 | 天津市环智新能源技术有限公司 | Solar silicon wafer and damage layer thickness control method thereof |
-
2012
- 2012-05-28 CN CN201210168209XA patent/CN102700012A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107718333A (en) * | 2017-08-24 | 2018-02-23 | 天津市环欧半导体材料技术有限公司 | A kind of technique of 60um diameters Buddha's warrior attendant wire cutting silicon |
CN110039672A (en) * | 2019-04-25 | 2019-07-23 | 内蒙古中环协鑫光伏材料有限公司 | A kind of processing technology of hexagon silicon single crystal rod |
CN112157831A (en) * | 2020-07-30 | 2021-01-01 | 长治高测新材料科技有限公司 | Semiconductor silicon slicing diamond wire cutting process for power device |
CN114603728A (en) * | 2020-12-03 | 2022-06-10 | 天津市环智新能源技术有限公司 | Solar silicon wafer and damage layer thickness control method thereof |
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Application publication date: 20121003 |