CN102687443B - Parity check control system and method and communication system and method - Google Patents
Parity check control system and method and communication system and method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
Abstract
The invention discloses parity check control system, wherein, at transmitting terminal, modulating-coding is carried out to the message part that will send and then carries out error correction coding, produce parity check thus; And at receiving terminal, error correction decoding and decode-regulating are carried out to the receiving sequence comprising message part and parity check.At transmitting terminal, the message part to modulating-coding adds stem, and being formed thus will to the block of information of error correction coding process input.Then, input this block of information to error correction coding process, produce parity check thus.Then use the value of stem to control the bit mode of parity check.
Description
Technical field
The present invention relates to parity check control system and parity check control method, and communication system and communication means, more specifically, relate to the control of the pattern to the Parity Check Bits that the error correction coding in communication produces.
Background technology
In digital communication, bit mode characteristic (balance (DC balance) such as, between 0 and the number of 1 or haul distance (number of continuous print 0 or 1)) is applied with some impacts to communication characteristic.Therefore, before transmission process, usually perform the process of converting transmission bit sequence, occur to suppress the bit mode that communication characteristic can be caused to degenerate.This conversion process is called as " modulating-coding " or " line coding ".
This technology is roughly divided into two kinds of methods: (1) uses some redundancies to perform coding, strictly to meet the method for given bit mode characteristic; And (2) perform coding by using scrambler etc., to reduce the probability of the bit mode appearance causing communication characteristic to be degenerated.
The representative of method (1) has at Ethernet
the Manchester coding of middle use and 8B/10B coding.These technology perform the conversion strictly meeting channel constraints (such as DC balance or haul distance) in units of block.In this manual, above technology is referred to as " block modulating-coding (block modulation encoding) ".Block modulating-coding produces desirable bit mode, but has the problem of redundancy increase.Such as, when 8B/10B encodes, the channel speed sending information with 10Gbps is 12.5Gbps, and thus needs the sending/receiving equipment can supporting this channel speed.Redundancy can be reduced by increasing block size, but generally speaking, along with block size increases, conversion process becomes complicated.About this, PTL 1 describes the digital data transmission system using block forecast.
The pseudo-random number sequence utilizing easy-to-install LFSR (linear feedback shift register) to produce based on the method (2) of scrambling is come transmitting bit sequence randomization.Such method for scrambling is roughly divided into wheel synchronization type and motor synchronizing type.
Synchronous method for scrambling be pseudo-random number sequence by exporting from LFSR with information sequence be added (XOR) to realize randomized method.In this synchronous method for scrambling, between transmitter side and receiver side, buffer status needs Complete Synchronization in advance.The advantage of the method is, if there is mistake (bit reversal), mistake is not propagated.In SONET (standard for multiplexing), in CCSDS (suggestion for satellite communication) etc., adopt above-mentioned synchronous method for scrambling.
Motor synchronizing method for scrambling is that the output from LFSR is produced with information sequence phase Calais the method exporting bit by bit storage by being exported in the past in LFSR.The shortcoming of the method is that bit reversal (if generation) propagates the number of the connecting line of LFSR, and advantage is not need to perform frame synchronization, to make to recover to be possible from losing synchronous (if generation).In addition, motor synchronizing scrambling has superiority in fail safe.
As based on the security threat in the method for scrambling, can consider that the network such as eliminating scrambling effect hinders input data.The initial condition of assailant's Stochastic choice LFSR in this case, to produce obstruction sequence.But, in motor synchronizing scrambling, by fully increasing LFSR length, the probability that initial condition set by assailant is consistent with actual initial condition fully can be reduced.For
motor synchronizing method for scrambling is used in 64b/66b coding.
Even when performing modulating-coding, such situation may be there is: when the S/N of such as channel is smaller time, needing to perform error correction coding.In this case, the processing sequence between modulating-coding and error correction coding becomes focus.
To this, natural scheme performs modulating-coding in lower layer, that is, after error correction coding, perform modulating-coding.
To this, PTL 2 describes the example performing the wireless communication system of modulation after performing error correction coding.
But in this case, thus receiver side performs the decoding of error correction coding afterwards in the decoding of modulation code.In block modulating-coding or motor synchronizing scrambling, error propagation may be there is when decoding.Therefore, under the state that mistake has been expanded, perform the decoding of error correction coding, this may cause the degeneration of characteristic.
Fig. 1 is the view that above state is shown.In FIG, error correction coding is applied to message part by encoder for correcting 101 by transmitter side (transmitter) 11, to produce parity check, and by modulating-coding device 102, modulating-coding is being applied to message part and parity check afterwards, to produce the transfer sequence that will send to communication path 12.Modulation code to be decoded the receiving sequence comprising message part and parity check be applied to from communication path 12 by modulation code decoding device 103 by receiver side (receiver) 13, and is applying error correction decode by error correcting code decoding device 104 afterwards.Now, the process of modulation code decoding device 103 is exaggerated the mistake occurred in receiving sequence, makes error correcting code decoding device 104 can not correct this mistake.
In order to avoid the impact of error propagation, need under zero defect state, perform modulation code decoding.For this reason, after error correction decode, preferably perform modulation code decoding.That is in this case, first transmitter side performs modulating-coding, then performs error correction coding.Now, if error correcting code is systematic code (wherein, issuing carry information part not having situation about revising), with regard to message part, channel constraints is met.But the parity check that error correction coding produces is not through modulating-coding.
In order to solve this problem, following method can be considered: determine that the parity check produced based on the information through modulating-coding is statistically fully random, and send this parity check when not revising.When simple scrambling is applied to message part, the method is considered as natural method.
On the other hand, when block modulating-coding or motor synchronizing scrambling are applied to parity check, the error propagation in the decoding of parity check can be a problem, because with regard to parity check, receiver side performs error correction decode after modulation code decoding.In order to process this problem, following method can be had: the fritter modulating-coding using zero defect to propagate to parity check, to avoid error propagation.This method is disclosed in such as NPL 1.
Fig. 2 is the view that handling process disclosed in NPL 1 is shown.
In fig. 2, modulating-coding is applied to message part by the first modulating-coding device 201 by transmitter side 11, and by encoder for correcting 202, error correction coding is being applied to modulated message part afterwards, to produce parity check.Then, the second modulating-coding device 203 uses the Modulation and Coding Scheme different from the Modulation and Coding Scheme being applied to message part to change the parity check produced by error correction coding.Parity check after conversion is sent as transmission sequence to communication path 12 together with message part.
When comprising the receiving sequence of message part and parity check from communication path 12 reception, first receiver side 13 comes to decode to parity check application of modulation code by the first modulation code decoding device 204.Because transmitter side modulating-coding device 203 have employed the method suppressing error propagation, next stage error correcting code decoding device 205 can suppress the mode of error propagation to perform error correction decode by entirety.Therefore, after error correction decode, next stage second modulation code decoding device 206 can perform the modulation code decoding of message part under zero defect state.
(reference listing)
(patent documentation)
(PTL 1)JP-A-11-243383
(PTL 2)JP-A-2009-044484
(non-patent literature)
(NPL 1)J.L.Fan and A.R.Calderbank，“A Modified ConcatenatedCoding，Scheme，with Application to Magnetic Data Storage，”IEEE Trans.Information Theory，vol.44，no.4，pp.1565-1574，1998.
Summary of the invention
(technical problem)
The bit mode of parity check is controlled to (first communication means encodes to message part application of modulation in communication means, then to message part application error correction coding) in, if have the modulating-coding of very little redundancy to message part application, then preferably also perform the conversion with less redundancy for parity check, to improve bit mode characteristic, and, be necessary to utilize the method that error propagation does not occur at receiver side.
The object of this invention is to provide the system and method overcome the above problems.
(scheme of dealing with problems)
In order to realize above object, according to the invention provides parity check control system, comprising: transmitter side, to send message part application of modulation coding, then to obtained message part application error correction coding to produce parity check; And receiver side, to the sequence application error correction decode comprising message part and parity check received and modulation code decoding.Stem is added to through the message part of modulating-coding by transmitter side, to form the block of information that will be input to error correction coding, block of information is input to error correction coding to produce parity check, and uses the value of stem to control the bit mode of parity check.
(advantageous effects of the present invention)
According to the present invention, parity check control system can be provided, in this parity check control system, when there is the modulating-coding of very little redundancy to message part application, during the bit mode of parity check controls in communication means (first to message part application of modulation coding, then performing error correction coding), also perform the conversion with less redundancy for parity check, to improve bit mode characteristic, and prevent error propagation when receiving.
Accompanying drawing explanation
Fig. 1 is the view of the impact that processing sequence in correlation technique between error correction coding and modulating-coding and mistake are shown.
Fig. 2 is the view of the impact that modulating-coding in correlation technique, processing sequence between error correction coding and parity check modulating-coding and mistake are shown.
Fig. 3 illustrates according to the first exemplary embodiment of the present invention, the view of the data format in parity check control system.
Fig. 4 illustrates according to the first exemplary embodiment of the present invention, and the parity check in parity check control system produces the view of the flow process of process.
Fig. 5 is according to the first exemplary embodiment of the present invention, the block diagram of the configuration of the transmitter side of parity check control system.
Fig. 6 is the block diagram of the configuration of the parity check control device of Fig. 5.
Fig. 7 shows the view of the handling process performed when data receiver according to the receiver side of the parity check control system of the first exemplary embodiment of the present invention.
Fig. 8 illustrates in the first exemplary embodiment of the present invention, also uses information portion to assign to perform the block diagram of the configuration that parity check controls.
Fig. 9 illustrates in the first exemplary embodiment of the present invention, also uses the statistical estimation value obtained by the modulating-coding of message part to perform the block diagram of the configuration that parity check controls.
Figure 10 illustrates to adopt when receiver side does not send the method for parity check stem, the view of the handling process performed time in parity check control system according to a second embodiment of the present invention at data receiver.
Figure 11 A to 11D is the figure of the format sample of block of information in example of the present invention, in block of information, in units of 66 bits or 65 bit blocks, message part is input to error correction coding.
Figure 12 illustrates in example of the present invention, the view of the handling process that the parity check based on two different statistical estimation values is selected.
Figure 13 A and 13B is the figure of the simulation result of the bit mode characteristic of the parity check of the example represented according to this aspect.
Embodiment
With reference to accompanying drawing, the exemplary embodiment according to parity check control system of the present invention and method and communication system and method thereof is below described.
First embodiment
Fig. 3 shows according to the first exemplary embodiment of the present invention, the data structure of the error correction code word in parity check control system.As shown in the figure, stem (being referred to as " parity check stem ") is added to the information of ovennodulation coding, being formed thus will to the block of information of error correction coding input.Then, block of information through error correction coding, thus produces parity check.The value of adjustment parity check stem, to control the bit mode of the actual parity check that will send.Although parity check stem to be placed in Fig. 3 the end of block of information, another location can be placed it in.
Fig. 4 illustrates in the present example embodiment, produces the view of the flow process of parity check stem and parity check at transmitter side.Although describe the situation of the different parity check stem of use two in the diagram, may process the situation using three or more parity check stem, this easily can find out from Fig. 8.Transmitter side handling process according to Fig. 4 is below described.
Transmitter side adds parity check stem h1 to transmission information, to produce block of information (step 401).The block of information application error correction coding that transmitter side produces in step 401, to produce parity check 1 (step 402).Then, transmitter side calculates the statistical estimation value (will describe after a while) (step S403) of parity check 1.
Transmitter side and step 401 process below performing concurrently to 403.That is transmitter side adds parity check stem h2 to transmission information, to produce block of information (step 404).The block of information application error correction coding that transmitter side produces in step 404, to produce parity check 2 (step 405).Then, transmitter side calculates the statistical estimation value (will describe after a while) (step S406) of parity check 2.
Then, in step 407, the statistical estimation value obtained in transmitter side comparison step 403 and 406, and result selects parity check stem and parity check (step 408) based on the comparison.
Statistical estimation value is the value of the bit mode characteristic representing parity check, and can be that maximum length of stroke or DC balance or its combination.Maximum length of stroke is the maximum of the length of continuous print 0 or 1 in bit mode.DC balance is the difference between the number of in bit mode 0 and the number of 1.
Although as shown in Figure 4, this example embodiment can be realized by multiple exercise error correction coding, can by using the process linearly simplifying this exemplary embodiment of error correcting code.That is the parity check only performing error correcting encoder produces process once, and adds the correct sequence according to parity check stem to obtained parity check 1, can produce corresponding parity check thus.
Fig. 5 shows above simplify processes.Correct sequence can be obtained as the parity check corresponding with following block of information: wherein message part is set to " complete zero " and has been placed through by parity check header section be added by h1 and h2 and the value obtained.
In Figure 5, transmitter side (transmitter) 51 comprises the parity production section 500 producing parity check from the information after modulating-coding.Parity production section 500 comprises temporary parity stem adding set 501, encoder for correcting 502 and parity check control device 503.The bit sequence of parity check stem h1 is added into information by temporary parity stem adding set 501, to produce the input to encoder for correcting 502.Encoder for correcting 502 to this input application error correction coding, to export parity check 1.Parity check control device 503, based on the parity check 1 exported from encoder for correcting 502, produces the parity check stem corresponding with the actual parity check that will send, and exports the actual parity check stem that will send and parity check that produce.
Fig. 6 is the block diagram of the configuration of the parity check control device 503 of Fig. 5, and Fig. 6 shows the situation of the different parity check stem of use two, the same with the situation of Fig. 4.
Parity check control device 503 shown in Fig. 6 comprises the first statistical estimation value calculation apparatus 601, second statistical estimation value calculation apparatus 602, correct sequence generation device 603, determining device 604, selector 605 and buffer 606.
First statistical estimation value calculation apparatus 601 calculates the characteristic value (statistical estimation value) of the parity check 1 exported from encoder for correcting 502, such as, and DC balance or maximum length of stroke.The interim storage parity 1 of buffer 606.
Correct sequence generation device 603 produces correct sequence, and correct sequence represents the difference between the parity check that produces from parity check stem h1 and h2.That is, can by parity check 1 and correct sequence phase Calais be obtained parity check 2.Usually, by storing correct sequence on the memory of such as ROM, and this correct sequence can be read to realize this calculating.
For with the addition by parity check 1 and correct sequence and the corresponding parity check of the parity check 2 that produces, the second statistical estimation value calculation apparatus 602 calculates the identical characteristic value (statistical estimation value) calculated with the first statistical estimation value calculation apparatus 601.
The bit mode characteristic value (statistical estimation value) that first and second statistical estimation value calculation apparatus 601 and 602 calculate by determining device 604 is compared, and determines actually should select which parity check.Generally speaking, select to balance at DC the parity check or parity check less in maximum length of stroke that are dominant in (balance between 0 and the number of 1).Then, the parity check stem selected by output.
Correct sequence selected by selector 605, and according to the parity check stem that determining device 604 is selected, correct sequence will be applied to the parity check 1 stored in buffer 606, and is added with parity check 1 by correct sequence, to produce final parity check.Fig. 6 shows following configuration: when have selected parity check stem h1, then selector exports " complete zero ", and send the parity check 1 that is stored in buffer 606 and do not make an amendment, if and have selected parity check stem h2, then correct sequence selected by selector, correct sequence is added with parity check 1 by adder, and sends the result be added.
Fig. 7 shows decoding process, and in this decoding process, the receiver side (receiver) 53 in this example embodiment obtains information, and this receiver side has received the parity check control data sent from transmitter side 51 by communication path 52.Error correction decode is applied to the receiving sequence corresponding with code word by error correcting code decoding device 701 by receiver side 53.The result of decoding is made up of message part and parity check stem.Only message part is decoded through the modulation code of modulation code decoding device 702, to obtain information.As mentioned above, receiver side 53 can obtain information and not perform special processing, and this is one of feature of this exemplary embodiment.
Although the bit mode characteristic only based on the parity check in Fig. 4 and Fig. 5 selects parity check, the present invention need not be limited to this.Such as, following method can be considered: based on the bit mode characteristic of not only parity check but also message part, select the parity check that will send.As the amendment of the configuration shown in Fig. 5, Fig. 8 shows this exemplary embodiment of the present invention.In this case, the parity check control device 803 in transmitter side parity production section 500 arranges statistical estimation value as follows.That is, for maximum length of stroke, only there are parity check stem and parity check, or when form shown in Figure 3, only have comprise message part end, parity check stem and parity check sequence be used as statistical estimation value, and for DC balance, calculate the DC balance comprising the whole code word of message part and be used as statistical estimation value.
That can revise Fig. 8 is configured to the following configuration of acquisition: use the statistical estimation value about message part to control to perform parity check, the statistical estimation value of this message part calculates when the modulating-coding for message part.Fig. 9 shows this configuration.Modulating-coding device 901 in transmitter side parity production section 500 shown in Fig. 8 provides bit mode characteristic value to parity check control device 903, such as, the DC of message part balances or the information relevant with the stroke of the bit sequence of the end of message part.Parity information device 903 carrys out counting statistics assessed value based on the bit mode of above-mentioned information and parity check.
(the second embodiment)
As the second embodiment of the present invention, following method can be considered: use parity check stem to control parity check, but do not send this parity check stem.In this case, when decoding, receiver side arranges parity check stem, and multiple exercise is decoded, and correctly determines sent parity check based on the result of decoding.
Figure 10 shows when data receiver, the handling process of receiver side 53.
At receiver side 53 place, the value of parity check stem is unknown, parity check stem 1 and 2 is placed through the first and second encoder for correcting 701a and 701b to attempt error correction decode.In Reed-Solomon code, if use the parity check stem of the value being set to different from its actual value to perform decoding, then " can not correct " from each Output rusults the first and second encoder for correcting 701a and 701b.
Decoded result determining device 1001 inputs the result of the first and second encoder for correcting 701a and 701b, select by being correctly decoded the result that obtained (in the example of Figure 10, the result of the first encoder for correcting 701a), and only to more high-rise process (namely, modulation code decoding device 702) send message part (in the case of fig. 7, do not comprise parity check stem (in the example of Figure 10, parity check stem 1)).
Example
Preferably, in the present invention the error correcting code used is the error correcting code that the bit mode of parity check significantly changes along with the small difference of the value of parity check stem.Reed-Solomon code meets this requirement.In this example, the Reed-Solomon in Galois territory GF (2^8) (symbol=8 bit) is adopted.Now, in basic Reed-Solomon code, code length as many as 255 symbols, when the parity check code of use 16 symbols, can perform the error correction of as many as 8 symbols.The primitive element (primitive element) of GF (2^8) is determined by the equation on following GF (2).
[equation 1] α ^8+ α ^4+ α ^3+ α ^2+1=0
The generator polynomial g (x) of Reed-Solomon 16 symbol parity check code can be expressed as following [equation 2].
[equation 2] g (x)=(x-α) (x-α ^2) ... (x-α ^16)
With α ^7, α ^6, α ^5, α ^4, α ^3, α ^2, α and 1 for base, the element of GF (2^8) can be represented by the vector on GF (2).Such as, in [equation 1], represent with 16 systems, α=0 × 02, α ^8=0 × 1d.
Information sequence is represented by following equation
[equation 3] U=(a (0)), a (1) ..., a (k-1)) and a (i) ∈ GF (2^8) (message length is assumed to the multiple of symbol).In the Reed-Solomon code of [equation 2], k is made to be less than 239 (k < 239).The parity check stem in the present invention is used as at use 1 bit, and using when there is end that the symbol of parity check stem as MSB be connected to U to produce the block of information of error correcting code, represent following respectively for the U1 of the U0 of the block of information in step 801 and the block of information in step 803.
[equation 4] U0=(a (0), a (1) ..., a (k-1), 0 × 00)
U1＝(a(0)，a(1)…，a(k-1)，0×80)
When parity check stem is connected to the front end of U, obtain following equation.
[equation 5] U0=(0x00, a (0), a (1) ..., a (k-1))
U1＝(0x01，a(0)，a(1)…，a(k-1))
By use symbol as the parity check stem in [equation 4] or [equation 5], registration process when sending and receive can be simplified.In this case, although can obtain as many as 255 parity check stem patterns, the number limiting bit mode based on used bit balance or maximum length of stroke is also effective.Such as, when parity check stem is 1 symbol (8 bit) and only uses two parity check stems, produce block of information according to [equation 4], wherein h1 is set to 0xaa, and h2 is set to 0x55.
[equation 6] U0=(a (0), a (1) ..., (k-1), 0xaa)
U1＝(a(0)，a(1)…，a(k-1)，0x55)
When being unit with the block of the multiple of the bit number of the symbol not being Reed-Solomon code (being 8 in this example) (situation as 64b/66b coding) to error correction coding input message part, the multiple that the length arranging parity check stem becomes the bit number of symbol with the value that the length made by merging parity check stem and message part obtains is effective.
Such as, message part GF (2^8) had in the Reed-Solomon code of 32 symbols of redundancy can have as many as 223 symbols.In this case, if message part is the multiple of 66 bit blocks, then as illustrated in figure 11 a the parity check stem of 2 bits is connected to 27 blocks, to produce the block of information be made up of 223 symbols, this block of information will be imported in error correction coding.
It is the situation of 65 bits that Figure 11 B shows the block of configuration information part each.In this case, the parity check stem of 5 bits is connected to 27 blocks, to produce the block of information be made up of 220 symbols.Figure 11 C and 11B is when using Reed-Solomon 16 symbol parity check (as many as 239 information symbols) code, the example of formatted message block.
The following describes when use is represented as Reed-Solomon code (16 parity check symbols on GF (2^8)) of the generator polynomial of [equation 2], the concrete example of the correct sequence S that will export from correct sequence generation device 603 (Fig. 6).
When the symbol comprising parity check stem being set to last symbol (the 238th symbol from 0 counts) corresponding with its maximum length of stroke in [equation 4], represent S as follows.
[equation 7] S=0x76 0x34 0x67 0x1f 0x68 0x7e 0xbb 0xe8 0x11 0x380xb7 0x31 0x64 0x51 0x2c 0x4f
In order to process the situation using three or more parity check stem, utilize the number of parity check stem to prepare statistical estimation value calculation apparatus, and correct sequence generation device 603 produce (number of parity check stem-1) correct sequence.The sequence of all generations can store in memory by correct sequence generation device 603.When there is linear relationship between parity check stem, correct sequence can be produced by the sequence phase Calais will stored in memory.
Using statistics assessed value is described below to select the example of parity check.
In the communications, generally speaking, maximum length of stroke is the smaller the better.Thus, when using maximum length of stroke as statistical estimation value, select the parity check with minimum stroke length.When using DC balance as statistical estimation value, select the parity check that the difference between the number of 0 and the number of 1 is minimum.
Statistical estimation value usually become be equal to or less than particular value time just enough.In this communication system, the method selecting parity check based on criterion can be considered.But, if having selected multiple parity check, or non-selected parity check, be then necessary to use another criterion to come to select one from multiple parity check.In this case, following methods can be utilized.
The simplest method is following method: carry out prioritization to parity check stem, and when there is multiple parity check that will select, performs selection according to priority.In addition, can Stochastic choice parity check from multiple candidate.Adopt and can reduce the people of malice by deliberately sending the threat that the bit mode causing communication characteristic to be degenerated causes system intervention with the method being difficult to the mode Stochastic choice parity check guessed.
In addition, following method can be considered: prepare two statistical estimation values (the first and second statistical estimation values), and first use the first statistical estimation value and then use the second statistical estimation value to select to perform two-stage.Handling process in this situation has been shown in Figure 12.
In fig. 12, transmitter side parity check control device checks whether the number that the first statistical estimation value meets the parity check of reference value is only 1 (step 1201).More specifically, when selecting maximum length of stroke as the first statistical estimation value, transmitter side parity check control device checks whether only has the maximum length of stroke of a parity check to be equal to or less than such as reference value M.When determining parity check in above-mentioned checking process uniquely, select associated parity stem and parity check (step 1202).Otherwise, that is the first statistical estimation value of multiple parity check meets reference value M, or the first statistical estimation value of all parity checks does not meet reference value M, then and (step 1203) is selected in the parity check performed based on the second statistical estimation value.
Figure 13 A and Figure 13 B respectively illustrates by selecting process (first statistical estimation value=maximum length of stroke (M=15) based on the parity check of Figure 12, second statistical estimation value=DC balance) perform emulation (10^6 code word), the distribution of maximum length of stroke and the distribution (=n1-L/2) of DC balance in the parity check obtained.
Use Reed-Solomon 16 symbol parity check code ([equation 2]) as error correcting code, use [equation 4] as parity check stem.
In order to compare, in Figure 13 A and 13B, also depict the result not using the convenient example of parity check stem to obtain.Be appreciated that from Figure 13 A, in this example of selection using the first statistical estimation value execution parity check based on maximum length of stroke (M=15), compared with convenient example, more effectively inhibit maximum length of stroke to become to be greater than the number of times that the parity check of 15 occurs.In addition, about the selection balanced based on DC parity check, Figure 13 B discloses and is greater than in the region of convenient example at the absolute value of DC balance, can suppress number of times some levels occurred or more in this example.
As mentioned above, according to embodiments of the invention, when using the error correcting code of such as Reed-Solomon code, even if parity check stem is 1 bit, according to the parity check stem for controlling parity check, the bit mode of parity check is significantly different, and from multiple parity check different from each other, selects the parity check with outstanding bit mode characteristic according to parity check header values, even if allow to utilize less redundancy, also significantly improve bit mode characteristic.
In addition, the receiver side receiving the data produced in the present embodiment abandons parity check stem simply after decoding and error code, thus prevents the generation of error propagation.
Above-mentioned parity check control system and parity check control method can be realized by hardware, software or its combination.
Such as, although above-mentioned parity check control system can pass through hardware implementing, it can be read for allowing computer be used as the program of this system and perform this program to realize from computer readable recording medium storing program for performing by computer.
Although above-mentioned parity check control method can pass through hardware implementing, it can be read for allowing computer perform the program of the method and perform this program to realize from computer readable recording medium storing program for performing by computer.
In addition, above hardware configuration or software merit rating are not particularly limited, as long as but the function of above assembly can be realized, then can apply any hardware configuration or software merit rating.Such as, following configuration can be adopted: each assembly forms the configuration of the independent function of said apparatus, or the configuration of its multiple function integrated.
Above disclosed exemplary embodiment can be described as following complementary annotations in whole or in part, but be not limited thereto.
(complementary annotations 1) a kind of parity check control system, comprising: transmitter side, to send message part application of modulation coding, then to obtained message part application error correction coding to produce parity check; And receiver side, to the sequence application error correction decode comprising message part and parity check received and modulation code decoding, stem is added to through the message part of modulating-coding by transmitter side, to form the block of information that will be input to error correction coding, block of information is input to error correction coding to produce parity check, and uses the value of stem to control the bit mode of parity check.
(complementary annotations 2) parity check control system according to complementary annotations 1, wherein, transmitter side performs parity check by following operation and controls: produce multiple parity check according to the value of stem, for each in parity check, calculate the statistical estimation value determined by the bit mode of parity check, and select parity check based on calculated statistical estimation value.
(complementary annotations 3) parity check control system according to complementary annotations 2, wherein, statistical estimation value is maximum length of stroke, and maximum length of stroke is the maximum of the occurrence number of continuous print 0 or 1 in the bit mode of parity check.
(complementary annotations 4) parity check control system according to complementary annotations 2, wherein, statistical estimation value is DC balance, and DC balance is in the bit mode of parity check, the difference between the occurrence number of 0 and the occurrence number of 1.
(complementary annotations 5) parity check control system according to complementary annotations 1 or complementary annotations 2, wherein, transmitter side comprises: temporary parity stem adding set, adds fixing stem to produce block of information to the message part that will send; Encoder for correcting, calculates the parity check of the block of information that temporary parity stem adding set produces; And parity check control device, parity check input parity check control device, calculate the parity check of the block of information being added with stem based on input, described stem is different from the stem that temporary parity stem adding set has added, and selects the stem that will send and parity check.
(complementary annotations 6) parity check control system according to complementary annotations 5, wherein, parity check control device comprises: statistical estimation value calculation apparatus, calculates the characteristic value of parity check; Correct sequence generation device, the stem of adding for temporary parity stem adding set and parity check, produce correct sequence, and described correct sequence is used for producing the parity check corresponding from described different stem at this moment; And determining device, the characteristic value of each parity check that Corpus--based Method assessed value calculation element produces determines the stem that will send and parity check.
(complementary annotations 7) parity check control system according to any one of complementary annotations 1 to 6, wherein, after error correction decode, receiver side abandons stem and sends message part to more high-rise process.
(complementary annotations 8) parity check control system according to complementary annotations 6, wherein, statistical estimation value calculation apparatus also uses information portion to assign to calculate the characteristic value of parity check.
(complementary annotations 9) parity check control system according to complementary annotations 6, wherein, statistical estimation value calculation apparatus is also used in the statistical estimation value that is applied to and calculates in the modulating-coding of message part to calculate the characteristic value of parity check.
(complementary annotations 10) parity check control system according to any one of complementary annotations 1 to 9, wherein, transmitter side does not send stem, and receiver side performs repeatedly error correction decode according to the pattern of stem.
(complementary annotations 11) parity check control system according to any one of complementary annotations 1 to 10, wherein, the error correcting code used in error correction coding is Reed-Solomon code, and is the multiple of the bit number of the symbol of Reed-Solomon code by the value that the size of the size and message part that merge parity check stem obtains.
(complementary annotations 12) parity check control system according to complementary annotations 2, wherein, transmitter side selects statistical estimation value to meet the parity check of reference value given separately.
(complementary annotations 13) parity check control system according to complementary annotations 12, wherein, when transmitter side have selected multiple parity check or non-selected parity check, the transmitter side parity check that Stochastic choice is final from multiple parity check.
(complementary annotations 14) parity check control system according to complementary annotations 12, wherein, transmitter side prepares the second statistical estimation value, and when transmitter side have selected multiple parity check or non-selected parity check, transmitter side selects parity check based on the second statistical estimation value from multiple parity check.
(complementary annotations 15) a kind of communication system, uses the parity check control system according to any one of complementary annotations 1 to 14 to carry out executive communication.
(complementary annotations 16) a kind of parity check control method, comprising: at transmitter side, to send message part application of modulation coding, then to obtained message part application error correction coding to produce parity check; And at receiver side, to the sequence application error correction decode comprising message part and parity check received and modulation code decoding, stem is added to through the message part of modulating-coding by transmitter side, to form the block of information that will be input to error correction coding, block of information is input to error correction coding to produce parity check, and uses the value of stem to control the bit mode of parity check.
(complementary annotations 17) parity check control method according to complementary annotations 16, wherein, transmitter side performs parity check by following operation and controls: produce multiple parity check according to the value of stem, for each in parity check, calculate the statistical estimation value determined by the bit mode of parity check, and select parity check based on calculated statistical estimation value.
(complementary annotations 18) parity check control method according to complementary annotations 17, wherein, statistical estimation value is maximum length of stroke, and maximum length of stroke is the maximum of the occurrence number of continuous print 0 or 1 in the bit mode of parity check.
(complementary annotations 19) parity check control method according to complementary annotations 17, wherein, statistical estimation value is DC balance, and DC balance is the difference between the occurrence number of in the bit mode of parity check 0 and the occurrence number of 1.
(complementary annotations 20) parity check control method according to complementary annotations 16 or complementary annotations 17, wherein, transmitter side performs: temporary parity stem adds process, adds fixing stem to produce block of information to the message part that will send; Error correction coding process, calculates temporary parity stem and adds the parity check processing the block of information produced; And parity check control treatment, parity check is inputted parity check control treatment, the parity check of the block of information being added with stem is calculated based on input, described stem is different from temporary parity stem and adds and process the stem of having added, and selects the stem that will send and parity check.
(complementary annotations 21) parity check control method according to complementary annotations 20, wherein, parity check control treatment comprises: the computing of statistical estimation value, calculates the characteristic value of parity check; Correct sequence produces process, adds the stem and parity check that process and add, produce correct sequence for temporary parity stem, and described correct sequence is used for producing the parity check corresponding from described different stem at this moment; And determine process, the characteristic value of each parity check that the computing of Corpus--based Method assessed value produces determines the stem that will send and parity check.
(complementary annotations 22) parity check control method according to any one of complementary annotations 16 to 21, wherein, after error correction decode, receiver side abandons stem and sends message part to more high-rise process.
(complementary annotations 23) parity check control method according to complementary annotations 21, wherein, the computing of statistical estimation value also uses information portion to assign to calculate the characteristic value of parity check.
(complementary annotations 24) parity check control method according to complementary annotations 21, wherein, the computing of statistical estimation value is also used in the statistical estimation value that is applied to and calculates in the modulating-coding of message part to calculate the characteristic value of parity check.
(complementary annotations 25) parity check control method according to any one of complementary annotations 16 to 24, wherein, transmitter side does not send stem, and receiver side performs repeatedly error correction decode according to the pattern of stem.
(complementary annotations 26) parity check control method according to any one of complementary annotations 16 to 25, wherein, the error correcting code used in error correction coding is Reed-Solomon code, and is the multiple of the bit number of the symbol of Reed-Solomon code by the value that the size of the size and message part that merge parity check stem obtains.
(complementary annotations 27) parity check control method according to complementary annotations 17, wherein, transmitter side selects statistical estimation value to meet the parity check of reference value given separately.
(complementary annotations 28) parity check control method according to complementary annotations 27, wherein, when transmitter side have selected multiple parity check or non-selected parity check, the transmitter side parity check that Stochastic choice is final from multiple parity check.
(complementary annotations 29) parity check control method according to complementary annotations 27, wherein, transmitter side prepares the second statistical estimation value, and when transmitter side have selected multiple parity check or non-selected parity check, transmitter side selects parity check based on the second statistical estimation value from multiple parity check.
(complementary annotations 30) a kind of communication means, uses the parity check according to any one of complementary annotations 16 to 29 to control to send executive communication.
Although reference example embodiment describes the present invention, the present invention is not limited thereto.In addition, within the scope of the present invention, the various amendments that can those skilled in the art will appreciate that configuration of the present invention or details.
The application is based on Japanese patent application No.2009-242435 (on October 21st, 2009 submits) and require its priority, is incorporated to herein by the full content of this application with reform.
(industrial applicibility)
The present invention is suitable for being applied to the parity check control system in optical communication and parity check control method, and uses this parity check control system and parity check control method to come communication system and the communication means of executive communication.
(list of numerals)
11,51: transmitter side (transmitter)
12,52: communication path
13,53: receiver side (receiver)
101: encoder for correcting
102: modulating-coding device
103: modulation code decoding device
104: error correcting code decoding device
201: the first modulating-coding devices
202: encoder for correcting
203: the second modulating-coding devices
204: the first modulation code decoding devices
205: error correcting code decoding device
206: the second modulation code decoding devices
500: parity production section
501: temporary parity stem adding set
502: encoder for correcting
503,803,903: parity check control device
601: the first statistical estimation value calculation apparatus
602: the second statistical estimation value calculation apparatus
603: correct sequence generation device
604: determining device
605: selector
606: buffer
901: modulating-coding device
1001: decoded result determining device
Claims (19)
1. a parity check control system, comprising:
Transmitter side, comprising:
Modulating-coding device, for encoding to message part application of modulation;
Stem adding set, for adding parity check stem, to produce the block of information comprising message part and parity check stem to the message part through modulating-coding;
Encoder for correcting, for the block of information application error correction coding comprising message part and parity check stem, to produce parity check;
Control device, for the bit mode by selecting the value of parity check stem to control parity check, wherein, described control device performs the control of the bit mode of parity check by following operation: produce the multiple parity checks corresponding with multiple different values of parity check stem, for each in described multiple parity check, calculate the statistical estimation value determined by the bit mode of parity check, and select parity check based on the statistical estimation value of calculated described multiple parity check; And
Dispensing device, for sending the sequence comprising at least message part and parity check, and
Receiver side, comprising:
Receiving system, for receiving sequence;
Error correction decoding device, for receiving sequence application error correction decoding; And
Decode-regulating device, for decoding to the receiving sequence application of modulation through error correction decoding.
2. parity check control system according to claim 1, wherein
Described statistical estimation value is maximum length of stroke, and described maximum length of stroke is the maximum of the occurrence number of continuous print 0 or 1 in the bit mode of parity check.
3. parity check control system according to claim 1, wherein
Described statistical estimation value is DC balance, and described DC balance is the difference between the occurrence number of in the bit mode of parity check 0 and the occurrence number of 1.
4. parity check control system according to claim 1, wherein
Described stem adding set adds fixing parity check stem, to produce the block of information comprising message part and fixing parity check stem to the message part through modulating-coding;
Described encoder for correcting to the block of information application error correction coding comprising message part and fixing parity check stem, to produce the first parity check; And
Described control device produces at least one second parity check based on described first parity check, at least one second parity check described with by comprise message part and be different from fixing parity check parity check stem block of information application error correction coding and the parity check that obtains is identical, and any one in selection the first parity check sum second parity check.
5. parity check control system according to claim 4, wherein
Described control device comprises:
Correct sequence generation device, at least producing correct sequence;
Multiple statistical estimation value calculation apparatus, each statistical estimation value calculation apparatus is for calculating the statistical estimation value determined by the bit mode of parity check;
Determining device, the statistical estimation value for calculating based on each statistical estimation value calculation apparatus determines the parity check that will send; And
Adder, for not only based on described first parity check, and at least produces at least one second parity check described based on correct sequence.
6. parity check control system according to claim 1, wherein
At receiver side, even if parity check stem is included in receiving sequence, after described error correction decoding device performs error correction decoding, abandon parity check stem, described decode-regulating device is not decoded to parity check stem application of modulation.
7. parity check control system according to claim 1, wherein
Not only by the bit mode of parity check, and assigned to determine statistical estimation value by information portion.
8. parity check control system according to claim 1, wherein
Not only by the bit mode of parity check, and by the information obtained from described modulating-coding device to determine statistical estimation value.
9. parity check control system according to claim 1, wherein
The sequence sent does not comprise parity check stem, and
Described error correction decoding device while different parity check stem is added in inside, repeatedly to the receiving sequence application error correction decoding not comprising parity check stem.
10. parity check control system according to claim 1, wherein
The error correcting code used in error correction coding and decoding is Reed-Solomon code, and
The value obtained by the size of the size and message part that merge parity check stem is the multiple of the bit number of the symbol of Reed-Solomon code.
11. parity check control system according to claim 1, wherein
Described transmitter side selects statistical estimation value to meet the parity check of reference value given separately.
12. parity check control system according to claim 11, wherein
When described transmitter side have selected multiple parity check or non-selected parity check, the parity check that Stochastic choice is final from multiple parity check of described transmitter side.
13. parity check control system according to claim 11, wherein
Described transmitter side prepares the second statistical estimation value, and when described transmitter side have selected multiple parity check or non-selected parity check, described transmitter side selects parity check based on described second statistical estimation value from multiple parity check.
14. 1 kinds of communication systems, use parity check control system according to claim 1 to carry out executive communication.
15. 1 kinds of parity check control methods, comprising:
At transmitter side, to send message part application of modulation coding, then to produced message part application error correction coding to produce parity check, and
At receiver side, to the sequence application error correction decode comprising message part and parity check received and modulation code decoding,
Stem is added to through the message part of modulating-coding by described transmitter side, to form the block of information that will be input to error correction coding, described block of information is input to error correction coding to produce parity check, and by producing the multiple parity checks corresponding with multiple different values of parity check stem, for each in described multiple parity check, calculate the statistical estimation value determined by the bit mode of parity check, and select parity check based on the statistical estimation value of calculated described multiple parity check, use the value of stem to control the bit mode of parity check.
16. 1 kinds of communication meanss, use parity check control method according to claim 15 to carry out executive communication.
17. 1 kinds of transmitter side equipment, comprising:
Modulating-coding device, for encoding to message part application of modulation;
Stem adding set, for adding parity check stem, to produce the block of information comprising message part and parity check stem to the message part through modulating-coding;
Encoder for correcting, for the block of information application error correction coding comprising message part and parity check stem, to produce parity check;
Control device, for the bit mode by selecting the value of parity check stem to control parity check, wherein, described control device performs the control of the bit mode of parity check by following operation: produce the multiple parity checks corresponding with multiple different values of parity check stem, for each in described multiple parity check, calculate the statistical estimation value determined by the bit mode of parity check, and select parity check based on the statistical estimation value of calculated described multiple parity check; And
Dispensing device, for sending the sequence comprising at least message part and parity check.
18. 1 kinds of receiver side equipment, comprising:
Receiving system, for receiving the sequence comprising at least message part and parity check;
Error correction decoding device, for receiving sequence application error correction decoding; And
Decode-regulating device, for decoding to the receiving sequence application of modulation through error correction decoding, wherein
Even if parity check stem is included in receiving sequence, after described error correction decoding device performs error correction decoding, abandon parity check stem, described decode-regulating device is not decoded to parity check stem application of modulation.
19. 1 kinds of receiver side equipment, comprising:
Receiving system, for receiving the sequence comprising at least message part and parity check;
Error correction decoding device, for receiving sequence application error correction decoding; And
Decode-regulating device, for decoding to the receiving sequence application of modulation through error correction decoding,
Wherein
Receiving sequence does not comprise parity check stem, and
Described error correction decoding device while different parity check stem is added in inside, repeatedly to the receiving sequence application error correction decoding not comprising parity check stem.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2009242435 | 2009-10-21 | ||
| JP2009-242435 | 2009-10-21 | ||
| PCT/JP2010/068139 WO2011049014A1 (en) | 2009-10-21 | 2010-10-15 | Parity control system and method, and communication system and method |
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| CN102687443A CN102687443A (en) | 2012-09-19 |
| CN102687443B true CN102687443B (en) | 2015-10-07 |
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| JPS61100059A (en) * | 1984-10-22 | 1986-05-19 | Nippon Telegr & Teleph Corp <Ntt> | Coding system |
| JP3077639B2 (en) * | 1997-08-27 | 2000-08-14 | 日本電気株式会社 | Error correction balanced code transmission / reception system |
| JP4321175B2 (en) * | 2003-08-13 | 2009-08-26 | 富士ゼロックス株式会社 | Signal transmission system with error correction code |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1788446A (en) * | 2003-05-19 | 2006-06-14 | 松下电器产业株式会社 | Error correction encoding/decoding apparatus and error correction encoding/decoding method |
| CN1828754A (en) * | 2005-01-31 | 2006-09-06 | 日立环球储存科技荷兰有限公司 | Techniques for implementing non-uniform constraints in modulation encoded data |
| JP2007306212A (en) * | 2006-05-10 | 2007-11-22 | Fuji Xerox Co Ltd | Transmitter, receiver, communication system, and communication method |
| JP2009111941A (en) * | 2007-11-01 | 2009-05-21 | Panasonic Corp | Wireless transmission device and wireless reception device |
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| WO2011049014A1 (en) | 2011-04-28 |
| CN102687443A (en) | 2012-09-19 |
| JPWO2011049014A1 (en) | 2013-03-14 |
| JP5724877B2 (en) | 2015-05-27 |
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