JPS61100059A - Coding system - Google Patents

Coding system

Info

Publication number
JPS61100059A
JPS61100059A JP59221592A JP22159284A JPS61100059A JP S61100059 A JPS61100059 A JP S61100059A JP 59221592 A JP59221592 A JP 59221592A JP 22159284 A JP22159284 A JP 22159284A JP S61100059 A JPS61100059 A JP S61100059A
Authority
JP
Japan
Prior art keywords
code
bch
pattern
bits
error correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59221592A
Other languages
Japanese (ja)
Inventor
Seizo Onoe
誠蔵 尾上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59221592A priority Critical patent/JPS61100059A/en
Publication of JPS61100059A publication Critical patent/JPS61100059A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/31Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To improve DC balancing characteristics by applying coding so as not to transmit a part or all of patterns on the proposition that the decoding is applied while the part of pattern not transmitted yet is added at the reception. CONSTITUTION:In a code format using a BCH(23,12) code, 4 bits shown in B of K=12 bits is set to a pattern of [0101] in advance and the remaining 8-bit shown A is used for information. Since each 1 bit of 0, 1 exists in the part B, the information points in 12 bits of the BCH(23,12) code do not go to all 1 nor to all 0. No all 0, all 1 is not included even after error correction coding by the BCH code and a code whose mark rate is concentrated nearly on 50% is obtained.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は、誤り訂正符号を用いるディジタル信号伝送に
用いられる直流平衡特性の良い符号化方式に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a coding system with good DC balance characteristics used in digital signal transmission using error correction codes.

(従来技術) 誤り訂正符号化された符号系列には、オール「0」、あ
るいはオール「1」が含まれており、直流平衡が良好で
はない。直流遮断を行う伝送路てこのような符号を伝送
するためには、さらに直流平衡符号化を行う必要があっ
た。例えば、スプリットフェーズ符号は「0」に「Ol
」を「1」に「lO」を対応させるもので、これにより
完全    ・な直流平衡がとれるが、冗長度が増加す
るため、効率がさらに%となり、しかも、効率を落とす
ことを信頼度を上げるために利用することは不合理であ
る。このように、従来の方法では必ずしも、効率的な直
流平衡特性を持つ誤り訂正符号化方式を実現するもので
はないという欠点があった。
(Prior Art) A code series subjected to error correction encoding includes all "0"s or all "1s" and does not have good DC balance. In order to transmit such a code through a transmission line that cuts off DC, it is necessary to perform DC balanced encoding. For example, the split phase code is set to ``0'' to ``Ol''.
” corresponds to “1” and “lO”. This allows perfect DC balance to be achieved, but as redundancy increases, the efficiency further increases by %, and moreover, reducing efficiency increases reliability. It is unreasonable to use it for this purpose. As described above, the conventional method has the drawback that it does not necessarily realize an error correction encoding system with efficient DC balance characteristics.

(発明の目的) 本発明は、直流平衡特性の劣る符号系列を含まず直流遮
断伝送路への適用性の良い誤り訂正符号化方式を提供す
るものである。
(Objective of the Invention) The present invention provides an error correction encoding system that does not include a code sequence with poor DC balance characteristics and is highly applicable to DC cut-off transmission lines.

(発明の構成及び作用) 以下図面により本発明の詳細な説明する。(Structure and operation of the invention) The present invention will be explained in detail below with reference to the drawings.

図1に本発明の実施例の符号フォーマットを示す。誤り
訂正符号としてボーズチョードリホツケンゲム符号(B
ose−Chaudhuri Hocquenghem
 Code。
FIG. 1 shows a code format according to an embodiment of the present invention. Bose Chowdhury Hotsukem code (B) is used as an error correction code.
ose-Chaudhuri Hocquenghem
Code.

以下BC,H符号という)で符号長n=23.情報点数
に=12のBCI((23,12)符号を用いた実施例
である。
(hereinafter referred to as BC, H code), code length n=23. This is an example using a BCI ((23, 12) code with a number of information points of =12).

この実施例においてはに=12ビットのうち、図中のB
で示す4ビットは予めro 101Jというパタンに定
めておき、残りのAで示す8ビットを情報として使用す
る。このA、Bを情報ビットとして、生成多項式G(x
)=1+x+x’+xh+x’+x9+x”によるチェ
ックビットCを生成して符号構成する。チェックビット
の作り方はよく知られている手段であり、A、Bの情報
を符号多項式F (x)と表し、xII・F (x)を
G (x)で−割った剰余多項式として求められる。
In this embodiment, out of 12 bits, B in the figure is
The 4 bits indicated by are previously set in a pattern of ro 101J, and the remaining 8 bits indicated by A are used as information. Using A and B as information bits, the generator polynomial G(x
) = 1 + x + x' +・It is obtained as the remainder polynomial obtained by dividing F (x) by -G (x).

以上のように符号が構成され、Bの部分にはrOJ、r
lJが少なくとも1ビットずつ存在するので、BCH(
23、12)符号の12ビットの情報点がオール「0」
、オール「1」になることはない。
The code is constructed as described above, and the part B contains rOJ, r
Since lJ exists at least 1 bit each, BCH(
23, 12) The 12-bit information points of the code are all “0”
, it will never be all "1".

このように情報点のパタンにオール「0」、オール「1
」を含まないために、これをBCH符号による誤り訂正
符号化を行うと、直流平衡特性はさらに改善される。
In this way, the pattern of information points is all “0” and all “1”.
'', the DC balance characteristic is further improved by performing error correction encoding using a BCH code.

1    ゛  0     ゛ 4   ゛  0     ′ 5    :  0     ; 22  °  0     ゛ これを説明するために、表1にBCH(23,12)符
号の符号の重み分布を示す。符号の重みとは符号の中の
「1」の数であるので、符号の重みを符号長で割ったも
のがその符号のマーク率を表している。
1 ゛ 0 ゛ 4 ゛ 0 ' 5 : 0 ; 22 ° 0 ゛ To explain this, Table 1 shows the code weight distribution of the BCH (23, 12) code. Since the weight of a code is the number of "1"s in the code, the weight of the code divided by the code length represents the mark rate of that code.

表1に示されるようにBCH(23,12)符号には、
オール「0」、オール「1」が含まれており、これが符
号の重み0,23となりマーク率O%1100%で直流
平衡特性が非常に劣る。しかしこれを除けば、マーク率
は30%〜70%に集中している。このことは、誤り訂
正符号の性質より次のように説明することができる。す
なわちBCH符号は線形符号であるのでオール「0」を
符号として含むことは定義より明らかであり、また巡回
符号の一種であることより、オール「1」も符号として
含むことが証明できる。従って、符号間距離が7であれ
ば(BCH(23,12)符号は7である〕、オール「
0」に最も近い符号でも符号の重みは7であり、それよ
り小さい重みの符号は存在しない。オール「1」に対し
ても同様で重みが16より大きい符号は存在しない。本
発明においては、情報点のパタンにオール「0」、オー
ル「1」を含まないので、誤り訂正符号化を行った後に
も、オール「0」、オール「1」は含まれず、マーク率
が50%の近くに集中した符号が得られる。本実施例で
は、図に示すBの部分は予め定まったパタンであるから
、この部分は必ずしも送信する必要はなく、受信側で付
加してもよい。このように、情報点の一部を予め約束し
たパタンとし、その部分は送信せずに受信側で付加する
方法はある誤り訂正符号から情報点数が小さい誤り訂正
符号を作る方法で短縮化符号として知られているが従来
の方法では符号化、復号化が簡単なことのみに着目し、
約束するパタンとしてオール「0」を用いている。本発
明は、直流平衡をとるために、この部分に少なくとも「
0」。
As shown in Table 1, the BCH (23, 12) code has:
All "0" and all "1" are included, and the code weights are 0 and 23, and the mark rate is 1100%, and the DC balance characteristic is very poor. However, excluding this, the mark rate is concentrated between 30% and 70%. This can be explained from the nature of error correction codes as follows. That is, since the BCH code is a linear code, it is clear from the definition that it includes all "0"s as a code, and since it is a type of cyclic code, it can be proven that it also includes all "1s" as a code. Therefore, if the inter-symbol distance is 7 (BCH (23, 12) code is 7), then all "
Even the code closest to "0" has a code weight of 7, and there is no code with a smaller weight than that. Similarly for all "1"s, there is no code with a weight greater than 16. In the present invention, since the information point pattern does not include all "0" and all "1", even after error correction encoding, all "0" and all "1" are not included, and the mark rate is A code concentrated near 50% is obtained. In this embodiment, since the part B shown in the figure is a predetermined pattern, this part does not necessarily need to be transmitted, and may be added on the receiving side. In this way, a method in which a part of the information points is made into a predetermined pattern and that part is added on the receiving side without being transmitted is a method that creates an error correction code with a small number of information points from a certain error correction code, and is used as a shortened code. Although it is known, conventional methods focus only on the fact that encoding and decoding are easy.
All "0" is used as the promising pattern. In order to achieve direct current balance, the present invention provides at least "
0".

「1」を1ビットずつ以上存在するようにパタンを約束
するものである。約束するパタンの長さが4以上の時は
、パタンとして、「0」とrlJO数の差が高々1とな
るように設定するのが望ましい。
This guarantees a pattern such that one or more bits of "1" exist. When the length of the promised pattern is 4 or more, it is desirable to set the pattern so that the difference between "0" and the number of rlJOs is at most 1.

前述の説明かられかるように、マーク率を50%の近く
のみに集中させるためには符号間距離が符号長の半分に
近い誤り訂正符号を用いればよい。
As can be seen from the above explanation, in order to concentrate the mark rate near 50%, it is sufficient to use an error correction code in which the inter-symbol distance is close to half the code length.

図2にBCH(15,5)符号を用いた実施例を示す。FIG. 2 shows an example using a BCH (15,5) code.

この実施例ではBの部分も送信する場合を示した。In this embodiment, a case is shown in which part B is also transmitted.

BC[((15,5)符号は符号長が15で符号間距離
が7であるので、表2に示すように重み分布は、重み0
゜15を除く外は7と8に集中している。従って本実施
例においては、マーク率が50%±3.3%に集中した
直流平衡にすぐれた符号が得られる。
BC[((15,5) code has a code length of 15 and an inter-code distance of 7, so as shown in Table 2, the weight distribution is
Except for ゜15, they are concentrated in 7 and 8. Therefore, in this embodiment, a code with excellent DC balance in which the mark ratio is concentrated at 50%±3.3% is obtained.

本発明℃はマーク率を50%に集中するためには符号間
距離を大きくとる必要があり、符号の能率を落とすが、
その代償として誤り訂正能力が強くなる。従って、直流
平衡をとるために増加した冗長度が信頼度の向上のため
にも有効に利用されている。
In the present invention, in order to concentrate the mark rate at 50%, it is necessary to increase the distance between codes, which reduces code efficiency.
In return, the error correction ability becomes stronger. Therefore, the increased redundancy for DC balancing is also effectively used to improve reliability.

以上は、巡回符号としてBC)l符号について説明した
が、R5符号(Reed−5olomon Code 
)を含む非2元BCH符号又はFire符号の如き巡回
符号を用いる場合にも本発明は適用可能である。
The above describes the BC)l code as a cyclic code, but the R5 code (Reed-5olomon Code)
) or a cyclic code such as a Fire code.

(発明の効果) 以上説明したように、本発明の符号化方式においては、
オール「0」、オール「1」のパタンを含まず、マーク
率が50%に集中した符号が得られ。
(Effect of the invention) As explained above, in the encoding method of the present invention,
A code that does not include patterns of all "0" and all "1" and whose mark rate is concentrated at 50% is obtained.

るので、直流遮断伝送路への適用性が良い。例えば、移
動通信方式においては、周波数ドリフトの影響を避ける
ため等の理由から、直流遮断を行うので、本発明を有効
に利用することができる。従来の方法では、スプリント
フェーズ符号、サブキャリアFM等により直流平衡をと
っていたが、本発明を用いてマーク率を50%に集中さ
せてNRZのまま変調することも可能である。また、符
号の能率をあまり落とさずにマーク率の集中度が良くな
い場合でも、スプリットフェーズ符号のように直流平衡
特性の強力な符号化を用いる必要はな(、直流平衡特性
はやや劣るものでもっと効率の良い直流平衡符号化を併
用すれば、最適な通信システムを提供することが可能で
ある。
Therefore, it has good applicability to DC cut-off transmission lines. For example, in a mobile communication system, direct current is cut off in order to avoid the influence of frequency drift, so the present invention can be effectively utilized. In the conventional method, DC balance was achieved using a sprint phase code, subcarrier FM, etc., but using the present invention, it is also possible to concentrate the mark rate at 50% and modulate as NRZ. Also, even if the concentration of mark rates is not good without reducing the efficiency of the code too much, there is no need to use encoding with strong DC balance characteristics like the split phase code (although the DC balance characteristics are somewhat inferior). If more efficient DC balanced encoding is also used, it is possible to provide an optimal communication system.

【図面の簡単な説明】[Brief explanation of drawings]

図1は本発明の実施例としてBCH(23,12)符号
の例を示すフォーマント、図2は本発明の実施例として
BCH(15,5)符号の例を示すフォーマットである
FIG. 1 shows a formant showing an example of a BCH (23, 12) code as an embodiment of the present invention, and FIG. 2 shows a format showing an example of a BCH (15, 5) code as an embodiment of the invention.

Claims (1)

【特許請求の範囲】[Claims] 組織(n、k)符号を用いる符号化方式において、情報
ビット数にのうち2ビット以上は「0」と「1」が少な
くとも1ビットずつ存在する一定のパタンとし、受信側
で当該パタンのうち送信しなかった部分を付加して復号
を行うことを前提として当該パタンの全部または一部(
空集合を含む)は送信しないように符号化することを特
徴とする符号化方式。
In an encoding method using a systematic (n, k) code, two or more of the information bits are a certain pattern in which there is at least one "0" and one "1" bit, and the receiving side The entire or part of the pattern (
An encoding method characterized by encoding such that data (including empty sets) are not transmitted.
JP59221592A 1984-10-22 1984-10-22 Coding system Pending JPS61100059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59221592A JPS61100059A (en) 1984-10-22 1984-10-22 Coding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59221592A JPS61100059A (en) 1984-10-22 1984-10-22 Coding system

Publications (1)

Publication Number Publication Date
JPS61100059A true JPS61100059A (en) 1986-05-19

Family

ID=16769168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59221592A Pending JPS61100059A (en) 1984-10-22 1984-10-22 Coding system

Country Status (1)

Country Link
JP (1) JPS61100059A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05153198A (en) * 1991-11-27 1993-06-18 Nec Corp Cyclic redundancy checking method and transmitter and receiver
WO2007046491A1 (en) * 2005-10-20 2007-04-26 Nec Corporation Mram and its operation method
JP5724877B2 (en) * 2009-10-21 2015-05-27 日本電気株式会社 Parity control system and method, and communication system and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05153198A (en) * 1991-11-27 1993-06-18 Nec Corp Cyclic redundancy checking method and transmitter and receiver
WO2007046491A1 (en) * 2005-10-20 2007-04-26 Nec Corporation Mram and its operation method
JP5724877B2 (en) * 2009-10-21 2015-05-27 日本電気株式会社 Parity control system and method, and communication system and method

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