JP4321175B2 - Signal transmission system with error correction code - Google Patents

Description

  The present invention relates to a signal transmission system with an error correction code in which nodes such as a plurality of devices and control boards are mutually connected by an optical bus.

  Conventionally, optical fibers have been used mainly in basic communication applications taking advantage of their characteristics, but the signal transmission method using them is based on transmission in which the transmission side and the reception side are connected one-to-one. Yes.

  On the other hand, the development of very large scale integrated circuits (VLSI) in recent years has greatly increased the circuit functions of circuit boards used in data processing systems. As the circuit function increases, the number of signal lines used on each circuit board also increases, and the number of cable cores connecting the boards also increases. In such a system, the conventional transmission system using electric wires causes reflection due to mismatching in the characteristic impedance of the cable, signal delay resulting from variations in the length of the electric wires, or radiated electromagnetic field noise due to unwanted radiation from the electric wires. However, these have been an obstacle to speeding up the signal.

  As a means for solving this type of problem, there is a method using optical transmission. If optical fiber is used for optical transmission, the speed of the signal can be increased without generating radiated electromagnetic noise due to unnecessary radiation, and the number of optical fibers can be reduced by serializing the signal. is there. For the reasons described above, optical fibers are not limited to basic communication applications but are gradually being applied to signal transmission between devices, within devices, or between chips on a board.

When considering such an application, the range of use does not widen if the connection method of optical fibers is limited to one-to-one, so one-to-many to join (couple) or shunt (branch) signal light, or A many-to-many connection method is required. At that time, an optical branching and coupling device (an optical branching device and / or an optical coupling device) is used for one-to-many or many-to-many connection of optical fibers. For this, for example, a component such as an optical star coupler is used, but an optical sheet bus as described in Patent Document 1 can also be used.
JP-A-10-123350

Techniques for transmitting optical signals between an arithmetic module having a processor and a memory module having a memory using an optical branching and coupling device such as this type of optical sheet bus are described in, for example, Patent Document 2 and Patent Document 3. . This technology solves problems such as increased power consumption when the bus wiring is electrically connected, cost increase, transmission error due to skew, etc., speeding up data transmission between the arithmetic module and memory module and reducing power consumption It is intended to simplify the connection.
Japanese Patent Laid-Open No. 11-39069 JP-A-11-39251

In order to realize such optical transmission, various means are provided on the transmission side and the reception side. Specifically, photoelectric conversion means, electro-optic conversion means, parallel / serial conversion means, serial / parallel conversion means, error correction code encoder / decoder means, code encoder / decoder means for DC balance, optical transmission There are clock and data signal timing adjustment means, and the provision of these means makes it possible to transmit and receive high-quality signals. An error correction method is described in Patent Document 4, for example.
JP-A-9-219698

  When a bidirectional data bus signal such as a CPU bus is simply replaced with an optical fiber connection, it is necessary to divide the optical signal system into two systems, a transmission side and a reception side. In this case, when writing data from the CPU side device to the memory or ASIC side device (during writing), the CPU side device uses the optical signal transmission side and the memory or ASIC side device uses the optical signal transmission side. Use the signal receiver. Conversely, when the CPU side reads data to the memory or ASIC side device (when reading), the CPU side device uses the optical signal receiving side, and the memory or ASIC side device uses the optical signal transmitting side. To do.

The problems here are the bit error rate (BER) and the data transmission band.
In high-speed serial data transmission using an optical fiber, it is essential to prepare an error correction code encoding / decoding means. In reading and writing data on the CPU bus, there is no room for resending data when an error occurs, and error correction must be performed in real time. The actual BER in a state where the BER at the physical level and the error correction algorithm are combined must exceed the required specification. Further, it is not preferable that the photodiode used for receiving the optical signal is continuously in a no-signal state or a state in which a fixed-level optical signal is continuously given, because the response characteristic of the photodiode is deteriorated. It is possible to maintain the response characteristics of the photodiode by constantly applying an optical signal having a strong and weak level at a constant duty ratio to achieve DC balance.

  On the other hand, in order to transmit an optical signal using a diffusion optical system using a combination of an inexpensive optical sheet bus and a plastic optical fiber (POF), the upper limit of the transmission band per fiber is naturally determined from the relationship of absorption loss. come. In order to clear the bandwidth limitation, it is conceivable to increase the number of fiber lines, but if it is increased unnecessarily, signal-to-signal skew becomes a problem.

  Therefore, in order to reduce the number of fibers by effectively using the bandwidth of the optical fiber, the transmission data is serialized. Prior to the generation of the serial data, encoding means for maintaining the DC balance of the serial data, for example, 8B10B encoding is performed. Thereby, DC balance can be ensured for the data. On the other hand, an error correction code (ECC) is also transmitted for error correction of data. However, in order to maintain the responsiveness of the photodiode, it is necessary to ensure DC balance for the ECC. There is a problem that 8B10B encoding cannot be used.

  The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a signal transmission system with an error correction code that secures a bit error rate and a data transmission band while maintaining the responsiveness of a photodiode. To do.

The above object is a signal transmission system with an error correction code that serializes a data signal and its error correction code and transmits the data signal from one node to the other node via an optical transmission line, the serialized data signal and This is achieved by a signal transmission system with an error correction code in which both of the error correction codes are transmitted in a DC balanced state.
Here, the data signal and its inverted signal and the error correction code and its inverted signal can be transmitted via a common line.

The error correction code and its inverted signal can be transmitted via a dedicated line different from the data signal transmission line. In this case, the error correction code and its inverted signal can be alternately arranged, for example, every bit.
Further, the error correction code and the dummy bit (fixed value) can be transmitted via a dedicated line different from the data signal transmission line. In this case, the error correction code and the dummy bit can be alternately arranged, for example, every bit.

The error correction code, its inverted signal and dummy bit can be transmitted via a dedicated line different from the data signal transmission line.
Further, the error correction code is divided, and the divided error correction code and its inverted signal and / or dummy bit can be transmitted through a plurality of dedicated lines different from the data signal transmission line. .

  According to the present invention, a bit error rate (BER) and data transmission are maintained while maintaining the responsiveness of a photodiode while using a diffusion optical system using a combination of inexpensive optical components, for example, an optical sheet bus and a plastic optical fiber (POF). It is possible to realize a signal transmission system with an error correction code that secures a band.

Hereinafter, the present invention will be described, but before that, an example of a signal transmission system to which the present invention is applied will be described.
FIG. 1 is a schematic diagram illustrating an example of a signal transmission system. CPUs used for controlling mechanical operation, ASIC for image processing, and the like include a CPU bus called a CPU interface for electrically connecting and controlling the CPU and its peripheral devices. When the bidirectional data bus of the CPU bus is to be realized by optical fiber connection, as shown in FIG. 1, it is necessary to divide the optical signal system into two systems, a transmission side and a reception side. In the system of this example, the error correction code encoder / decoder is provided in the ASIC for optical interface control as will be described later.

  As shown in FIG. 1, the system of this example includes a master device 1, a main slave device 2, and sub slave devices 3 and 4. The master device 1 includes a CPU (processor) 11, an optical interface control ASIC 12, an optical transmitter 13, and an optical receiver 14. The optical transmitter 13 includes a light emitting element 131 such as one or a plurality of laser diodes (LD), a driving circuit 132 thereof, and an optical connector 133 for coupling with an optical fiber. The optical receiver 14 includes a light receiving element 141 such as one or a plurality of photodiodes (PD), a receiving circuit 142, and an optical connector 143 for coupling with an optical fiber. A predetermined clock 15 is applied to the optical interface control ASIC 12.

  The main slave device 2 and the sub slave devices 3 and 4 can have the same configuration, and the memories 21, 31, and 41, the optical interface control ASICs 22, 32, and 42, the optical transmitters 23, 33, and 43, and the optical receiver, respectively. And 24, 34, 44. As in the case of the master device, the optical transmitters 23, 33, and 43 are one or more light emitting elements such as laser diodes (LD), their drive circuits, and optical connectors 233, 333 for coupling to optical fibers, 433. Similarly, the optical receivers 24, 34, and 44 include one or a plurality of light receiving elements such as photodiodes (PD), a receiving circuit, and optical connectors 243, 343, and 443 for coupling with optical fibers.

  The master device 1 and each of the slave devices 2 to 4 are connected by a downstream optical transmission path 5 and an upstream optical transmission path 6. The downstream optical transmission path 5 includes an optical fiber 51, an optical branching device 55, and a plurality of optical fibers 52 to 54. The upstream optical transmission line 6 includes an optical fiber 61, an optical coupling device 65, and a plurality of optical fibers 62 to 64. As shown in FIG. 1, the optical fiber 51 is connected to the optical connector 133, and the optical fibers 52 to 54 are connected to the optical connectors 243, 343, and 443. The optical fiber 61 is connected to the optical connector 143, and the optical fibers 62 to 64 are connected to the optical connectors 233, 333, and 433. Here, as the optical fiber, for example, a plastic optical fiber (POF) can be used, but is not limited thereto. As the optical branching device 55 and the optical coupling device 65, for example, a star coupler or an optical sheet bus (Japanese Patent Laid-Open No. 10-123350, Japanese Patent Laid-Open No. 10-282371, etc.) provided with a transmitted light diffusing unit can be used. .

  FIG. 2 is a block diagram illustrating a specific configuration example of the signal transmission system of FIG. In particular, the optical interface control ASIC 12 of the master device 1 and the optical interface control ASIC 22 of the main slave device 2 are specifically shown in FIG. As shown in the figure, the optical interface control ASIC 12 of the master device 1 has a CPU I / F bus timing adjustment unit 121 for securing a setup hold time for an address bus, a data bus, etc. Encoding means 122 for encoding so as not to be transmitted and maintaining the DC balance of serial data, and error correction code (ECC) transmitted together with a data signal to maintain the transmission quality of optical transmission An error correction code encoder means 123 to be generated, a Tx (transmission side) bus switch means 124 for switching the bus to the timing adjustment circuit at the time of timing adjustment, and a parallel / serial conversion means 125 for serializing parallel data signals are provided. In Serial / parallel conversion means 131 for parallelizing the aldata signal, Rx (reception side) bus switch means 132 for switching the bus to a timing adjustment circuit (to be described later) at the time of timing adjustment, and an error correction code sent together with the received data signal Error correction code decoder means 133 that corrects the data signal when there is an error, and decoding means 134 that restores the serial data signal encoded so as not to be DC transmission when optically transmitted to the original data signal, And a CPU I / F bus timing adjustment means 135.

  Further, the ASIC 12 for controlling the optical interface controls the timing adjustment circuit 140 connected to the Tx bus switch means 124 or the Rx bus switch means 132 to adjust the phase of the clock and the data signal, and the parallel data signal to the serial data signal. For conversion, a PLL (Phase Locked Loop) circuit 150 that multiplies the input clock from several times to about 10 times and applies it to the parallel / serial conversion means 125 is provided.

  On the other hand, the optical interface control ASIC 22 of the slave device 2 holds, on the transmission side, latch means 221 for inputting a data signal from the memory, encoding so as not to be DC transmission during optical transmission, and maintaining the DC balance of the serial data. Encoding means 222, error correction code encoder means 223 for generating an error correction code to be transmitted together with a data signal in order to maintain the transmission quality of optical transmission, and a Tx bus switch for switching the bus to the timing adjustment circuit at timing adjustment Means 224 and parallel / serial conversion means 225 for serializing the parallel data signal, and on the receiving side, serial / parallel conversion means 231 for parallelizing the serial data signal, and switching the bus to the timing adjustment circuit at the time of timing adjustment. Rx bus switch to perform Means 232, error correction code decoder means 233 for correcting the data signal when there is an error by comparing the received data signal and the error correction code sent together, encoded so as not to be DC transmission when optically transmitted A decoding unit 234 for restoring the serial data signal to the original data signal and a latch unit 235 for suppressing inter-channel skew between the data signals are provided.

Further, the ASIC 22 for controlling the optical interface controls the timing adjustment circuit 240 connected to the Tx bus switch means 224 or the Rx bus switch means 232 to adjust the phase of the clock and the data signal, and the parallel data signal to the serial data signal. For conversion, a PLL circuit 250 that multiplies the input clock from several times to about 10 times and applies it to the parallel / serial conversion means 225 is provided.
In the above example, each means and circuit on the transmission side and reception side are realized in each optical interface control ASIC, but the present invention is not limited to this, and some Means or circuitry may be provided externally.

  FIG. 3 is a diagram for explaining how to balance DC between data and an error correction code (ECC). In the figure, the numbers in parentheses indicate the number of bits. It should be noted that in the generation of serial data with DC balance maintained, the 8B10B encoder can be used for the original data, but the 8B10 encoder cannot be used for the ECC. That is. This is because if the ECC is converted using the 8B10B encoding table, data error correction cannot be performed on the receiving side.

  Therefore, in this example, the DC balance between the data signal and the ECC is set as shown in FIG. That is, the parallel 8-bit original data output from the original data generating means 301 is converted into 10 bits with DC balance by the 8B10B encoder 302. The numbers in parentheses in the figure indicate the number of bits. The parallel data signal is serialized by the parallel / serial conversion means 303 and transmitted. On the other hand, the ECC encoder 304 generates a 6-bit ECC in the ECC generation unit 305 based on the parallel data signal output from the 8B10B encoder 302, and further the DC balance of the ECC is obtained in the inverted ECC addition unit 306. The inverted signal of 4 bits is added to the ECC and output in 10 bits. The ECC to which the inverted signal is added is serialized by the parallel / serial conversion means 303 and transmitted. The reason for doing this is as follows. That is, even if the ECC is serially converted as it is, it does not become serial data in which DC balance is maintained. Also, the number of ECC bits does not match the number of bits of data after 8B10B conversion. Therefore, by adding an inverted ECC, DC balance is maintained when the ECC is serially converted, and the number of bits is the same as that of the data signal. A fixed bit (dummy bit) can be added instead of or together with the inverted ECC. This will be described later. In the example of FIG. 3, a 24-bit data signal, a 6-bit ECC, and a frame clock are transmitted as serial data in which DC balance is maintained by using five fibers. On the serial data receiving side, data error correction is performed using the ECC from which the inverted ECC bits are removed.

  In general, when transmitting an optical signal, transmission data is serialized as described above in order to reduce the number of fibers by effectively using the bandwidth of the optical fiber. At that time, either the frame clock is transmitted together with the serialized transmission data, or the frame clock is included in the signal and transmitted. The frame clock is a reference clock for converting parallel data into serial data. If the clock signal and the data signal cannot be received on the receiving side, the serial data cannot be accurately restored to parallel data.

Prior to the generation of the serial data, an encoding means for maintaining the DC balance of the serial data, here 8B10B encoding (algorithm) is used, and 2 redundant bits are added for each 8 bits of data. It is changed to bit data. As a result, when the data is binary data composed of a combination of 0 and 1, the appearance ratio of 0 data and 1 data is kept close to 5 to 5. Further, in order to secure a bit error rate (BER), an error correction code is generated using an error correction algorithm. For example, a Hamming code is used to generate an error correction code. When the data signal is m bits and the ECC is n bits, if the relationship of m + n ≦ 2 ⁿ −1 is satisfied, error correction can be performed without retransmitting the data signal when a transmission error occurs.

  As described above, it is necessary to consider the DC balance of the ECC dedicated line itself when sending the ECC. Since 8B10B algorithm cannot be used for ECC, by adding ECC and its inverted signal and / or dummy bit (fixed bit) as an alternative means, while making the same 10-bit width as 8B10B encoded data to be sent together, Make sure that the DC balance is achieved. Ideally, the appearance ratio of 0 data and 1 data is always 5 to 5, but even if there is a partial 6 to 4 or 4 to 6 state, it will not be fixed with it. As long as there is no real problem.

  Further, when the number of data to be sent is small, it is possible to share the data and ECC with one fiber. In this case, instead of adding redundant bits to the data using the 8B10B algorithm described above, for example, inverted data × 2 bits, ECC × 3 bits, and inverted ECC × 3 bits for data × 2 bits. All 10 bits can be sent on a single fiber. Even in such a configuration, the appearance ratio of 0 data and 1 data can be made close to 5 to 5 without using the 8B10B algorithm.

On the other hand, when the frequency of the frame clock and the conversion ratio from parallel data to serial data are combined, the transmission band of the serialized signal is naturally determined. For example, if the frequency of the frame clock is 50 MHz and the parallel / serial conversion ratio is 10: 1, a transmission line of 500 Mbps is required for a fiber line for sending one piece of serial data. If the frequency of the frame clock or the parallel / serial conversion ratio is increased, the transmission band required for the fiber line for sending one serial data naturally increases. In order to transmit an optical signal using a diffusion optical system using a combination of an inexpensive optical sheet bus and a plastic optical fiber (POF) that enables broadcast transmission of an optical signal, the fiber 1 is naturally used from the relationship between transmission distance and absorption loss. The upper limit of transmission bandwidth per book is determined. In order to increase the transmission band, it is conceivable to use glass optical fiber (GOF) instead of POF. However, this causes a problem of alignment of the optical axis, and it is necessary to connect to a diffusion optical system using an optical sheet bus. Becomes difficult. Conversely, if a diffusion optical system using a combination of an inexpensive optical sheet bus and POF is used and if the number of POFs is increased excessively in order to secure a transmission band, it will be difficult to compensate for the signal-to-signal skew. Or the circuit board becomes complicated.
Increasing the number of ECC dedicated lines increases the number of error bits that can be corrected in real time, but increasing the number of POFs also increases the problem of increased signal skew and circuit board complexity, as described above. However, when the number of POFs is limited, the number of bits (information amount) that can be transmitted is reduced. For this reason, in the present invention, data and ECC are transmitted as follows.

FIG. 4 is a diagram illustrating an example of the relationship between the optimum number of ECC bits and the number of bits that can be transmitted (information amount) with respect to the number of fibers (number of cores). As shown in the figure, since one clock (CLK) line is used in each case, the number of fibers that can be used for data signals and ECC is the number obtained by subtracting one CLK for all fiber core lines. As described above, when the data signal is m bits and the ECC is n bits, m + n ≦ 2 ⁿ −1 is satisfied. Hereinafter, the numbers in parentheses indicate the number of bits.

In case A, there is one data line and no ECC dedicated line. Data (2) + inverted data (2) + ECC (3) + inverted ECC (3) are sent together to this data line. In this case, DC balance is secured by adding an inverted signal to both data and ECC. 8B10B encoding is not used.
In case B, there is one data line and one ECC dedicated line. The data line uses 8B10B encoding, and the ECC dedicated line adds 10 bits to the ECC (4) by adding the inverted ECC (4) + dummy (2). In this case, data (10) + ECC (4) ≦ 2 ⁴ −1 is satisfied.

In Case C, there are two data lines and one ECC dedicated line. The two data lines use 8B10B encoding, and the ECC dedicated line adds ECC (5) to ECC (5) to achieve 10 bits. In this case, data (20) + ECC (5) ≦ 2 ⁵ −1 is satisfied.
In Case D, there are three data lines and one ECC dedicated line. The two data lines use 8B10B encoding, and the ECC dedicated line adds ECC (5) to ECC (5) to achieve 10 bits. In this case, data (20) + ECC (5) ≦ 2 ⁵ −1 is satisfied. The remaining data (2) + inverted data (2) + ECC (3) + inverted ECC (3) are sent together in one line, but 8B10B is not used. This is used for transmission from the slave device to the master device.

In Case E, there are three data lines and one ECC dedicated line. The three data lines use 8B10B encoding. ECC sends 6 bits on one line. Of these, inverted ECC (4) is generated for 4 bits, and this is added to the ECC to achieve 10 bits. In this case, data (30) + ECC (6) ≦ 2 ⁶ −1 is satisfied. This is used for transmission from the master device to the slave device (cost priority).
In Case F, there are three data lines and two ECC dedicated lines. The three data lines use 8B10B encoding. ECC divides 6 bits into 2 lines. Inverted ECC (3) and dummy (4) are added to each line to achieve 10 bits. In this case, data (30) + ECC (6) ≦ 2 ⁶ −1 is satisfied.

In Case G, there are four data lines and two ECC dedicated lines. The four data lines use 8B10B encoding. ECC divides 6 bits into 2 lines. Inverted ECC (3) and dummy (4) are added to each line to achieve 10 bits. In this case, data (40) + ECC (6) ≦ 2 ⁶ −1 is satisfied.
In Case H, there are five data lines and two ECC dedicated lines. The five data lines use 8B10B encoding. ECC divides 6 bits into 2 lines. Inverted ECC (3) and dummy (4) are added to each line to achieve 10 bits. In this case, data (50) + ECC (6) ≦ 2 ⁶ −1 is satisfied.

In Case I, there are 6 data lines and 2 ECC dedicated lines. The 6 data lines use 8B10B encoding. ECC distributes 7 bits to two lines. One adds an inverted ECC (4) and a dummy (2), and the other adds an inverted ECC (3) and a dummy (4) to achieve 10 bits. In this case, data (60) + ECC (7) ≦ 2 ⁷ −1 is satisfied.
In Case J, there are seven data lines and two ECC dedicated lines. Seven data lines use 8B10B encoding. ECC distributes 7 bits to two lines. One adds an inverted ECC (4) and a dummy (2), and the other adds an inverted ECC (3) and a dummy (4) to achieve 10 bits. In this case, data (70) + ECC (7) ≦ 2 ⁷ −1 is satisfied. This is used for transmission from the master device to the slave device (speed priority).
Note that the case of 11 or more fiber cores is not illustrated here, but in this case as well, a DC balanced signal can be transmitted using a data line and an ECC dedicated line in a combination of the above cases. it can.

  FIGS. 5A to 5D are diagrams showing a specific example of a method of adding an inverted bit or a dummy bit in the case of ECC 6 bits. When converting ECC 6 bits to 10 bits, in FIG. 5A, inverted ECCs are inserted into consecutive free 4 bits as shown. Here, the inverted ECC is performed using the first 4 bits of the ECC 6 bits, but other bits may be used. The same applies to the following examples. In FIG. 5B, the first 4 bits of the ECC 6 bits are alternately inverted as shown, and the inverted ECC is inserted into the empty 4 bits. In FIG. 5 (c), dummy bits (fixed values) are inserted into consecutive four free bits as shown. The dummy bit insertion position is arbitrary. In FIG. 5 (d), dummy bits are alternately inserted as shown in the top 4 bits of the ECC 6 bits. In the above, the inverted ECC and dummy bits in the 10-bit ECC are ignored on the receiving side. The same applies to the following examples. As for DC balance, it is ideal that the appearance ratio of 0 data and 1 data is always 5 to 5. However, as described above, a state of 6 to 4 or 4 to 6 is partially mixed. Even if it is, there is no problem in practice unless it is fixed with it. However, it is preferable to select the most suitable method, that is, the method that minimizes the continuity of the same value. This will be described next.

  FIGS. 6A to 6D are diagrams showing a specific example in the case where an inverted bit or a dummy bit is added to the ECC 6 bits and serialized and transmitted. FIG. 6A shows a serialized ECC having 10 bits as shown in FIG. In this case, the same value may appear continuously for a maximum of 6 bits. FIG. 6B shows a serialized ECC having 10 bits as shown in FIG. In this case, the same value may appear continuously for up to 3 bits. FIG. 6C shows a serialized ECC having 10 bits as shown in FIG. In this case, the same value may appear continuously up to 7 bits. FIG. 6D shows a serialized ECC having 10 bits as shown in FIG. In this case, the same value may appear continuously up to 4 bits. Considering the above, it can be said that the case of FIG.

  FIG. 7 is a diagram showing a specific example of the inverted bit adding method in the case of ECC 3 bits. In this example, ECC is sent on the same line (shared line) as 2-bit data, and 8B10B encoding is not performed on the data. Conversion to 10 bits is performed by first inverting ECC 3 bits alternately, and then inverting data 2 bits alternately. Thereby, DC balance of data and ECC can be taken.

  FIG. 8 is a diagram showing a specific example of the method of adding the inverted bit and the dummy bit in the case of ECC 4 bits. In this example, ECC 4 bits are divided into two bits, the first half and the second half, and are alternately inverted. One dummy bit is inserted after the first half is inverted, and one dummy bit is inserted after the second half is inverted. To 10 bits. Thereby, the DC balance of ECC can be taken.

  FIG. 9 is a diagram illustrating a specific example of a method of adding an inverted bit in the case of ECC 5 bits. In this example, ECC 5 bits are alternately inverted bit by bit to achieve 10 bits. Thereby, the DC balance of ECC can be taken.

  FIG. 10 is a diagram showing a specific example of a method of adding an inverted bit and a dummy bit in a case where ECC 6 bits are sent by two dedicated lines. In this example, the ECC 6 bits are divided into the first half 3 bits and the second half 3 bits, and each is divided into two ECC dedicated lines. As shown in the figure, the first 3 bits are alternately inverted after inserting 2 bits of dummy bits, and after this inversion is completed, 2 more dummy bits are inserted into 10 bits, and the latter 3 bits are similarly replaced with dummy bits. Inverted alternately after 2 bits are inserted, and after the end of the inversion, another 2 bits are inserted into 10 bits. Thereby, the DC balance of ECC can be taken.

  FIG. 11 is a diagram showing a specific example of the method of adding the inverted bit and the dummy bit in the case of ECC 7 bits. In this example, ECC 7 bits are divided into 4 bits in the first half and 3 bits in the second half, and each is assigned to two ECC dedicated lines. As shown in the figure, for the first 4 bits, 2 bits are alternately inverted and 1 dummy bit is inserted, then 2 bits are alternately inverted and 1 dummy bit is inserted again to make 10 bits. Bits are inverted alternately after 2 bits of dummy bits are inserted, and after the inversion, 2 bits of dummy bits are inserted to make 10 bits. Thereby, the DC balance of ECC can be taken.

  FIG. 12 is a diagram illustrating an example of the flow of data and ECC. This figure shows the case of 10 downlink channels (D0 to D8, CLK) and 5 uplink channels (D'0 to D'3, CLK). When data is written from the master device 1 which is a substrate on which a CPU (processor) is mounted to the slave devices 2 to 4 which are substrates on which an ASIC or a memory is mounted, the address AD and data DA from the master device 1 The control signals such as the write WR and the chip select CS, and the signals such as the error correction code ECC and the frame clock (CLK) are transmitted from the optical transmitter via the optical transmission line 5. Each slave device 2-4 receives these signals by an optical receiver. When the master device 1 reads the data of the slave devices 2 to 4, first, the master device 1 transmits signals such as the address AD, the read RE, and the chip select CS from the optical transmitter via the optical transmission line 5. The devices 2 to 4 perform operations according to the signals received by the optical receiver. Then, the slave devices 2 to 4 send the data DA and the error correction code ECC to the master device 1 via the optical transmission path 6 from the optical transmitter. In this example, the return frame clock (CLK ′) signal is not sent. The master device 1 can receive the data by receiving the data signal and the like by the optical receiver. The signal transmitted here is in a DC balanced state including ECC.

  When transmitting an optical signal from the master device 1 to the slave device via the optical branching device 55, the optical signal from the master device 1 is transmitted to all the slave devices 2 to 4, unlike the case of transmission by one-to-one connection. Will be sent. This is because the signal branched by the optical branching device 55 reaches each slave device. Therefore, the receiving side of each slave device determines whether it is a signal related to itself, and as a result, if it is a signal transmitted to itself, it receives that signal, otherwise it is ignored. A determination device is provided. In order to make this determination, a unique identification number is stored in each slave device. This identification number can be given to each slave device from the master device.

  FIG. 13 is a diagram illustrating another example of the flow of data and ECC. This figure is particularly different from the example of FIG. 12 in that the number of channels is 5 downlink channels (D0 to D3, CLK) and 5 uplink channels (D'0 to D'3, CLK). This example reduces the number of fibers by dividing the number of address buses and data buses from the master device 1 to the slave devices 2 to 4 into upper bits and lower bits and transferring them in two clocks. It is possible. That is, in the upstream channel, the address AD and the data DA are each divided into 16 bits by 8 bits and transmitted from the master device 1 to the slave devices 2 to 4 over 2 cycles. The error correction code (ECC) is transmitted at 10 bits with DC balance by adding 4 bits of the inverted signal to ECC 6 bits. In the downstream channel, the data DA is transmitted in 16 bits from the slave devices 2 to 4 to the master device 1, and the error correction code (ECC) adds 5 bits of the inverted signal to the ECC 5 bits to achieve DC balance. It is transmitted in 10 bits.

  Since the present invention can secure a bit error rate and a data transmission band while maintaining the responsiveness of a photodiode, for example, an error correction code in which nodes such as a plurality of devices or between control boards are connected to each other by an optical bus. It can be applied to an attached signal transmission system.

It is the schematic which shows an example of a signal transmission system. It is a block diagram which shows the specific structural example of the signal transmission system of FIG. It is a figure for demonstrating how to make DC balance of data and an error correction code (ECC). It is a figure which shows an example of the relationship between the optimal ECC bit number with respect to the number of fibers (core number), and the number of bits (information amount) which can be transmitted. (A)-(d) is a figure which shows the specific example of the addition method of the inversion bit or dummy bit in the case of ECC 6 bits. (A)-(d) is a figure which shows the specific example in the case of adding an inversion bit or a dummy bit to ECC6 bit, and serializing and transmitting. It is a figure which shows the specific example of the addition method of the inversion bit in the case of ECC3 bit. It is a figure which shows the specific example of the addition method of the inversion bit and dummy bit in the case of ECC4 bit. It is a figure which shows the specific example of the addition method of the inversion bit in the case of ECC5 bit. It is a figure which shows the specific example of the addition method of the inversion bit and dummy bit in the case where ECC6 bit is sent with two exclusive lines. It is a figure which shows the specific example of the addition method of the inversion bit and dummy bit in the case of ECC7 bit. It is a figure which shows an example of the flow of data and ECC. It is a figure which shows the other example of the flow of data and ECC.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Master apparatus 2 Main slave apparatus 3, 4 Sub slave apparatus 5 Downstream optical transmission path 6 Uplink optical transmission path 13,23,33,43 Optical transmitter 14,24,34,44 Optical receiver 55 Optical branching Device 56 Optical coupling device 51 to 54, 61 to 64 Optical fiber 301 Original data generation means 302 8B10B encoder 303 Parallel / serial conversion means 304 ECC encoder 305 ECC generation unit 306 Inverted ECC addition unit

Claims (6)

A data signal and the error correction code with signal transmission system for transmitting over an optical transmission path that error correcting code from one node to serialize the other node, the N-bit original data before Kide data signal 0-data and 1-data are converted into M-bit data in which the appearance ratio of 0-data and 1-data is balanced, and an error correction code generated based on the data signal converted into the M-bit data is added to the inverted signal. The data signal converted into the M-bit data is serialized and transmitted through a transmission line, and an M-bit error correction code with the inverted signal added thereto is used. A signal transmission system with an error correction code, characterized by being serialized and transmitted via a dedicated line different from the transmission line . The error correction code and an error correction code with signal transmission system according to claim 1, wherein the inverted signal thereof and being arranged alternately. 2. The signal transmission system with an error correction code according to claim 1 , wherein an M-bit error correction code is changed to M bits by adding dummy bits instead of the inverted signal . 4. The signal transmission system with an error correction code according to claim 3, wherein the error correction code and the dummy bit are alternately arranged. 2. The signal transmission system with an error correction code according to claim 1 , wherein an M-bit error correction code is changed to M bits by adding the inverted signal and a dummy bit instead of the inverted signal . A signal transmission system with an error correction code that serializes a data signal and its error correction code and transmits the data signal from one node to the other node via an optical transmission line, wherein the N-bit original data of the data signal is set to 0 data The data is converted into M-bit data in which the appearance ratio of one data is balanced, and the error correction code generated based on the data signal converted into the M-bit data is divided, and the divided error correction code is converted into its inverted signal. And / or dummy bits are added to form M bits in which the appearance ratios of 0 data and 1 data are balanced, and the data signal converted into the M bit data is serialized and transmitted through a transmission line. Serialize the divided M-bit error correction code to which the inverted signal and / or dummy bit is added An error correction code with signal transmission system characterized by transmitting through respective different plurality of dedicated lines to the transmission line.

Images