CN102683419B - SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with back gate connected with negative voltage through alloy bonding and manufacturing method thereof - Google Patents
SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with back gate connected with negative voltage through alloy bonding and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to an SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with a back gate connected with negative voltage through alloy bonding and a manufacturing method thereof. A substrate at the back of a partial depletion-type SOI/MOS device is leaded out, and a negative voltage is connected externally, thus the back grate effect of the partial depletion-type SOI/MOS device under the radiation condition is improved. The manufacturing method provided by the invention has the advantages that not only can the problem of uncertainty of substrate voltage at the back of the SOI/MOS device be solved, but also during the manufacturing process of the device, the back gate is not required to be solidified by an additional process, and the process steps are simplified; and the back gate is connected with the negative voltage, the total dosage resistant capability of the partial depletion-type SOI/MOS circuit can be improved, and performances of other circuit on the surface are not influenced.
Description
Technical field
The present invention relates to SOI/MOS device radiation hardening technology, specifically a kind of SOI/MOS device architecture and manufacture method being connect negative voltage by alloy bonding in backgate.
Background technology
SOI technology refers to and forms the material with certain thickness single crystal semiconductor silicon membrane layer on the insulating layer and prepare technology and on thin layer, manufacture the technology of semiconductor device.This technology can realize medium isolation completely, compared with the body silicon device of isolating by P-N junction, has the advantages such as, radiation hardness high, high temperature resistant without breech lock, high speed, low-power consumption, integrated level.
SOI device can be divided into thick devices and thin-film device according to SOI silicon film thickness.For thick film SOI device, when SOI silicon film thickness is greater than the maximum depletion widths of twice, be called as part depletion device; For Thin film SOI device, when the thickness of silicon fiml is less than maximum depletion widths, be called fully-depleted device.
In SOI technology, device is fabricated in the very thin silicon fiml of top layer, buries oxide layer separate between device and substrate by one deck.This structure makes SOI/ MOS device have many merits low in energy consumption of Denging just, compares, be more suitable for high performance ULSI and VLSI circuit than traditional body silicon MOS technique.Its advantage mainly comprises:
1, without latch-up.Due to the existence of dielectric isolation structure in SOI/MOS device, so there is no the current channel of substrate, the path of latch-up is cut off, and between each device physically with electricity on mutually isolated, improve the reliability of circuit.
2, structure is simple, and technique is simple, and integration density is high.SOI/MOS device architecture is simple, and do not need to prepare the complicated isolation technologies such as the trap of body silicon MOS circuit, the restriction of photoetching and lithographic technique is only depended in device minimum interval, and integration density significantly improves.SOI/MOS device is also particularly suitable for integrated high voltage and low-voltage circuit on the same chip, therefore has very high chip area utilance and cost performance.
3, parasitic capacitance is little, and operating rate is fast.The main electric capacity of body silicon MOS device is pipe source-drain area and the electric capacity between source/drain diffusion zone and substrate, and its doping content with substrate increases and increases, and this is by the load capacitance of increasing circuit, affects the operating rate of circuit; In SOI/MOS device, owing to burying the existence of oxide layer, source-drain area and substrate cannot form PN junction, parasitic capacitance of PN junction disappears, the substitute is buried oxidation layer electric capacity, this electric capacity is proportional to the dielectric constant of capacitance material, its value much smaller than the PN junction parasitic capacitance of source-drain area in body silicon and substrate, and not by the impact of scaled down.
4, low-power consumption.The power consumption of SOI/MOS device is made up of quiescent dissipation and dynamic power consumption two parts, and SOI device has steep sub-threshold slope, and close to desirable level, therefore leakage current is very little, and quiescent dissipation is very low; Because SOI/MOS device has the junction capacitance less than body silicon device and wire capacitances, under therefore same operating rate, dynamic power consumption also reduces greatly.
From radioresistance angle analysis, due to SOI technology MOS device, oxide layer formed burying, and compared with body silicon, reduces and forms the sensitive volume of Single event upset effecf, so the ability of anti-single particle effect strengthens greatly.But when device continues to be subject to ionising radiation (as X ray, gamma-rays etc.), can total extreme be produced.For SOI technology, owing to burying the existence of oxygen medium layer, make under radiation condition, in silica dioxide medium, ionization produces the electron-hole pair of some.The electronics major part that mobility is larger is overflowed, and some electronics and hole are to compound, and most of hole is transported to SiO2/Si interface under the effect of positive electric field, and some is captured by the defect of SiO2 side, interface, form interfacial state.Such positive charge accumulation can cause device back also to form the passage of a source/drain, and not by the control of front grid, causes backgate threshold voltage shift effect and backgate to open effect, finally affect the performance of device.
Adopt in two ways to the reinforcing of SOI back-gate effect in the world at present: 1, utilize technique to reinforce means more.As low temperature process, silicon oxynitride gate medium, reduce and bury oxide layer oxygen implantation dosage and carry out nitrogen injection, to add negative electrical charge complex centre simultaneously.2, special SOI/MOS device architecture is adopted.Do one deck screen burying in oxide layer, shielding back-gate effect is on the impact of front grid.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of the SOI/MOS device architecture and the manufacture method that are connect negative voltage by alloy bonding in backgate are provided, improve back-gate effect by the method for circuit design.
According to technical scheme provided by the invention, a kind of SOI/MOS device architecture connecing negative voltage in backgate by alloy bonding comprises: silicon dioxide buries oxide layer and is positioned on the silicon substrate of back, silicon dioxide buries oxide layer and is provided with silicon tagma, the monocrystalline silicon source/drain region of MOS device, the place of silicon dioxide isolation, the monocrystalline silicon source/drain region of MOS device is positioned at around silicon tagma, and the place of silicon dioxide isolation is positioned at around the monocrystalline silicon source/drain region of MOS device; Silicon tagma is coated with the silicon dioxide gate dielectric layer of MOS device, the silicon dioxide gate dielectric layer of described MOS device is coated with the polysilicon gate of MOS device, the monocrystalline silicon source/drain region of MOS device and the polysilicon gate of MOS device are provided with tungsten alloy through hole, and the active area of MOS device is connected with aluminum metal interconnection line by described tungsten alloy through hole; In MOS device surface coverage silicon dioxide passivation layer, have the alloy contact layer that alloy bonding is formed at the back of described back silicon substrate, the negative voltage that contact layer is provided by aluminum metal interconnection line and outside is connected, for back silicon substrate provides effective voltage.
The described manufacture method being connect the SOI/MOS device of negative voltage by alloy bonding in backgate, the steps include: that first on the silicon substrate of back, forming silicon dioxide buries oxide layer, buries place oxide layer being formed silicon tagma and silicon dioxide isolation at silicon dioxide; Then, by oxidation on silicon tagma, form silicon dioxide gate dielectric layer; Depositing polysilicon grid on silicon dioxide gate dielectric layer; Then, by ion implantation means, form the monocrystalline silicon source/drain region of MOS device around tagma, a basic MOS device just defines; Then, silicon dioxide passivation layer is formed at the MOS device surface deposition silicon dioxide formed; Then, connecting for being formed, by etching and depositing technics, forming tungsten alloy through hole; Tungsten alloy through hole is connected with effective voltage by recycling aluminum metal interconnection line; Deposit again, generates silicon dioxide passivation layer; Finally, contact layer is formed at the back of the MOS structure backgate place formed and described back silicon substrate by alloy bonding.
Advantage of the present invention is: the present invention utilizes alloy bonding technology to be drawn by SOI back silicon substrate, direct external negative voltage, thus improves device backgate under radiation parameter and be subject to the impact of total dose effect and the backgate threshold voltage shift effect that formed.The present invention, from the angle of circuit design, improves in the impact of radiation parameter lower back gate threshold voltage drift on device backgate performance.With original to be reinforced by process means compared with, simplify processing step, and when not affecting circuit performance, optimize the performance of circuit under radiation parameter.Eliminate the backgate threshold voltage shift under radiation parameter of PD SOI technique to the impact of circuit.
Accompanying drawing explanation
Fig. 1 is that the present invention utilizes bonding technology to improve the example structure figure of backgate threshold voltage shift.
Fig. 2 is PD SOI/MOS device energy band diagram.
Fig. 3 is that PD SOI/MOS device backgate connects negative voltage energy band diagram.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.The present invention relates to the SOI/MOS device architecture and the manufacture method that connect negative voltage in backgate, by PD SOI/MOS device back silicon substrate is drawn, external negative voltage, thus the back-gate effect improving radiation condition lower part depletion type SOI/MOS device.The general principle of this design is: utilize back silicon substrate to connect negative voltage, change the Electric Field Distribution in SOI/MOS device oxygen buried layer, to affect the accumulation of positive charge in backgate interface under radiation condition, thus eliminate back-gate effect that total radiation dose causes to the impact of device performance.
As shown in Figure 1, a kind of SOI/MOS device architecture utilizing alloy bonding to connect negative voltage in backgate comprises: the oxide layer 2 of burying that silicon dioxide is formed is positioned on back silicon substrate 1, bury oxide layer 2 and be provided with the tagma 3 that silicon is formed, the place 4 isolated by the source/drain region 5 to Si ion implantation formation MOS device, silicon dioxide, the source/drain region 5 of MOS device is positioned at tagma 3 around, and the place 4 of silicon dioxide isolation is positioned at around the source/drain region 5 of MOS device; Tagma 3 is coated with the silicon dioxide gate dielectric layer 6 of MOS device, the silicon dioxide gate dielectric layer 6 of described MOS device is coated with the polysilicon gate 7 of MOS device, the source/drain region 5 of MOS device and the polysilicon gate 7 of MOS device are provided with the through hole 9 of tungsten alloy material, and the active area of MOS device is connected with aluminum metal interconnection line 8 by described through hole 9; In MOS device surface coverage silicon dioxide passivation layer 10.At the back of back silicon substrate 1, also has the back silicon substrate contact layer 11 being generated silicon-aluminum material by alloy bonding.The negative voltage that contact layer 11 is provided by metal interconnecting wires 8 and outside is connected, and according to this structure, negative voltage is for back silicon substrate 1 provides negative voltage from back silicon substrate silicon-aluminum contact layer 11.
The described manufacture method being connect the SOI/MOS device of negative voltage by alloy bonding in backgate is: first formed on back substrate 1 and bury oxide layer 2, is burying the place 4 oxide layer being formed tagma 3 and silicon dioxide isolation.Then, by oxidation on tagma 3, form gate dielectric layer 6; Depositing polysilicon grid 7 on gate dielectric layer 6; Then, by ion implantation means, source/drain region 5, the basic MOS device forming MOS device around tagma 3 just defines; Then, silicon dioxide passivation layer 10 is formed at the MOS device surface deposition silicon dioxide formed; Then, connecting for being formed, by etching and depositing technics, forming through hole 9; Through hole 9 is connected with effective voltage by recycling metal interconnection wire 8; Deposit again, generates silicon dioxide passivation layer 10; Finally, contact layer 11 is formed at the back of the MOS structure backgate place formed and described back substrate 1 by alloy bonding.
As shown in Figure 2, under radiation parameter, the energy band diagram of SOI/MOS device.When high-energy particle bombardment silicon dioxide layer, ionize out a lot of electron-hole pair, under the effect of electric field, most of electronics drifts to polysilicon gate fast, and hole will to silicon dioxide interface step.Having close to silicon dioxide interface much owing to spreading the room of oxygen atom and the mismatch of lattice that stay, these lattice points and defect just become the Trapping Centers in hole.Captured by trap near hole step to silicon dioxide interface, define the accumulation (as shown in a in figure) of positive charge.And the existence of interface trap is due to can be with caused by difference in interface.In SOI/MOS device, the Fermi level of silicon in interface is lower than the energy level of trap.Now, trap " will impose on " electronics to silicon, and trap itself then becomes positive charge, be piled up in silicon dioxide interface (as shown in b in figure).Due to the impact of oxide traps and interface trap, finally form the accumulation of positive charge at silicon dioxide, have impact on the performance of SOI/MOS device.E in figure
cfor the energy level of conduction band, E
vfor the energy level of valence band, E
fifor intrinsic Fermi level.
As shown in Figure 3, under radiation parameter, back substrate connects the SOI/MOS device energy band diagram of negative voltage.Because oxide traps and interface trap positive charge pile up the effect all depending on electric field, at the additional electric field Δ E of back substrate, to keep oxygen buried layer Electric Field Distribution, the accumulation of electric charge under reduction total dose irradiation condition, and then improve the performance of device.Back substrate adds negative voltage thus suppresses hole to silicon dioxide interface step, reduces the quantity that positive charge is captured by trap, and then reduces the accumulation (as figure in a process) of positive charge at silicon dioxide interface.Meanwhile, utilize additional electric field Δ E, raise the Fermi level of silicon in interface, reduce the electronics that trap " imposes on ", thus reduce the accumulation (as b process in figure) of interface positive charge.Except above-mentioned two kinds of suppression mechanism, connect negative voltage at back substrate and also make the threshold voltage of metal-oxide-semiconductor increase.
The present invention not only solves the uncertain problem of SOI/MOS device back underlayer voltage, and does not need to carry out extra technique reinforcing to backgate in the process of device manufacture, simplifies processing step.Backgate connects negative pressure, can improve the resistant to total dose ability of PD SOI/MOS circuit, and the performance of other circuit of effects on surface is without impact.
Unaccomplished matter of the present invention belongs to techniques well known.
Claims (1)
1. connect a manufacture method for the SOI/MOS device of negative voltage by alloy bonding in backgate, it is characterized in that:
(1), at the upper silicon dioxide that formed of back silicon substrate (1) bury oxide layer (2), the oxide layer (2) of burying that silicon dioxide is formed is positioned on back silicon substrate (1);
(2), the silicon tagma (3) oxide layer (2) being provided with silicon formation is being buried, by forming the source/drain region (5) of MOS device, the place (4) of silicon dioxide isolation to Si ion implantation, the source/drain region (5) of MOS device is positioned at silicon tagma (3) around, and the place (4) of silicon dioxide isolation is positioned at the source/drain region (5) of MOS device around;
(3), on silicon tagma (3), be coated with the silicon dioxide gate dielectric layer (6) of MOS device, the silicon dioxide gate dielectric layer (6) of described MOS device be coated with the polysilicon gate (7) of MOS device;
(4), in the monocrystalline silicon source/drain region (5) of MOS device and the polysilicon gate (7) of MOS device, be provided with the through hole (9) of tungsten alloy material, the active area of MOS device is connected with aluminum metal interconnection line (8) by described tungsten alloy through hole (9);
(5), silicon dioxide passivation layer 10 is formed at the MOS device surface deposition silicon dioxide formed;
(6), at the back at described back silicon substrate (1) have the alloy contact layer (11) that alloy bonding is formed, contact layer (11) is connected with the negative voltage that outside provides by aluminum metal interconnection line (8), for back silicon substrate provides effective voltage.
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| CN102270582A (en) * | 2011-07-25 | 2011-12-07 | 中国科学院微电子研究所 | Method for improving back gate threshold voltage of SOI-PMOS device |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
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| CN102194828B (en) * | 2010-03-16 | 2014-05-28 | 北京大学 | Anti-irradiation SOI (silicon on insulator) device with novel source/drain structure and preparation method thereof |
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| CN102270582A (en) * | 2011-07-25 | 2011-12-07 | 中国科学院微电子研究所 | Method for improving back gate threshold voltage of SOI-PMOS device |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
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