CN102683419A - SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with back gate connected with negative voltage through alloy bonding and manufacturing method thereof - Google Patents
SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with back gate connected with negative voltage through alloy bonding and manufacturing method thereof Download PDFInfo
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- CN102683419A CN102683419A CN2012101909417A CN201210190941A CN102683419A CN 102683419 A CN102683419 A CN 102683419A CN 2012101909417 A CN2012101909417 A CN 2012101909417A CN 201210190941 A CN201210190941 A CN 201210190941A CN 102683419 A CN102683419 A CN 102683419A
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Abstract
The invention relates to an SOI (silicon on insulator)/MOS (metal oxide semiconductor) device structure with a back gate connected with negative voltage through alloy bonding and a manufacturing method thereof. A substrate at the back of a partial depletion-type SOI/MOS device is leaded out, and a negative voltage is connected externally, thus the back grate effect of the partial depletion-type SOI/MOS device under the radiation condition is improved. The manufacturing method provided by the invention has the advantages that not only can the problem of uncertainty of substrate voltage at the back of the SOI/MOS device be solved, but also during the manufacturing process of the device, the back gate is not required to be solidified by an additional process, and the process steps are simplified; and the back gate is connected with the negative voltage, the total dosage resistant capability of the partial depletion-type SOI/MOS circuit can be improved, and performances of other circuit on the surface are not influenced.
Description
Technical field
The present invention relates to SOI/MOS device radiation hardening technology, specifically is a kind of SOI/MOS device architecture and manufacturing approach that connects negative voltage through alloy bonding at back of the body grid.
Background technology
The SOI technology refers to and is forming the technology that the technology of preparing of the material with certain thickness single crystal semiconductor silicon membrane layer reaches manufacturing semiconductor device on thin layer on the insulating barrier.This technology can realize dielectric isolation completely, compares with the body silicon device of isolating with P-N knot, have no breech lock, at a high speed, advantage such as high, high temperature resistant, the radiation hardness of low-power consumption, integrated level.
Can the SOI device be divided into thick film device and thin-film device according to the SOI silicon film thickness.For the thick film SOI device,, be called as the part depletion device when SOI silicon film thickness during greater than the maximum depletion widths of twice; For the thin film SOI device,, be called full depleted device when the thickness of silicon fiml during less than maximum depletion widths.
In the SOI technology, device is fabricated in the very thin silicon fiml of top layer, buries oxide layer by one deck between device and the substrate and separates.This just structure makes SOI/ MOS device have numerous advantages such as low in energy consumption, compares than traditional body silicon MOS technology, is more suitable in high performance ULSI and VLSI circuit.Its advantage mainly comprises:
1, no latch-up.Because the existence of dielectric isolation structure, therefore arrive the current channel of substrate in the SOI/MOS device, the path of latch-up is cut off, and between each device physically with electricity on isolation each other, improved the reliability of circuit.
2, simple in structure, technology is simple, and integration density is high.The SOI/MOS device architecture is simple, need not prepare the complicated isolation technologies such as trap of body silicon MOS circuit, and the restriction of photoetching and lithographic technique is only depended in the device minimum interval, and integration density significantly improves.The SOI/MOS device also is particularly suitable for integrated high voltage and low-voltage circuit on same chip, therefore has very high chip area utilance and cost performance.
3, parasitic capacitance is little, and operating rate is fast.The main electric capacity of body silicon MOS device is the electric capacity between pipe source-drain area and source/leakage diffusion zone and the substrate, and its doping content with substrate increases, and the load capacitance that this will increase circuit influences the operating rate of circuit; In the SOI/MOS device; Because bury the existence of oxide layer, source-drain area and substrate can't form PN junction, parasitic PN junction electric capacity disappears; The substitute is buried oxidation layer electric capacity; This electric capacity is proportional to the dielectric constant of capacitance material, the PN junction parasitic capacitance of its value source-drain area and substrate in the body silicon, and do not receive the influence of scaled down.
4, low-power consumption.The power consumption of SOI/MOS device is made up of quiescent dissipation and two parts of dynamic power consumption, and the SOI device has steep sub-threshold slope, and near desirable level, so leakage current is very little, and quiescent dissipation is very low; Because the SOI/MOS device has junction capacitance and the wire capacitances littler than body silicon device, under the therefore same operating rate, dynamic power consumption also reduces greatly.
From the radioresistance angle analysis, because SOI technology MOS device forms above the oxide layer burying, compare with body silicon, reduced to form the sensitive volume of single-particle inversion effect, so the ability of anti-single particle effect strengthens greatly.But when device continues to receive ionising radiation (like X ray, gamma-rays etc.), can produce the integral dose radiation effect.For SOI technology, because the existence of burying the oxygen medium layer makes that under radiation condition ionization produces the electron-hole pair of some in silica dioxide medium.The electronics major part that mobility is bigger is overflowed, and some electronics and hole be to compound, and to the transportation of SiO2/Si interface, and some is captured by the defective of SiO2 one side at the interface, forms interfacial state under the effect of positive electric field in most of hole.Such positive charge accumulation can cause that device back also forms the passage of a source/leakage, and does not receive the control of preceding grid, causes back of the body gate threshold voltage drift effect and back of the body grid unlatching effect, finally influences the performance of device.
In the world dual mode is adopted in the reinforcing of SOI back of the body matrix effect more at present: 1, utilize technology to reinforce means.Bury oxide layer oxygen implantation dosage and carry out the nitrogen injection simultaneously like low temperature process, silicon oxynitride gate medium, reduction, to add the negative electrical charge complex centre.2, adopt special SOI/MOS device architecture.Do one deck screen on the oxide layer burying, shielding back of the body matrix effect is to the influence of preceding grid.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art, provide a kind of and connect the SOI/MOS device architecture and the manufacturing approach of negative voltage at back of the body grid, improve back of the body matrix effect through the method for circuit design through alloy bonding.
According to technical scheme provided by the invention; A kind ofly comprise at the SOI/MOS device architecture that back of the body grid connect negative voltage through alloy bonding: silicon dioxide buries oxide layer and is positioned on the silicon substrate of back; Silicon dioxide buries monocrystalline silicon source/drain region that oxide layer is provided with silicon tagma, MOS device, the place that silicon dioxide is isolated; Monocrystalline silicon source/the drain region of MOS device be positioned at the silicon tagma around, the place that silicon dioxide is isolated is positioned at around the monocrystalline silicon source/drain region of MOS device; On the silicon tagma, be coated with the silicon dioxide gate dielectric layer of MOS device; Be coated with the polysilicon gate of MOS device on the silicon dioxide gate dielectric layer of said MOS device; On the polysilicon gate of the monocrystalline silicon source/drain region of MOS device and MOS device, be provided with the tungsten alloy through hole, said tungsten alloy through hole is connected the active area of MOS device with the aluminum metal interconnection line; Cover silicon dioxide passivation layer at the MOS device surface, the back of silicon substrate has the alloy contact layer that alloy bonding forms at said back, and contact layer links to each other through the negative voltage that aluminum metal interconnection line and outside provide, for the back silicon substrate provides effective voltage.
Saidly connect the manufacturing approach of the SOI/MOS device of negative voltage at back of the body grid, the steps include: that at first on the silicon substrate of back, forming silicon dioxide buries oxide layer, bury the place that forms silicon tagma and silicon dioxide isolation on the oxide layer at silicon dioxide through alloy bonding; Then, on the silicon tagma,, form the silicon dioxide gate dielectric layer through oxidation; Deposit polysilicon gate on the silicon dioxide gate dielectric layer; Then, inject means through ion, form the monocrystalline silicon source/drain region of MOS device in the tagma on every side, a basic MOS device has just formed; Then, form silicon dioxide passivation layer at the MOS device surface deposit silicon dioxide that forms; Then, connect,, form the tungsten alloy through hole through etching and depositing technics for forming; Utilize the aluminum metal interconnection line that the tungsten alloy through hole is connected with effective voltage again; Deposit once more generates silicon dioxide passivation layer; At last, be that the back of said back silicon substrate forms contact layer through alloy bonding at the MOS structure back of the body grid place that forms.
Advantage of the present invention is: the present invention utilizes the alloy bonding technology that SOI back silicon substrate is drawn, and direct external negative voltage receives the influence of total dose effect and the back of the body gate threshold voltage drift effect that forms thereby improve device at radiation parameter lower back grid.The present invention has improved in the drift of radiation parameter lower back gate threshold voltage device back of the body grid Effect on Performance from the angle of circuit design.Compare with original the reinforcing, simplified processing step, and under the situation that does not influence circuit performance, optimized the performance of circuit under radiation parameter through process means.Eliminated the influence of the back of the body gate threshold voltage drift under radiation parameter of PD SOI technology to circuit.
Description of drawings
Fig. 1 improves the example structure figure of back of the body gate threshold voltage drift for the present invention utilizes bonding technology.
Fig. 2 is PD SOI/MOS device energy band diagram.
Fig. 3 is that PD SOI/MOS device back of the body grid connect the negative voltage energy band diagram.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further.The present invention relates to connect the SOI/MOS device architecture and the manufacturing approach of negative voltage at back of the body grid, through PD SOI/MOS device back silicon substrate is drawn, external negative voltage, thus improve the back of the body matrix effect of radiation condition lower part depletion type SOI/MOS device.The basic principle of this design is: utilize the back silicon substrate to connect negative voltage; Change the Electric Field Distribution in the SOI/MOS device oxygen buried layer; Influencing under the radiation condition positive charge, thereby eliminate the influence of back of the body matrix effect that total radiation dose causes to device performance in the accumulation at the interface of back of the body grid.
As shown in Figure 1; A kind of alloy bonding that utilizes comprises at the SOI/MOS device architecture that back of the body grid connect negative voltage: the oxide layer 2 of burying that silicon dioxide forms is positioned on the back silicon substrate 1; Bury oxide layer 2 be provided with tagma 3 that silicon forms, through silicon ion being injected the source/drain region 5 that forms the MOS device, the place 4 that silicon dioxide is isolated; Source/the drain region 5 of MOS device be positioned at tagma 3 around, the place 4 that silicon dioxide is isolated is positioned at around the source/drain region 5 of MOS device; On tagma 3, be coated with the silicon dioxide gate dielectric layer 6 of MOS device; Be coated with the polysilicon gate 7 of MOS device on the silicon dioxide gate dielectric layer 6 of said MOS device; On the polysilicon gate 7 of source/drain region of MOS device 5 and MOS device, be provided with the through hole 9 of tungsten alloy material, said through hole 9 is connected the active area of MOS device with aluminum metal interconnection line 8; Cover silicon dioxide passivation layer 10 at the MOS device surface.The back of silicon substrate 1 at the back also has the back silicon substrate contact layer 11 that generates the silicon-aluminum material through alloy bonding.Contact layer 11 links to each other through the negative voltage that metal interconnecting wires 8 and outside provide, and according to this structure, negative voltage is that silicon substrate silicon-aluminum contact layer 11 provides negative voltage for back silicon substrate 1 from the back.
Saidly in the manufacturing approach that back of the body grid connect the SOI/MOS device of negative voltage be: at first on back substrate 1, form and bury oxide layer 2, form the place 4 that tagma 3 and silicon dioxide are isolated on the oxide layer burying through alloy bonding.Then, on tagma 3,, form gate dielectric layer 6 through oxidation; Deposit polysilicon gate 7 on gate dielectric layer 6; Then, inject means through ion, 5, one the basic MOS devices of source/drain region that form the MOS device in the tagma around 3 have just formed; Then, form silicon dioxide passivation layer 10 at the MOS device surface deposit silicon dioxide that forms; Then, connect,, form through hole 9 through etching and depositing technics for forming; Utilize metal interconnection line 8 that through hole 9 is connected with effective voltage again; Deposit once more generates silicon dioxide passivation layer 10; At last, be that the back of said back substrate 1 forms contact layer 11 through alloy bonding at the MOS structure back of the body grid place that forms.
As shown in Figure 2, under radiation parameter, the energy band diagram of SOI/MOS device.When the high-energy particle bombardment silicon dioxide layer, ionization goes out a lot of electron-hole pairs, and under effect of electric field, most of electronics drifts to polysilicon gate fast, and the hole will be to silicon dioxide interface step.Having at the interface near silicon dioxide much owing to spread the room of the oxygen atom that stays and the mismatch of lattice, these lattice points and defective just become the trap center in hole.Captured by trap when hole step to silicon dioxide near interface, formed the accumulation (shown in a among the figure) of positive charge.And the existence of interface trap is owing to differ from caused being with at the interface.In the SOI/MOS device, silicon is lower than the energy level of trap at Fermi level at the interface.At this moment, trap will " impose on " electronics and give silicon, and trap itself then becomes positive charge, be piled up in silicon dioxide interface (shown in b among the figure).Because the influence of oxide traps and interface trap finally forms the accumulation of positive charge at silicon dioxide, influenced the performance of SOI/MOS device.E among the figure
cBe the energy level of conduction band, E
vBe the energy level of valence band, E
FiBe intrinsic Fermi level.
As shown in Figure 3, under radiation parameter, the back substrate connects the SOI/MOS device energy band diagram of negative voltage.All depend on effect of electric field because oxide traps and interface trap positive charge are piled up, substrate adds an electric field Δ E at the back, to keep the oxygen buried layer Electric Field Distribution, reduces the accumulation of electric charge under the total dose irradiation condition, and then improves the performance of device.Thereby the back substrate adds negative voltage and suppresses the hole to silicon dioxide interface step, reduces the quantity that positive charge is captured by trap, and then reduces the accumulation (like figure in a process) of positive charge at the silicon dioxide interface.Simultaneously, utilize the electric field Δ E add, raise silicon, reduce the electronics that trap " imposes on ", thereby reduce the accumulation of positive charge at the interface (like b process among the figure) at the interface Fermi level.Except above-mentioned two kinds of inhibition mechanism, substrate connects negative voltage and also makes the threshold voltage of metal-oxide-semiconductor increase at the back.
The present invention has not only solved the uncertain problem of SOI/MOS device back underlayer voltage, and in the process of device manufacturing, need not carry out extra technology to back of the body grid and reinforce, and has simplified processing step.Back of the body grid connect negative pressure, can improve the resistant to total dose ability of PD SOI/MOS circuit, and the performance of other circuit of surface is not had influence.
Unaccomplished matter of the present invention belongs to techniques well known.
Claims (2)
1. connect the SOI/MOS device architecture of negative voltage at back of the body grid through alloy bonding; It is characterized in that; Comprise: silicon dioxide buries oxide layer (2) and is positioned on the back silicon substrate (1); Silicon dioxide buries monocrystalline silicon source/drain region (5) that oxide layer (2) is provided with silicon tagma (3), MOS device, the place (4) that silicon dioxide is isolated; Monocrystalline silicon source/the drain region (5) of MOS device be positioned at silicon tagma (3) around, monocrystalline silicon source/drain region (5) that the place (4) that silicon dioxide is isolated is positioned at the MOS device is on every side; On silicon tagma (3), be coated with the silicon dioxide gate dielectric layer (6) of MOS device; Be coated with the polysilicon gate (7) of MOS device on the silicon dioxide gate dielectric layer (6) of said MOS device; On the polysilicon gate (7) of the monocrystalline silicon source/drain region (5) of MOS device and MOS device, be provided with tungsten alloy through hole (9), said tungsten alloy through hole (9) is connected the active area of MOS device with aluminum metal interconnection line (8); Cover silicon dioxide passivation layer (10) at the MOS device surface; The back of silicon substrate (1) has the alloy contact layer (11) that alloy bonding forms at said back; Contact layer (11) links to each other with the negative voltage that the outside provides through aluminum metal interconnection line (8), for the back silicon substrate provides effective voltage.
2. connect the manufacturing approach of the SOI/MOS device of negative voltage at back of the body grid through alloy bonding; It is characterized in that; At first silicon substrate (1) is gone up formation silicon dioxide and is buried oxide layer (2) at the back, buries oxide layer (2) at silicon dioxide and goes up the place (4) that forms silicon tagma (3) and silicon dioxide isolation; Then, go up through oxidation, form silicon dioxide gate dielectric layer (6) in silicon tagma (3); Go up deposit polysilicon gate (7) at silicon dioxide gate dielectric layer (6); Then, inject means through ion, (3) form the monocrystalline silicon source/drain region (5) of MOS device on every side in the tagma, and a basic MOS device has just formed; Then, form silicon dioxide passivation layer (10) at the MOS device surface deposit silicon dioxide that forms; Then, connect,, form tungsten alloy through hole (9) through etching and depositing technics for forming; Utilize aluminum metal interconnection line (8) that tungsten alloy through hole (9) is connected with effective voltage again; Deposit once more generates silicon dioxide passivation layer (10); At last, be that the back of said back silicon substrate (1) forms contact layer (11) through alloy bonding at the MOS structure back of the body grid place that forms.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194828A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Anti-irradiation SOI (silicon on insulator) device with novel source/drain structure and preparation method thereof |
| CN102270582A (en) * | 2011-07-25 | 2011-12-07 | 中国科学院微电子研究所 | Method for improving back gate threshold voltage of SOI-PMOS device |
| US8080805B2 (en) * | 2010-03-09 | 2011-12-20 | International Business Machines Corporation | FET radiation monitor |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8080805B2 (en) * | 2010-03-09 | 2011-12-20 | International Business Machines Corporation | FET radiation monitor |
| CN102194828A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | Anti-irradiation SOI (silicon on insulator) device with novel source/drain structure and preparation method thereof |
| CN102270582A (en) * | 2011-07-25 | 2011-12-07 | 中国科学院微电子研究所 | Method for improving back gate threshold voltage of SOI-PMOS device |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
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