CN102683419A - Structure and manufacturing method of SOI/MOS device connected to negative voltage on back gate through alloy bonding - Google Patents

Abstract

The invention relates to an SOI/MOS device structure with a back gate connected with a negative voltage and a manufacturing method thereof. The invention has the advantages that: the method not only solves the problem that the substrate voltage at the back of the SOI/MOS device is uncertain, but also does not need to carry out additional process reinforcement on the back gate in the device manufacturing process, thereby simplifying the process steps. The back gate is connected with negative voltage, so that the total dose resistance of the partially depleted SOI/MOS circuit can be improved, and the performance of other circuits on the surface is not influenced.

Description

Structure and manufacturing method of SOI/MOS device connected to negative voltage on back gate through alloy bonding

technical field

The invention relates to the anti-radiation strengthening technology of SOI/MOS devices, in particular to a SOI/MOS device structure and a manufacturing method in which the back gate is connected to a negative voltage through alloy bonding.

Background technique

SOI technology refers to the material preparation technology of forming a single crystal semiconductor silicon thin film layer with a certain thickness on the insulating layer and the process technology of manufacturing semiconductor devices on the thin film layer. This technology can achieve complete dielectric isolation. Compared with bulk silicon devices isolated by P-N junctions, it has the advantages of no latch, high speed, low power consumption, high integration, high temperature resistance, and radiation resistance.

According to the thickness of SOI silicon film, SOI devices can be divided into thick film devices and thin film devices. For thick-film SOI devices, when the thickness of the SOI silicon film is greater than twice the maximum depletion width, it is called a partially depleted device; for thin-film SOI devices, when the thickness of the silicon film is less than the maximum depletion width, it is called a partially depleted device. fully depleted device.

In SOI technology, the device is fabricated in a very thin silicon film on the top, separated from the substrate by a layer of buried oxide. It is this structure that makes SOI/MOS devices have many advantages such as low power consumption. Compared with the traditional bulk silicon MOS process, it is more suitable for high-performance ULSI and VLSI circuits. Its advantages mainly include:

1. No latch-up effect. Due to the existence of the dielectric isolation structure in the SOI/MOS device, there is no current channel to the substrate, the channel of the latch effect is cut off, and the devices are physically and electrically isolated from each other, which improves the reliability of the circuit.

2. The structure is simple, the process is simple, and the integration density is high. The structure of SOI/MOS devices is simple, and there is no need for complex isolation processes such as preparing wells for bulk silicon MOS circuits. The minimum spacing of devices depends only on the limitations of lithography and etching technology, and the integration density is greatly improved. SOI/MOS devices are also particularly suitable for integrating high-voltage and low-voltage circuits on the same chip, so they have high chip area utilization and cost performance.

3. The parasitic capacitance is small and the working speed is fast. The main capacitance of the bulk silicon MOS device is the capacitance between the source and drain regions of the tube and the source/drain diffusion region and the substrate, which increases with the increase of the doping concentration of the substrate, which will increase the load capacitance of the circuit and affect the circuit performance. Working speed; in SOI/MOS devices, due to the existence of the buried oxide layer, the source and drain regions and the substrate cannot form a PN junction, and the parasitic PN junction capacitance disappears, replaced by the buried oxide layer capacitance, which is proportional to the capacitor material The dielectric constant is much smaller than the parasitic capacitance of the PN junction between the source and drain regions and the substrate in bulk silicon, and is not affected by scaling.

4. Low power consumption. The power consumption of SOI/MOS devices is composed of static power consumption and dynamic power consumption. SOI devices have a steep sub-threshold slope, which is close to the ideal level, so the leakage current is very small and the static power consumption is very low; due to SOI/MOS The device has smaller junction capacitance and connection capacitance than bulk silicon devices, so the dynamic power consumption is also greatly reduced at the same operating speed.

From the perspective of anti-radiation analysis, since the SOI process MOS device is formed above the buried oxide layer, compared with bulk silicon, it reduces the sensitive volume for the formation of single event inversion effect, so the ability to resist single event effect is greatly enhanced. However, when the device is continuously exposed to ionizing radiation (such as X-rays, gamma rays, etc.), the total dose radiation effect will occur. For the SOI process, due to the existence of the buried oxide dielectric layer, a certain number of electron-hole pairs are generated by ionization in the silicon dioxide medium under radiation conditions. Most of the electrons with high mobility overflow, some electrons recombine with hole pairs, most of the holes are transported to the SiO2/Si interface under the action of a positive electric field, and some of the holes are captured by the defects on the SiO2 side of the interface, forming interface state. Such positive charge accumulation will cause a source/drain channel to be formed on the back of the device, which is not controlled by the front gate, causing the back gate threshold voltage drift effect and the back gate turn-on effect, which ultimately affects the performance of the device.

At present, there are two ways to strengthen the SOI back gate effect in the world: 1. Using process reinforcement means. Such as low-temperature process, silicon oxynitride gate dielectric, reducing the oxygen implantation dose of the buried oxide layer and performing nitrogen implantation at the same time to add negative charge recombination centers. 2. Adopt special SOI/MOS device structure. Make a layer of shielding layer on the buried oxide layer to shield the impact of the back gate effect on the front gate.

Contents of the invention

The object of the present invention is to overcome the deficiencies in the prior art, provide a SOI/MOS device structure and manufacturing method in which the back gate is connected to a negative voltage through alloy bonding, and improve the back gate effect by means of circuit design.

According to the technical solution provided by the present invention, an SOI/MOS device structure connected to a negative voltage on the back gate through alloy bonding includes: a silicon dioxide buried oxide layer is located on the back silicon substrate, and a silicon dioxide buried oxide layer is provided with Silicon body region, single crystal silicon source/drain region of MOS device, silicon dioxide isolated field region, single crystal silicon source/drain region of MOS device is located around the silicon body region, and silicon dioxide isolated field region is located in MOS device around the monocrystalline silicon source/drain region; the silicon body region is covered with a silicon dioxide gate dielectric layer of a MOS device, and the silicon dioxide gate dielectric layer of the MOS device is covered with a polysilicon gate of a MOS device; in the MOS device The monocrystalline silicon source/drain region and the polysilicon gate of the MOS device are provided with a tungsten alloy through hole, which connects the active area of the MOS device to the aluminum metal interconnection line; the surface of the MOS device is covered with carbon dioxide The silicon passivation layer has an alloy contact layer formed by alloy bonding on the back of the back silicon substrate, and the contact layer is connected to the negative voltage provided by the outside through the aluminum metal interconnection line to provide an effective voltage for the back silicon substrate.

The manufacturing method of the SOI/MOS device connected to the negative voltage on the back gate through alloy bonding, the steps are: firstly, a silicon dioxide buried oxide layer is formed on the back silicon substrate, and a silicon dioxide buried oxide layer is formed on the silicon dioxide buried oxide layer. The body region and the field region isolated by silicon dioxide; then, form a silicon dioxide gate dielectric layer by oxidation on the silicon body region; deposit a polysilicon gate on the silicon dioxide gate dielectric layer; then, by means of ion implantation, in The single crystal silicon source/drain region of the MOS device is formed around the body region, and a basic MOS device is formed; then, silicon dioxide is deposited on the surface of the formed MOS device to form a silicon dioxide passivation layer; then, to form a connection , form tungsten alloy through holes through etching and deposition processes; then use aluminum metal interconnection wires to connect tungsten alloy through holes with effective voltage; deposit again to generate silicon dioxide passivation layer; finally, in the formed The back gate of the MOS structure, that is, the back of the back silicon substrate forms a contact layer through alloy bonding.

The advantage of the present invention is: the present invention uses the alloy bonding technology to lead out the silicon substrate on the back of the SOI, and directly connects the negative voltage externally, thereby improving the back gate threshold voltage drift of the device under the influence of the total dose effect on the back gate under irradiation conditions effect. From the perspective of circuit design, the invention improves the influence of back gate threshold voltage drift on device back gate performance under irradiation conditions. Compared with the original reinforcement through technological means, the technological steps are simplified, and the performance of the circuit under irradiation conditions is optimized without affecting the performance of the circuit. The influence of the back gate threshold voltage drift on the circuit under the irradiation condition of the partially depleted SOI process is eliminated.

Description of drawings

FIG. 1 is a structure diagram of an embodiment of improving back gate threshold voltage drift by using a bonding process according to the present invention.

Figure 2 is the energy band diagram of a partially depleted SOI/MOS device.

Fig. 3 is an energy band diagram of a partially depleted SOI/MOS device with a back gate connected to a negative voltage.

Detailed ways

The present invention will be further described below in conjunction with drawings and embodiments. The invention relates to the SOI/MOS device structure and manufacturing method with a negative voltage connected to the back gate. By leading out the back silicon substrate of the partially depleted SOI/MOS device and externally connecting the negative voltage, the partial depletion SOI/MOS device under radiation conditions can be improved. The back gate effect of MOS devices. The basic principle of the design is to change the electric field distribution in the buried oxide layer of the SOI/MOS device by using the back silicon substrate to be connected to a negative voltage, so as to affect the accumulation of positive charges at the back gate interface under radiation conditions, thereby eliminating the radiation caused by the total dose. The influence of the back gate effect on the device performance.

As shown in Figure 1, an SOI/MOS device structure using alloy bonding to connect the back gate to a negative voltage includes: a buried oxide layer 2 formed of silicon dioxide is located on the back silicon substrate 1, and the buried oxide layer 2 is provided with The body region 3 formed of silicon, the source/drain region 5 of the MOS device and the field region 4 isolated by silicon dioxide are formed by implanting silicon ions, the source/drain region 5 of the MOS device is located around the body region 3, and the silicon dioxide is isolated The field region 4 is located around the source/drain region 5 of the MOS device; the body region 3 is covered with a silicon dioxide gate dielectric layer 6 of the MOS device, and the silicon dioxide gate dielectric layer 6 of the MOS device is covered with a MOS device The polysilicon gate 7 of the MOS device is provided with a tungsten alloy material through hole 9 on the source/drain region 5 of the MOS device and the polysilicon gate 7 of the MOS device, and the through hole 9 connects the active area of the MOS device with the aluminum metal interconnection line 8 connections; the silicon dioxide passivation layer 10 is covered on the surface of the MOS device. On the back of the back silicon substrate 1, there is also a back silicon substrate contact layer 11 made of silicon-aluminum alloy through alloy bonding. The contact layer 11 is connected to the external negative voltage through the metal interconnection line 8. According to this structure, the negative voltage is provided from the back silicon substrate silicon aluminum alloy contact layer 11 to the back silicon substrate 1 with negative voltage.

The manufacturing method of the SOI/MOS device in which the back gate is connected to a negative voltage through alloy bonding is as follows: firstly, a buried oxide layer 2 is formed on the back substrate 1, and a body region 3 and a silicon dioxide isolation layer are formed on the buried oxide layer. field area 4. Then, form a gate dielectric layer 6 by oxidation on the body region 3; deposit a polysilicon gate 7 on the gate dielectric layer 6; then, form a source/drain region 5 of a MOS device around the body region 3 by means of ion implantation, A basic MOS device is formed; then, silicon dioxide is deposited on the surface of the formed MOS device to form a silicon dioxide passivation layer 10; then, in order to form a connection, a through hole 9 is formed by etching and deposition processes; Then use the metal interconnection line 8 to connect the through hole 9 to the effective voltage; deposit again to form a silicon dioxide passivation layer 10; finally, pass through the back gate of the formed MOS structure, that is, the back of the back substrate 1 Alloy bonding forms the contact layer 11 .

As shown in Figure 2, it is the energy band diagram of the SOI/MOS device under irradiation conditions. When high-energy particles bombard the silicon dioxide layer, many electron-hole pairs are ionized. Under the action of the electric field, most of the electrons quickly drift to the polysilicon gate, while the holes will step to the silicon dioxide interface. Near the silicon dioxide interface, there are many oxygen atom vacancies and lattice mismatches left by diffusion, and these lattice points and defects become hole trap centers. When the holes step to the vicinity of the silicon dioxide interface and are trapped by traps, a positive charge accumulation is formed (as shown in a in the figure). The existence of interface traps is caused by the energy band difference at the interface. In SOI/MOS devices, the Fermi level of silicon at the interface is lower than that of the traps. At this time, the trap will "apply" electrons to the silicon, and the trap itself will become positively charged and accumulate at the silicon dioxide interface (as shown in b in the figure). Due to the influence of oxide layer traps and interface traps, a positive charge accumulation is finally formed in silicon dioxide, which affects the performance of SOI/MOS devices. In the figure, E _c is the energy level of the conduction band, E _v is the energy level of the valence band, and E _Fi is the intrinsic Fermi level.

As shown in Figure 3, it is the energy band diagram of the SOI/MOS device with the back substrate connected to a negative voltage under irradiation conditions. Since the accumulation of positive charges in oxide layer traps and interface traps depends on the action of the electric field, an electric field ΔE is applied to the back substrate to maintain the electric field distribution of the buried oxide layer, reduce the accumulation of charges under the total dose irradiation condition, and improve the device performance. performance. A negative voltage is added to the back substrate to inhibit the holes from stepping to the silicon dioxide interface, reduce the number of positive charges captured by traps, and then reduce the accumulation of positive charges on the silicon dioxide interface (a process in the figure). At the same time, using an external electric field ΔE, the Fermi level of silicon at the interface is raised, and the electrons "applied" to the trap are reduced, thereby reducing the accumulation of positive charges at the interface (as shown in process b in the figure). In addition to the above two suppression mechanisms, connecting a negative voltage to the back substrate also increases the threshold voltage of the MOS transistor.

The invention not only solves the problem of uncertain substrate voltage on the back of the SOI/MOS device, but also does not require additional process reinforcement for the back gate during the device manufacturing process, thereby simplifying the process steps. Connecting the back gate to negative pressure can improve the anti-total dose capability of partially depleted SOI/MOS circuits without affecting the performance of other circuits on the surface.

Matters not covered in the present invention belong to the well-known technologies in the art.

Claims (2)

1. An SOI/MOS device structure connected to a negative voltage on the back gate through alloy bonding, which is characterized by: a silicon dioxide buried oxide layer (2) located on the back silicon substrate (1), a silicon dioxide buried oxide layer (2) is provided with a silicon body region (3), a single crystal silicon source/drain region (5) of a MOS device, a silicon dioxide isolated field region (4), a single crystal silicon source/drain region of a MOS device (5 ) is located around the silicon body region (3), and the silicon dioxide isolated field region (4) is located around the single crystal silicon source/drain region (5) of the MOS device; the silicon body region (3) is covered with the The silicon dioxide gate dielectric layer (6), the silicon dioxide gate dielectric layer (6) of the MOS device is covered with the polysilicon gate (7) of the MOS device, in the single crystal silicon source/drain region (5) of the MOS device The polysilicon gate (7) of the MOS device is provided with a tungsten alloy through hole (9), and the tungsten alloy through hole (9) connects the active area of the MOS device with the aluminum metal interconnection line (8); in the MOS device The surface is covered with a silicon dioxide passivation layer (10), and there is an alloy contact layer (11) formed by alloy bonding on the back of the back silicon substrate (1), and the contact layer (11) passes through an aluminum metal interconnection line (8 ) is connected to the negative voltage provided externally to provide an effective voltage for the back silicon substrate. 2. A method for manufacturing an SOI/MOS device connected to a negative voltage on the back gate through alloy bonding, which is characterized in that a silicon dioxide buried oxide layer (2) is first formed on the back silicon substrate (1), and a silicon dioxide buried oxide layer (2) is formed on the silicon dioxide forming a silicon body region (3) and a silicon dioxide isolated field region (4) on the buried oxide layer (2); then, forming a silicon dioxide gate dielectric layer (6) by oxidation on the silicon body region (3); A polysilicon gate (7) is deposited on the silicon dioxide gate dielectric layer (6); then, by means of ion implantation, a single crystal silicon source/drain region (5) of a MOS device is formed around the body region (3), a basic The MOS device is formed; then, deposit silicon dioxide on the surface of the formed MOS device to form a silicon dioxide passivation layer (10); then, in order to form a connection, form a tungsten alloy via hole through etching and deposition processes (9); then use the aluminum metal interconnection line (8) to connect the tungsten alloy through hole (9) to an effective voltage; deposit again to generate a silicon dioxide passivation layer (10); finally, in the formed MOS structure A contact layer (11) is formed at the back gate, that is, the back of the back silicon substrate (1) through alloy bonding.

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