CN102683372B - Pixel structure and generation method of small size CMOS image sensor - Google Patents

Abstract

The invention relates to a complementary metal oxide semiconductor (CMOS) solid image sensor, and provides a small-size CMOS image sensor pixel photodiode structure, which ensures that an optimized small pixel unit can increase full-trap capacity under the condition of no increase of dark current, therefore dynamic range, signal to noise ratio and the like are indirectly increased, and the optimal design of the small pixel unit is completed. In order to achieve the purpose, the technical scheme adopted by the invention is as follows:, according to the small-size CMOS image sensor pixel photodiode structure, a pixel photodiode is formed by injecting a shallower N type region buried layer on a P type epitaxial layer, an N type region is of a U type buried layer structure formed by homotype impurities with larger diffusion coefficients, the middle of the U type buried layer structure is provided with homotype impurities with smaller diffusion coefficients; and an impurity injection layer with a larger diffusion coefficient completely buries an impurity injection layer with smaller diffusion coefficient. The invention is mainly used for designing and manufacturing the CMOS solid image sensor.

Description

Pixel structure and generation method of small size CMOS image sensor

technical field

The present invention relates to a metal complementary oxide semiconductor (CMOS) solid-state image sensor, in particular, to a photodiode structure of a small-sized CMOS image sensor pixel.

Background technique

Image sensors are semiconductor devices that convert incident light signals into electrical signals. According to different working principles, it is mainly divided into two categories: charge coupled image sensor (Charge Coupled Device) and CMOS image sensor (complementary metal-oxide-semiconductor). In recent years, benefiting from the rapid progress of standard CMOS technology and the continuous reduction of feature size, CMOS image sensors can be integrated with more digital-analog circuits on the same chip, realizing low power consumption, low cost, high integration and other CCD The incomparable advantages of image sensors have also promoted the rapid development of CMOS image sensors in recent years.

A CMOS image sensor is composed of a pixel array, an analog front-end circuit, a digital-to-analog conversion unit and a timing control circuit. But at the heart of the overall image sensor architecture is the array of pixel cells. As the basic photosensitive unit of CMOS image sensor, it is mainly divided into active pixel and passive pixel according to the working principle, and can be divided into three-tube active pixel (3T-APS), clamp diode four-tube active pixel ( 4T-APS), clamp diode five-tube active pixel (5T-APS), of which 4T-APS is the mainstream of the market. The traditional 4T-APS cross-sectional structure is shown in Figure 1. The 4T-APS consists of a photodiode (180, 200, 110), a floating diffusion node 160, a transmission tube 170, a reset tube 150, a source follower 140 and an address selector. The through pipes 130 are collectively formed. The photosensitive characteristics of the pixel are largely determined by the size structure and process parameters of these six devices, especially the size structure and process parameters of the photodiode and transmission tube, which will fundamentally affect the final imaging of the entire image sensor Performance is good or bad.

The traditional 4T active pixel photodiode is composed of an N-buried layer 200 implanted on the P-type epitaxial layer 110, together with the high-concentration doped P+ clamping layer 190 and the epitaxial layer 110 formed on the surface, and is used to receive the light incident on the surface of the image sensor. incident photons 111 and generate signal charges corresponding to the intensity of the incident light. Although this structure is mainstream in the design of large-size pixels, if this photodiode structure is used to design small-size pixels, as the feature size in the standard CMOS process decreases, the area of each pixel unit will decrease. The direct impact of this effect The area of the charge collection area will also be reduced accordingly, which will lead to a reduction in the full well capacity of the pixel unit. Under small-sized pixels, the reduction of full well capacity will reduce the dynamic range of the image sensor, the influence of dark current in small pixels will become larger and larger, and the signal-to-noise ratio is low, which seriously affects small-pixel image sensors. imaging effect. Then, how to design the structural size and process parameters of the charge collection region in a small-scale process, so that the image sensor has a small-scale pixel with high full well capacity, low dark current, high signal-to-noise ratio, and high dynamic range at the same time becomes particularly important. important.

In recent years, in order to reduce the insufficient well capacity of small pixels and the resulting problems such as small dynamic range and low signal-to-noise ratio, a concept of multi-step ion implantation to form a layered PD structure was proposed. The structure is shown in the figure 2. In this layered structure, the only N-type implanted region in the traditional PD structure is separated by a high-concentration P+ insertion layer 210, and the entire N-type doped region 200 divided by the P+ insertion layer is formed by a single N-type impurity to complete the doping. In this PD layered structure, the entire N-type region is actually a U-type buried layer structure with an opening to the left and composed of a kind of impurity, which together with the P insertion layer 210 plays the role of collecting signal charges. With this layered PD, when designing a small-sized pixel, the introduction of this layer of heavily doped P+-type insertion layer 210 will completely deplete the area in the core of the photodiode 200 that may not be completely depleted. Ultimately have a larger full well capacity. Obviously, this is achieved by completely depleting the undepleted area to achieve the "activation" effect, that is, increasing the degree of depletion allows more areas to be used to collect photo-generated electrons. However, it should be pointed out that when the N buried layer 200 is completely depleted, it will no longer be effective to use this method to increase the full hydrazine. Other ways to increase the full well capacity: We can also increase the full well capacity by increasing the total amount that the concentration of the entire N buried layer 200 can be depleted. However, this method will inevitably increase the doping concentration of the N-buried layer 200 in contact with the surface P-type clamping layer 190, thereby indirectly increasing the dark current generated at the si-sio2 interface, eventually increasing various noises, and Severely degrades the signal-to-noise ratio. To sum up, there is a mutually restrictive factor between increasing the full well capacity, reducing the dark current, and increasing the signal-to-noise ratio—the doping concentration. How to avoid this mutually restrictive factor and improve the full well capacity, dynamic range, signal-to-noise ratio and other indicators without increasing the dark current will be an important problem to be solved in the design of small pixels.

Contents of the invention

The present invention aims to overcome the deficiencies of the prior art, and provides a photodiode structure of a small-sized CMOS image sensor pixel, so that the optimized small pixel unit can increase the full well capacity without increasing the dark current, thereby completing Indirectly increase the dynamic range, signal-to-noise ratio, etc., and complete the optimal design of the pixel unit under the small pixel. The outer layer of the N-buried layer of the photodiode is composed of another impurity semiconductor to form the inner layer of the N-buried layer of the photodiode. The impurity semiconductor that constitutes the inner layer of the N-buried layer of the photodiode has a higher concentration and a smaller diffusion coefficient than the impurity semiconductor that constitutes the outer layer of the N-buried layer. , the shape of the inner layer of the N-buried layer is U-shaped with the opening to the left, and the middle part of the U-shaped layer is implanted with P-type doping to form a P-inserted layer. At a distance from the transmission tube X, the maximum value of the X range is not greater than the width of the entire photodiode N-buried layer, and the minimum value tends to zero but is always greater than zero. The outer layer of the N-buried layer and the inner layer of the N-buried layer are all buried.

The impurity semiconductor with a large diffusion coefficient is phosphorus, and the impurity semiconductor with a small diffusion coefficient is arsenic.

The size of the pixel structure varies in proportion to form a pixel structure of a large pixel CMOS image sensor.

A method for generating a pixel structure of a small-sized CMOS image sensor, comprising the following steps: choosing to use phosphorus P and arsenic AS with different diffusion coefficients to form an N buried layer, and using phosphorus implantation with a larger diffusion coefficient to form an N buried layer in the first step of implantation The concentration of the outer layer of the outer layer is lower than that of the arsenic implantation in the second step. When the arsenic implantation layer is formed in the second step, its concentration is higher than that of the phosphorus implantation in the first step. At the same time, the implantation energy is controlled so that the phosphorus with a larger diffusion coefficient is finally achieved. The injection layer is an N-buried layer structure in which the arsenic injection layer with a small diffusion coefficient is completely buried. The arsenic injection layer is U-shaped, and a P-type insertion layer is injected in the middle of the U-shaped.

The steps are detailed as follows: implant low-concentration phosphorus into the P-type epitaxial layer with a doping concentration of 1×10 ¹⁵ /cm ³ to form an N-buried outer layer structure, the implantation energy range is 70KeV-220KeV, and the doping concentration The range is 1×10 ¹⁰ /cm3 to 1×10 ¹³ /cm ³ ; re-implant arsenic with a concentration higher than that of the outer layer of the N-buried layer to form the inner layer of the photodiode N-buried layer with double impurities embedded, and the implantation energy range is 70KeV ～290KeV, the doping concentration range is 1×10 ¹¹ /cm3～2.5×10 ¹³ /cm ³ ; using a new mask, the opening range of the mask is, the left side starts from the left boundary of the N buried layer of the photodiode, and the right side At the distance X from the transmission tube, within this window, P-type doped boron difluoride is injected to form a P insertion layer. The implantation energy range of the P insertion layer is 10 keV to 100 keV. The concentration ranges from 1×10 ¹¹ /cm3 to 5×10 ¹³ /cm ³ , and finally forms an embedded photodiode structure composed of impurities with different diffusion coefficients, and its shape is U-shaped with the opening facing left.

If you choose to use N-type doping combinations with different diffusion coefficients at the same time, the selection range is nitrogen, phosphorus, arsenic, antimony, and bismuth.

The opening of the P-type insertion layer is to the right, that is, the N-buried layer of the photodiode is inserted from the left side.

Technical characteristics and effects of the present invention:

The introduction of layered and embedded N-buried layer clamp diodes composed of impurities with different diffusion coefficients, under the premise that the photosensitive area of the pixel remains unchanged,

1. The newly designed small pixel clamp diode has a larger full well capacity. Since the new structure is composed of two kinds of impurities with different diffusion coefficients, a higher dose of arsenic AS implantation can be used to form the inside of the N region, so that the capacity of the new full well is higher than that of the full well formed by a single low dose of phosphorus doping. Larger capacity.

2. The dark current of the newly designed small pixel clamping diode is lower than that of the N buried layer formed entirely by a single high-dose AS doping. Compared with the complete high-dose AS-doped structure (as shown in Figure 4-1), this embedded AS-doped structure has a smaller well capacity than high-concentration arsenic AS-doped, but the dark current generated by it is small. Because the concentration gradient of the entire N buried layer gradually changes from high-concentration AS in the center to low-concentration P, instead of directly adjacent to the P+ clamping layer with high-concentration AS, the resulting dark current is smaller.

3. Due to the superposition of vertical p+/n/n+/p/n+/n/p of the new clamping diode, the physical depth of the new photodiode will also increase within a certain range, thereby increasing the depletion region range in the longitudinal direction, The quantum efficiency of the long-wave spectrum can be increased.

4. The newly designed small pixel clamp diode charge transfer speed is faster. The N region of the clamping diode far away from the transmission tube TX is depleted by the P insertion layer and the potential decreases, while the N region close to the transmission tube TX has more AS injection than the N region far away from TX, so the side close to the TX tube The potential of the clamp diode is higher, which promotes the transfer of photo-generated electrons collected in the N region, and improves the transfer speed of the charge from the N region of the clamp diode to the FD.

Description of drawings

Figure 1 is a cross-sectional view of a traditional 4T-APS pixel unit structure.

Fig. 2 A cross-sectional view of the layered PPD pixel unit structure.

Fig. 3 is a schematic diagram of an N buried layer formed by implantation of a single type of impurity and its corresponding doping distribution curve.

Fig. 4 is a schematic diagram of the embedded N-buried layer PPD structure composed of impurities with different diffusion coefficients used in the present invention and its corresponding concentration distribution curve.

Fig. 5 is a cross-sectional view of the layered and embedded N-buried layer PPD pixel unit structure after applying the present invention to improve Fig. 2 .

Detailed ways

The present invention is a structure optimization based on a layered PD structure, which is used to improve the full well capacity and dynamic range of small pixels without increasing the dark current when designing a small pixel image sensor. In the conventional PPD and the unimproved layered PPD structure (FIG. 1 and FIG. 2), the buried N layer 200 is realized by a single N-type doping, such as phosphorus (P) or arsenic (AS). For the N buried layer doped with phosphorus (P), because P has a relatively high diffusion coefficient during ion implantation, the concentration distribution curve of the N buried layer formed by implantation is easy to form with a lower concentration and a wider range. Large doping concentration distribution, that is, "flat and wide type", as shown in Figure 3B. However, if in order to increase the full well capacity of the small pixel, only a higher dose of AS doping implantation is used to form the N buried layer, the concentration curve of the implanted N buried layer will easily form a curve with a higher concentration but a smaller diffusion range. That is, "narrow and thin type", as shown in Figure 3A. This is because AS has a relatively low diffusion coefficient during ion implantation. However, this high-dose AS implant will cause greater dark current in the N buried layer and Si-SiO2, making the dark current characteristics of the pixel unit worse.

In the present invention, in view of the great difference in the diffusion coefficients of AS and P during ion implantation, especially as the temperature increases, the difference between the two diffusion coefficients becomes larger. As shown in Figure 4, if you choose to use (phosphorus) P and (arsenic) AS with different diffusion coefficients at the same time to form the N buried layer, and when the first step is implanted to form the arsenic layer 240, the dose is relatively large, and the second step is to form the phosphorus implanted layer. 230, the dosage is small, and the implantation energy is controlled at the same time so that the (phosphorus) P implantation layer 230 with a large diffusion coefficient finally embeds the (arsenic) AS implantation layer 240 with a small diffusion coefficient. The structure and concentration-depth curves are shown in Figure 4. Through the N buried layer formed by doping with different diffusion coefficients in two steps, it can be seen that the concentration of P (phosphorus) near the contact area between the upper surface of the N buried layer and the surface P-type layer 180 is lower than the concentration of AS (arsenic) in the center. That is, the AS injection layer provides a higher well capacity, and the P (phosphorus) injection layer makes the concentration gradient of the entire N buried layer gradually change from the high-concentration AS in the center to the lower-concentration P (phosphorus), instead of directly using a high concentration The AS is adjacent to the surface P+-type clamping layer, making the generated dark current smaller. At the same time, the inserted P-type layer can also ensure that the full well capacity increased by the double diffusion coefficient impurity can be completely depleted, thus ensuring that this optimized photodiode structure can be used in small pixels while improving the full well capacity , can optimize dynamic range, signal-to-noise ratio and dark current and other characteristics.

In the present invention, in order to design a small pixel with higher full well capacity without increasing the dark current, the layered PPD structure shown in FIG. 2 is improved by using the structure shown in FIG. 4 . The improved structure is to use this embedded layered N-buried layer clamp photodiode composed of impurities with different diffusion coefficients, and its new structure is shown in Figure 5. The structure at A-A' dotted line place among Fig. 5 is exactly the structure among Fig. 4. The N-buried layer of the entire photodiode is composed of two kinds of impurities with diffusion coefficients. One is the outer layer 320 composed of low-concentration phosphorus. The implantation energy ranges from 70KeV to 220KeV, and the doping concentration ranges from 1e10 to 1e13/cm3 ; One is the inner layer 220 composed of relatively high concentration of arsenic, its shape is an inverted U-shape opening to the left, its implantation energy ranges from 70KeV to 290KeV, and its doping concentration ranges from 1e11 to 2.5e13/cm3. The inner layer of the N buried layer is implanted with P-type doped boron difluoride to form a P insertion layer. The implantation energy range is 10KeV～100KeV, the doping concentration range is 1e11～5e13/cm3, and the distance from the transmission tube is X. Theoretically The variation range of the upper X is: greater than 0, less than or equal to the width of the N-buried layer of the photodiode. Here, the distance of X is controlled to be half of the total width of the N buried layer of the entire photodiode. Compared with the layered PPD shown in Figure 2 in Figure 5, because the upper part of the N-buried layer in contact with the P+ clamping layer is doped with a lower concentration of phosphorus, the dark current is not increased. The increase in well capacity brought about by higher doses of arsenic doping improves important parameters such as dynamic range and signal-to-noise ratio.

AS and P are used as a pair of doping combinations in the present invention because they are relatively common and mature in the existing semiconductor manufacturing process, but it should be pointed out that other types of N-type doping combinations are also applicable. Combinations of arsenic and bismuth are also suitable as long as the isotype doping combinations have different diffusion coefficients. At the same time, almost all N-type doping combinations (nitrogen, phosphorus, arsenic, antimony, bismuth) are applicable.

The present invention uses two kinds of N-type impurities with different diffusion coefficients to form the N-buried layer, and it can also be realized by using three or more N-type impurities with different diffusion coefficients, all of which belong to the scope of the spirit of this patent.

In the embedded layered PD structure adopted in the present invention, its opening faces to the left. However, it should be pointed out that the direction of the opening to the right also belongs to the scope of the spirit of this patent. In the right-opening structure, the insertion range of the P insertion layer is greater than 0 and less than or equal to the width of the N buried layer of the photodiode. The insertion direction is inserted from the right side of the photodiode N buried layer.

The present invention is used to design a small pixel with higher full well capacity without increasing the dark current. However, it should be pointed out that if the patented method is used to design a large-pixel image sensor, it also falls within the scope of the spirit of this patent.

In the present invention, impurities with different diffusion coefficients are implanted multiple times to form an embedded layered N-buried layer clamp photodiode, which is used to improve the restriction relationship between dark current and well capacity when designing small pixels. Its photodiode specific implementation scheme is:

Referring to FIG. 5, a low concentration of phosphorus is implanted on the P-type epitaxial layer 110 with a doping concentration of 1e15/cm3 to form an N-buried outer layer structure 320. The implantation energy ranges from 70KeV to 220KeV, and the doping concentration range is 1e10 ~1e13/cm3; and then inject a higher dose of arsenic to form the N buried layer 220 of the entire photodiode, the implantation energy range is 70KeV-290KeV, and the doping concentration range is 1e11-2.5e13/cm3. P-type doped boron difluoride is implanted again to form a P insertion layer, the implantation energy range is 10KeV-100KeV, and the doping concentration range is 1e11-5e13/cm3. Finally, an embedded photodiode structure composed of impurities with different diffusion coefficients is formed, and its shape is an inverted U shape with the opening facing left.

Below in conjunction with embodiment specifically introduces the best implementation mode:

On the P-type epitaxial layer with a boron doping concentration of 1e15/cm3, N-type impurities are implanted twice to jointly form the N-region of the photodiode. In the first implantation, a traditional PD photoresist is used, and the implanted impurity is phosphorus with an energy of 200KeV and a dose of 0.5e12/cm3 to form a low-concentration N buried layer 320; the second step also uses traditional PD light Engraving plate, implanting impurity as arsenic, its energy is 170KeV, dose is 1.5e12/cm3, used to form the N buried layer part 220 embedded in the whole photodiode; the third step is implanted to form P-type insertion layer 210, need to use a new photodiode The stencil, which is arranged at a distance X from the transmission tube, is implanted with boron difluoride as an impurity, with an implantation energy of 110KeV and a dose of 1e13/cm3 to complete the implantation of the P insertion layer. Finally, the P+ clamping layer is formed by implantation, using a traditional PD photolithography plate, with an implantation energy of 35KeV and a dose of 1e13/cm3.

Using the above process parameters can achieve structural optimization based on the layered PD structure, so as to realize the design of the pixel unit of the small pixel image sensor with higher full well capacity and larger dynamic range without increasing the dark current. design.

Claims (6)

1. small size cmos image sensor dot structure, it is characterized in that, consist of photodiode N buried regions by a kind of extrinsic semiconductor outer, consist of photodiode N buried regions internal layer by another kind of extrinsic semiconductor, the extrinsic semiconductor that consists of photodiode N buried regions internal layer is larger than consisting of the outer extrinsic semiconductor concentration of N buried regions, diffusion coefficient is little, the internal layer of N buried regions is shaped as left U-shaped of opening, U-shaped middle part is injected by the doping of P type and is formed the P insert layer, P insert layer scope left side starts from the photodiode area left border, maximum distance transfer tube X place, right side, X scope maximum is not more than whole photodiode N buried regions width, minimum value trends towards zero but all the time greater than zero, the whole embeddings of internal layer of the outer N buried regions of N buried regions.

2. small size cmos image sensor dot structure as claimed in claim 1, is characterized in that, the extrinsic semiconductor that diffusion coefficient is large is phosphorus, and the extrinsic semiconductor that diffusion coefficient is little is arsenic.

3. small size cmos image sensor dot structure as claimed in claim 1, is characterized in that, the proportional variation of described dot structure size consists of large pixel cmos image sensor dot structure.

4. small size cmos image sensor dot structure generation method, it is characterized in that, comprise the following steps: that phosphorus P and arsenic AS that the choice for use diffusion coefficient is different form the N buried regions jointly, use the larger phosphorus of diffusion coefficient to inject when the first step is injected and form N buried regions skin, its concentration ratio second step arsenic implantation concentration is little, when second step forms the arsenic implanted layer, its concentration ratio first step phosphorus implantation concentration is larger, control simultaneously Implantation Energy and make the N buried structure that finally reaches the whole embeddings of arsenic implanted layer that diffusion coefficient is less of the larger phosphorus implanted layer of diffusion coefficient, the arsenic implanted layer is U-shaped, inject P type insert layer in the middle of U-shaped, P type insert layer left side starts from photodiode N buried regions left margin, P type insert layer right side is Distance Transmission pipe X distance, the excursion of X is: greater than 0, width less than or equal to photodiode N buried regions.

5. dot structure generation method as claimed in claim 4, is characterized in that, described step is refined as: be 1 * 10 in doping content ¹⁵/ cm ³P type epitaxial loayer in inject low concentration phosphorus form N buried regions layer structure, its Implantation Energy scope is 70KeV～220KeV, the doping content scope is 1 * 10 ¹⁰/ cm3 to 1 * 10 ¹³/ cm ³Reinjecting forms the photodiode N buried regions internal layer of two impurity embeddings than the higher arsenic of the outer concentration of N buried regions, its Implantation Energy scope is 70KeV～290KeV, and the doping content scope is 1 * 10 ¹¹/ cm3～2.5 * 10 ¹³/ cm ³Use new mask plate, mask plate opening scope is, the left side starts from photodiode N buried regions left margin, the right side is Distance Transmission pipe X distance, in this window ranges, inject the boron difluoride of P type doping, finally form the P insert layer, P insert layer Implantation Energy scope is 10 kiloelectron-volts～100 kiloelectron-volts, and the doping content scope is 1 * 10 ¹¹/ cm3～5 * 10 ¹³/ cm ³, and the final embedded photoelectric diode structure that is jointly consisted of by different diffusion coefficient impurity that forms, it is shaped as left U-shaped of opening.

6. dot structure generation method as claimed in claim 4, is characterized in that, uses simultaneously the different N-type doping combination of diffusion coefficient, and range of choice is nitrogen, phosphorus, arsenic, antimony, bismuth.

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