CN102683188A - Method for improving writing redundancy of SRAM (static random access memory) - Google Patents
Method for improving writing redundancy of SRAM (static random access memory) Download PDFInfo
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- CN102683188A CN102683188A CN2012101455005A CN201210145500A CN102683188A CN 102683188 A CN102683188 A CN 102683188A CN 2012101455005 A CN2012101455005 A CN 2012101455005A CN 201210145500 A CN201210145500 A CN 201210145500A CN 102683188 A CN102683188 A CN 102683188A
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- random access
- access memory
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- redundancy
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Abstract
The invention provides a method for improving writing redundancy of an SRAM (static random access memory). The method for improving the writing redundancy of the SRAM comprises the steps of covering an upper pull tube region by utilizing additional photoresist besides covering an NMOS (N-channel metal oxide semiconductor) device by utilizing photoresist in an element ion implantation process step of eliminating tensile stress of a PMOS (P-channel metal oxide semiconductor) region when utilizing stress treatment of a tensile stress through-hole etching stop layer, so that element ions are not implanted in the through-hole etching stop layer of the upper pull tube region, thereby keeping tensile stress of an upper pull tube channel. According to the method for improving the writing redundancy of the SRAM disclosed by the invention, the tensile stress of the upper pull tube channel is kept, so that carrier mobility of an upper pull tube device is reduced, and thus the equivalent resistance of an upper pull tube is increased.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field; More precisely, the present invention relates to a kind of static random access memory that improves writes the method for redundancy and has adopted this raising static random access memory to write the static random access memory manufacturing approach of the method for redundancy.
Background technology
Static random access memory (SRAM) has obtained using widely in high-speed data exchange systems such as computer, communication, multimedia as one type of staple product in the semiconductor memory.Shown in Figure 1 is the domain structure of one the 90 common static random access memory cell below the nanometer, includes these three levels of source region, polysilicon gate and contact hole.What zone 1 was marked among the figure is control valve (Pass Gate); This device is a nmos device; What zone 2 was marked is following trombone slide (Pull Down MOS); This device is similarly a nmos device, and what zone 3 was marked is last trombone slide (Pull Up MOS), and this device is a PMOS device.
Writing redundancy (Write Margin) is an important parameter weighing the static random access memory cell write performance; Fig. 2 is that a static random access memory device is being write fashionable work sketch map, and 4 is control valve among the figure, and 5 are following trombone slide; 6 is last trombone slide; Suppose that node 7 storage data are electronegative potential (promptly store data and be " 0 "), corresponding, node 8 storage data are high potential (promptly store data and be " 1 ").Now to write high potential to node 7 node 8 to write electronegative potential be example, before write activity, bit line 9 can be by preliminary filling to high potential; Bit line 10 can be precharged to electronegative potential; When write activity began, word line 11 was opened, because the data of node 7 initial storage are electronegative potential; So during initial condition, last trombone slide 6 opens and descends trombone slide 5 to cut out.Because last trombone slide 6 is all opened with control valve 4, so the current potential of node 8 no longer is " 1 ", but is positioned at a certain intermediate potential.This intermediate potential is determined by the equivalent resistance of last trombone slide 6 and control valve 4.In order to accomplish write activity, the intermediate potential of node 8 must be less than certain numerical value, and promptly the ratio of the equivalent resistance of control valve 4 and last trombone slide 6 must be less than certain numerical value, and the intermediate potential value is low more, static random access memory cell to write redundancy just big more.If the equivalent resistance of trombone slide 6 in the increase just can reduce the intermediate potential of node 8, thereby increase the redundancy that writes of static random access memory cell.
Along with the progress of technology generations, particularly in the following technology generations of 65 nanometers, can adopt via etch to stop ply stress processing (engineering) and improve the cmos device performance.For nmos device, the tensile stress in the raceway groove can be useful to the electron mobility that improves nmos device, therefore can adopt the via etch that produces tensile stress to stop the stress engineering of layer.But the tensile stress in the raceway groove can reduce the hole mobility of PMOS device, for addressing this problem, can adopt element ions such as germanium in the technology, the via etch of PMOS device area is stopped layer bombarding, to discharge the tensile stress of PMOS device area.Like this, can eliminate the negative effect of tensile stress again so that the electron mobility of nmos device improves to the PMOS device.Special, for the last trombone slide 6 among the SRAM, because it is a PMOS device, so can stop the ion bombardment that layer adopts elements such as germanium, the tensile stress in the release in trombone slide 6 raceway grooves to its via etch in the technology usually.
But, be not desirable especially according to the redundancy that writes of the static random access memory of the static random access memory manufacturing approach manufacturing of prior art, so hope can provide a kind of can effectively improve the method that static random access memory writes redundancy.
Summary of the invention
Technical problem to be solved by this invention is to have above-mentioned defective in the prior art, provides a kind of static random access memory that can effectively improve to write the method for redundancy and adopted this raising static random access memory to write the static random access memory manufacturing approach of the method for redundancy.
According to a first aspect of the invention; A kind of method that static random access memory writes redundancy that improves is provided; It is characterized in that comprising: when adopting the tensile stress via etch to stop the ply stress processing; In the element ion injection technology step of the tensile stress of eliminating the PMOS device area, cover the nmos device except adopting photoresist, also adopt additional photoresist will go up the trombone slide zone and cover; Make element ion can not stop layer and inject, thereby kept the tensile stress among the last trombone slide raceway groove the via etch in last trombone slide zone.
Preferably, said element ion is the Ge element ion.
Preferably, the said raising static random access memory method that writes redundancy is used for 45nm and the preparation of following static random access memory is handled.
Preferably, the said raising static random access memory method that writes redundancy realizes through logical operation.
According to a second aspect of the invention, a kind of static random access memory manufacturing approach is provided, it has adopted described according to a first aspect of the invention raising static random access memory to write the method for redundancy.
According to the present invention, owing to kept the tensile stress among the last trombone slide raceway groove, thus reduced the carrier mobility of last trombone slide device, thus the equivalent resistance of last trombone slide increased.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the domain structure of common static random access memory cell.
Fig. 2 schematically shows the circuit structure of static random access memory cell.
Fig. 3 schematically shows the tensile stress sketch map that discharges PMOS device and last trombone slide zone in the prior art.
Fig. 4 schematically shows to have adopted and improves the sketch map of tensile stress of release PMOS device area that static random access memory writes the method for redundancy according to the preferred embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
In improving the method that static random access memory writes redundancy according to the preferred embodiment of the invention, for example through logical operation (Logic Operation), when adopting the tensile stress via etch to stop ply stress handling; In element ion (for example, element ions such as germanium) the injection technology step of the tensile stress of eliminating the PMOS device area, cover the nmos device except adopting photoresist PR1; Adopting additional photoresist will go up trombone slide 6 zones covers; Make element ion such as germanium can not stop layer and inject, thereby kept the tensile stress among last trombone slide 6 raceway grooves, reduced the carrier mobility of last trombone slide 6 devices the via etch in last trombone slide 6 zones; Increased the equivalent resistance of last trombone slide 6; In ablation process, reduced the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.
Fig. 3 is the sketch map that discharges PMOS device area tensile stress in the common technology.As shown in Figure 3; For the device on the wafer substrate 100; Only nmos device is covered by photoresist PR1, PMOS device and last trombone slide 6 among the figure (being similarly a PMOS device) zone be opened (that is, being covered by photoresist); The via etch in PMOS device and last trombone slide 6 zones stops the ion injection (shown in the downward arrow as shown in Figure 3) that layer can carry out elements such as germanium; So in device channel, nmos device is tensile stress F1, the tensile stress F3 in tensile stress F2 in the PMOS device and last trombone slide 6 raceway grooves is released.
Fig. 4 is for discharging the sketch map of the tensile stress of PMOS device area among the present invention.As shown in Figure 4; For the device on the wafer substrate 100; When adopting the tensile stress via etch to stop the ply stress processing; In element ion injection technologies such as germanium (shown in the downward arrow as shown in Figure 4) step of the tensile stress of eliminating the PMOS device area (in other words, when carrying out the ion injection of elements such as germanium at the PMOS device area), except nmos device is covered by photoresist PR1; Last trombone slide 6 zones are also covered by additional photoresist PR2, can not carry out the ion injection of elements such as germanium.Thus, nmos device is tensile stress F1, and the tensile stress F2 in the PMOS device is released, and the tensile stress F 3 that goes up simultaneously in trombone slide 6 raceway grooves is able to keep; The hole mobility of last trombone slide 6 is reduced, thereby has increased the effective resistance of last trombone slide 6, has improved the redundancy that writes of random asccess memory.
Need to prove that though the foregoing description has adopted the present invention that has been example description of Ge element ion, the present invention is not limited to this, but can adopt other suitable element ion.
For example, preferably, the above embodiment of the present invention can be applicable among 45nm and the following static random access memory preparation technology, writes redundancy to improve it.
In addition, according to another preferred embodiment of the invention, the present invention also provides a kind of static random access memory manufacturing approach that has adopted above-mentioned raising static random access memory to write the method for redundancy.
In general, the raising static random access memory according to the present invention static random access memory manufacturing approach that writes the method for redundancy and adopted this raising static random access memory to write the method for redundancy at least also has following technique effect:
1. do not increase existing processing step.
2. when adopting the tensile stress via etch to stop the ply stress processing; In the element ion injection technology steps such as germanium of the tensile stress of eliminating the PMOS device area; Adopt photoresist will go up trombone slide 6 zones and cover, make element ion such as germanium can not stop layer and inject, thereby kept the tensile stress among last trombone slide 6 raceway grooves the via etch in last trombone slide 6 zones; Reduce the carrier mobility of last trombone slide 6 devices, increased the equivalent resistance of last trombone slide 6; And said process can adopt through logical operation and realize.
3. in ablation process, reduce the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (5)
1. one kind is improved the method that static random access memory writes redundancy; It is characterized in that comprising: when adopting the tensile stress via etch to stop the ply stress processing; In the element ion injection technology step of the tensile stress of eliminating the PMOS device area, cover the nmos device except adopting photoresist, also adopt additional photoresist will go up the trombone slide zone and cover; Make element ion can not stop layer and inject, thereby kept the tensile stress among the last trombone slide raceway groove the via etch in last trombone slide zone.
2. raising static random access memory according to claim 1 writes the method for redundancy, it is characterized in that, said element ion is the Ge element ion.
3. raising static random access memory according to claim 1 and 2 writes the method for redundancy, it is characterized in that, the method that said raising static random access memory writes redundancy is used for 45nm and the preparation of following static random access memory is handled.
4. raising static random access memory according to claim 1 and 2 writes the method for redundancy, it is characterized in that, the method that said raising static random access memory writes redundancy realizes through logical operation.
5. a static random access memory manufacturing approach is characterized in that having adopted the method that writes redundancy according to the described raising static random access memory of one of claim 1 to 4.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730469A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | SRAM (static random access memory) unit and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684246A (en) * | 2004-03-30 | 2005-10-19 | 三星电子株式会社 | Low noise and high performance LSI device, layout and manufacturing method |
| US20060226490A1 (en) * | 2005-04-06 | 2006-10-12 | Burnett James D | Interlayer dielectric under stress for an integrated circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684246A (en) * | 2004-03-30 | 2005-10-19 | 三星电子株式会社 | Low noise and high performance LSI device, layout and manufacturing method |
| US20060226490A1 (en) * | 2005-04-06 | 2006-10-12 | Burnett James D | Interlayer dielectric under stress for an integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730469A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | SRAM (static random access memory) unit and forming method thereof |
| US9312263B2 (en) | 2014-01-07 | 2016-04-12 | Shanghai Huadong Grace Semiconductor Manufacturing Corporation | Static random access memory cell and forming method thereof |
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Application publication date: 20120919 |