CN102646641A - Method for improving writing redundancy of static random access memory - Google Patents
Method for improving writing redundancy of static random access memory Download PDFInfo
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- CN102646641A CN102646641A CN2012101381938A CN201210138193A CN102646641A CN 102646641 A CN102646641 A CN 102646641A CN 2012101381938 A CN2012101381938 A CN 2012101381938A CN 201210138193 A CN201210138193 A CN 201210138193A CN 102646641 A CN102646641 A CN 102646641A
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Abstract
The invention provides a method for improving the writing redundancy of a static random access memory. The method comprises the following steps of: when a pressure-stress through-hole etching stopping layer is adopted for stress processing, in the process step of eliminating pressure-stress element ion implantation of an NMOS (N-channel metal oxide semiconductor) device area, opening an upper pulling-pipe area without covering modified photoresist, enabling the upper pulling-pipe area to carry out element ion implantation like the NMOS device area, and carrying out bombardment on the pressure-stress through-hole etching stopping layer by the element ions. According to the method provided by the invention, since the pressure stress in an upper pulling-pipe groove is released, the cavity migration rate of an upper pulling pipe is reduced, the equivalent resistance of the upper pulling pipe is increased and the writing redundancy of the static random access memory is improved.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field; More precisely, the present invention relates to a kind of static random access memory that improves writes the method for redundancy and has adopted this raising static random access memory to write the static random access memory manufacturing approach of the method for redundancy.
Background technology
Static random access memory (SRAM) has obtained using widely in high-speed data exchange systems such as computer, communication, multimedia as one type of staple product in the semiconductor memory.Shown in Figure 1 is the domain structure of one the 90 common static random access memory cell below the nanometer, includes these three levels of source region, polysilicon gate and contact hole.What zone 1 was marked among the figure is control valve (Pass Gate); This device is a nmos device; What zone 2 was marked is following trombone slide (Pull Down MOS); This device is similarly a nmos device, and what zone 3 was marked is last trombone slide (Pull Up MOS), and this device is a PMOS device.
Writing redundancy (Write Margin) is an important parameter weighing the static random access memory cell write performance; Fig. 2 is that a static random access memory device is being write fashionable work sketch map, and 4 is control valve among the figure, and 5 are following trombone slide; 6 is last trombone slide; Suppose that node 7 storage data are electronegative potential (promptly store data and be " 0 "), corresponding, node 8 storage data are high potential (promptly store data and be " 1 ").Now to write high potential to node 7 node 8 to write electronegative potential be example, before write activity, bit line 9 can be by preliminary filling to high potential; Bit line 10 can be precharged to electronegative potential; When write activity began, word line 11 was opened, because the data of node 7 initial storage are electronegative potential; So during initial condition, last trombone slide 6 opens and descends trombone slide 5 to cut out.Because last trombone slide 6 is all opened with control valve 4, so the current potential of node 8 no longer is " 1 ", but is positioned at a certain intermediate potential.This intermediate potential is determined by the equivalent resistance of last trombone slide 6 and control valve 4.In order to accomplish write activity, the intermediate potential of node 8 must be less than certain numerical value, and promptly the ratio of the equivalent resistance of control valve 4 and last trombone slide 6 must be less than certain numerical value, and the intermediate potential value is low more, static random access memory cell to write redundancy just big more.If the equivalent resistance of trombone slide 6 in the increase just can reduce the intermediate potential of node 8, thereby increase the redundancy that writes of static random access memory cell.
Along with the progress of technology generations, particularly in the following technology generations of 65 nanometers, can adopt via etch to stop the ply stress engineering and improve the cmos device performance.For the PMOS device, the compression in the raceway groove can be useful to the hole mobility that improves the PMOS device, therefore can adopt the via etch that produces compression to stop the stress engineering of layer.But the compression in the raceway groove can reduce the electron mobility of nmos device, for addressing this problem, can adopt element ions such as germanium in the technology, the regional via etch of nmos device is stopped layer bombarding, to discharge the compression in nmos device zone.Like this, can eliminate the negative effect of compression again so that the hole mobility of PMOS device improves to nmos device.Special, for the last trombone slide among the SRAM, because it is a PMOS device, so can not stop the ion bombardment that layer adopts elements such as germanium to its via etch in the technology usually, the compression in last trombone slide 6 raceway grooves is held.
But, be not desirable especially according to the redundancy that writes of the static random access memory of the static random access memory manufacturing approach manufacturing of prior art, so hope can provide a kind of can effectively improve the method that static random access memory writes redundancy.
Summary of the invention
Technical problem to be solved by this invention is to have above-mentioned defective in the prior art, provides a kind of static random access memory that can effectively improve to write the method for redundancy and adopted this raising static random access memory to write the static random access memory manufacturing approach of the method for redundancy.
According to a first aspect of the invention; A kind of method that static random access memory writes redundancy that improves is provided; It is characterized in that comprising: when adopting the compression via etch to stop the ply stress processing; In the element ion injection technology step of the compression of eliminating the nmos device zone; Open trombone slide zone so that it does not cover amended photoresist, make and go up the trombone slide the same injection of carrying out element ion with the nmos device zone in zone, element ion stops layer to bombard to the compression via etch in last trombone slide zone thus.
Preferably, all the nmos device zones on the substrate all do not cover amended photoresist.
Preferably, said element ion is the Ge element ion.
Preferably, the said raising static random access memory method that writes redundancy is used for 45nm and the preparation of following static random access memory is handled.
Preferably, the said raising static random access memory method that writes redundancy realizes through logical operation.
According to a second aspect of the invention, a kind of static random access memory manufacturing approach is provided, it has adopted described according to a first aspect of the invention raising static random access memory to write the method for redundancy.
According to the present invention, owing to the compression in the last trombone slide raceway groove is released, thereby reduced last trombone slide hole mobility, increased the equivalent resistance of last trombone slide, improve random asccess memory and write redundancy.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the domain structure of common static random access memory cell.
Fig. 2 schematically shows the circuit structure of static random access memory cell.
Fig. 3 schematically shows the compression sketch map that discharges the nmos device zone in the technology of prior art.
Fig. 4 schematically shows to have adopted and improves the compression sketch map that static random access memory writes the method for redundancy according to the preferred embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
According to the embodiment of the invention, for example through logical operation (Logic Operation), when adopting the compression via etch to stop the ply stress processing; In element ion injection technology (for example adopting element ions such as the germanium) step of the compression of eliminating the nmos device zone; Open trombone slide zone so that it does not cover amended photoresist, make and go up that the trombone slide zone is the same with the nmos device zone can carry out the injection of element ions such as germanium, element ion stops a layer L1 to the regional compression via etch of last trombone slide and bombards thus; Thereby discharged the compression among the last trombone slide raceway groove; Reduce the carrier mobility of last trombone slide device, increased the equivalent resistance of last trombone slide, in ablation process; Reduce the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.
Fig. 3 is the compression sketch map that discharges the nmos device zone in the technology of prior art.For the device on the substrate 100; All nmos device zones among Fig. 3 (schematically utilizing reference number NMOS1 to represent all nmos device zones) are opened (promptly; Do not cover photoresist PR1); Its compression via etch stops the ion injection (seeing shown in the downward arrow of Fig. 3) that layer L1 can carry out elements such as germanium, so in device channel, the compression of nmos device is released (promptly; Element ion stops a layer L1 to the regional compression via etch of nmos device and bombards, to discharge the first raceway groove internal pressure stress F1 in nmos device zone); And still keep the second raceway groove internal pressure stress F2 in all PMOS devices except last trombone slide 6 (schematically utilizing reference number PMOS1 to represent all the PMOS device areas except last trombone slide 6) raceway groove, still keep triple channel internal pressure stress F3 in last trombone slide 6 raceway grooves.
Fig. 4 is among the present invention, the sketch map of trombone slide 6 regional compression in the release.For the device on the substrate 100; When carrying out the ion injection of elements such as germanium in the nmos device zone; All nmos device zones (schematically utilizing reference number NMOS1 to represent all nmos device zones) be opened (that is, not covering photoresist PR1), its compression via etch stops the ion injection (seeing shown in the downward arrow of Fig. 3) that layer L1 can carry out elements such as germanium; So in device channel; The compression of nmos device is released (that is, the regional compression via etch of nmos device is stopped a layer L1 bombard, to discharge the first raceway groove internal pressure stress F1 in nmos device zone).In addition; Different with prior art is; Except all nmos device zones are opened outside (that is, not covering amended photoresist PR2), also open trombone slide 6 zones (promptly; Last trombone slide 6 zones do not cover amended photoresist PR2), make and go up the ion injection that elements such as germanium are carried out in trombone slide 6 zones equally.Triple channel internal pressure stress F 3 in last trombone slide 6 raceway grooves obtains discharging, and the hole mobility of last trombone slide 6 is reduced, thereby has increased the effective resistance of last trombone slide, has improved the redundancy that writes of random asccess memory.
And the photoresist PR2 of all the PMOS devices except last trombone slide 6 after being modified covers; So; All PMOS devices except last trombone slide 6 (schematically utilizing reference number PMOS1 to represent all the PMOS device areas except last trombone slide 6) do not carry out the ion injection of elements such as germanium, still keep the second raceway groove internal pressure stress F2 in its raceway groove.
In addition, according to another preferred embodiment of the invention, the present invention also provides a kind of static random access memory manufacturing approach that has adopted above-mentioned raising static random access memory to write the method for redundancy.
For example, preferably, the above embodiment of the present invention can be applicable among 45nm and the following static random access memory preparation technology, writes redundancy to improve it.
In general, the raising static random access memory according to the present invention static random access memory manufacturing approach that writes the method for redundancy and adopted this raising static random access memory to write the method for redundancy at least also has following technique effect:
1. do not increase existing processing step.
2. when adopting the compression via etch to stop the ply stress engineering; In the element ion injection technology steps such as germanium of the compression of eliminating the nmos device zone; Open the trombone slide zone, make that going up the trombone slide zone can carry out the injection of element ions such as germanium equally, thereby discharged the compression among the last trombone slide raceway groove; Reduce the carrier mobility of last trombone slide device, increased the equivalent resistance of last trombone slide; And but the said method logical operation realizes.
3. in ablation process, reduce the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. one kind is improved the method that static random access memory writes redundancy; It is characterized in that comprising: when adopting the compression via etch to stop the ply stress processing; In the element ion injection technology step of the compression of eliminating the nmos device zone; Open trombone slide zone so that it does not cover amended photoresist, make and go up the trombone slide the same injection of carrying out element ion with the nmos device zone in zone, element ion stops layer to bombard to the compression via etch in last trombone slide zone thus.
2. raising static random access memory according to claim 1 writes the method for redundancy, it is characterized in that, wherein all the nmos device zones on the substrate all do not cover amended photoresist.
3. raising static random access memory according to claim 1 and 2 writes the method for redundancy, it is characterized in that, said element ion is the Ge element ion.
4. raising static random access memory according to claim 1 and 2 writes the method for redundancy, it is characterized in that, the method that said raising static random access memory writes redundancy is used for 45nm and the preparation of following static random access memory is handled.
5. raising static random access memory according to claim 1 and 2 writes the method for redundancy, it is characterized in that, the method that said raising static random access memory writes redundancy realizes through logical operation.
6. a static random access memory manufacturing approach is characterized in that having adopted the method that writes redundancy according to the described raising static random access memory of one of claim 1 to 6.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185894A (en) * | 2020-09-14 | 2021-01-05 | 华虹半导体(无锡)有限公司 | Method for reducing pressure stress of etching stop layer to NMOS device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825568A (en) * | 2005-02-22 | 2006-08-30 | 索尼株式会社 | Method of manufacturing semiconductor integrated circuit |
| US20080142895A1 (en) * | 2006-12-15 | 2008-06-19 | International Business Machines Corporation | Stress engineering for sram stability |
| CN101558494A (en) * | 2005-04-06 | 2009-10-14 | 飞思卡尔半导体公司 | Interlayer dielectric under stress for an integrated circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1825568A (en) * | 2005-02-22 | 2006-08-30 | 索尼株式会社 | Method of manufacturing semiconductor integrated circuit |
| CN101558494A (en) * | 2005-04-06 | 2009-10-14 | 飞思卡尔半导体公司 | Interlayer dielectric under stress for an integrated circuit |
| US20080142895A1 (en) * | 2006-12-15 | 2008-06-19 | International Business Machines Corporation | Stress engineering for sram stability |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185894A (en) * | 2020-09-14 | 2021-01-05 | 华虹半导体(无锡)有限公司 | Method for reducing pressure stress of etching stop layer to NMOS device |
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Application publication date: 20120822 |