CN102662645A

CN102662645A - System-on-a-chip and configuration method of hardware programmable devices of system-on-a-chip

Info

Publication number: CN102662645A
Application number: CN2012100513037A
Authority: CN
Inventors: 王法翔
Original assignee: Fujian Star Net Communication Co Ltd
Current assignee: Fujian Star Net Communication Co Ltd
Priority date: 2012-03-01
Filing date: 2012-03-01
Publication date: 2012-09-12

Abstract

The invention provides a system-on-a-chip and a configuration method of hardware programmable devices of the system-on-a-chip. The system-on-a-chip comprises a central processing unit, a software memory, a software download and debugging interface, hardware programmable devices, a hardware configuration unit and a hardware configuration information download interface, wherein the central processing unit is connected with the software memory, the software download and debugging interface and the hardware configuration unit, and the hardware programmable devices are connected with the hardware configuration unit and the hardware configuration information download interface. The system-on-a-chip further comprises a hardware configuration management unit connected with the central processing unit, wherein the hardware configuration management unit is used to generate control signals which instruct the central processing unit to configure a corresponding hardware programmable device, is used to control the central processing unit to read configuration information of the corresponding hardware programmable device from the software memory, and is used to configure the corresponding hardware programmable device.

Description

The collocation method of the hardware programmable device of SOC(system on a chip) and SOC(system on a chip)

Technical field

The present invention relates to the programming device technology, relate in particular to the collocation method of the hardware programmable device of a kind of SOC(system on a chip) and SOC(system on a chip).

Background technology

(System-on-a-chip SOC) refers to an integrated complete system on single chip to SOC(system on a chip), comprises central processing unit (CPU), storer and peripheral circuit etc., all or part necessary electronic circuit is wrapped the technology of grouping.

Adopt the product of SOC generally all to adopt the main control chip of a SOC chip as product systems, the SOC chip is through Hardware I P that carries or the function of developing this dual mode realization product of embedded software.For first kind of mode, because be that cost is lower in the customization of SOC chip, but a lot of function can not change, and the technical know-how property of product is more weak; The second way, soft IP can satisfy the requirement of sexual function, but on performance, depends on selected SOC chip more, and high performance SOC chip expensive often.So on the basis of these two schemes, occurred a kind of new solution again, promptly a general performance SOC chip adds one group of FPGA.Function to the low performance of product in this scheme realizes with embedded software, realizes with FPGA hardware that for the high performance function of product so promptly satisfy the requirement cheaply of product and satisfy high performance requirement again, the while confidentiality of product is also more intense.

Wherein, FPGA (Field Programmable Gate Array, field programmable gate array) is the very high novel high-performance programmable chip of a kind of integrated level, and its internal circuit function is programmable (Programmable); Can pass through hardware description language (Hardware Description Language; Be called for short HDL) and the special designs instrument, portion realizes extremely complicated circuitry function neatly within it, is applicable to high speed, highdensity high-end digital logic circuit design field.

But the FPGA device is owing to configuration data after the power down can be lost, so before using, need dispose earlier FPGA.

The configuration of FPGA relates to the configuration and the configuration in product volume production stage in production debugging stage.

And the design of adopting the product of SOC not only relates to software and also relates to hardware, and therefore, the production debugging stage not only will be carried out software debugging and also will be carried out hardware debug.

When in the hardware debug process, carrying out the FPGA configuration; As shown in Figure 1, PC changes the JTAG mode through USB hardware information is configured among the FPGA, and hardware designs is revised if desired; Can download among the FPGA through JTAG very easily after the modification compiling and verify, be convenient to debugging.The general FPGA of this method manufacturer all can provide, and the instrument FPGA manufacturer that USB changes JTAG generally also can provide.But, during each software debugging, need the hardware personnel to download code to earlier among the FPGA, could begin software debugging then.If careless power down in the process of software debugging; Need the hardware personnel again once so, increased a lot of expenses of hardware development personnel so virtually, also increased software developer's workload the FPGA configuration; Cause the production debugging complex operation, also increased time cost.And such SOC is not owing to store the configuration information of FPGA, and when power down, the data of FPGA configuration can all be lost, and therefore can not directly get into the volume production stage as finished product.

In order to address the above problem, the extra external memory storage that increased on SOC is used for storing the configuration information of FPGA.As shown in Figure 2, when SOC starts, at first from external memory storage, configuration information is read out, be configured among the FPGA, FPGA operates then.When the product power down was restarted, CPLD or FPGA can read out from the configuration information of external memory storage the inside with the FPGA of needs, so this SOC can be used for the volume production stage.But SOC is many external memory storage makes the SOC cost increase.And the configuration information of FPGA needs programming to arrive external memory storage, perhaps need design extra block configuration in external memory storage, causes the workload of hardware designs to increase, and has further increased the cost of product.

Also have a kind of collocation method as shown in Figure 3, configuration information directly is configured to FPGA through JTAG, perhaps configuration information is stored in the external memory storage through CPLD.When SOC powered up again, CPLD or FPGA initiatively read configuration information from external memory storage, and are configured.In the time of new configuration information, original configuration information is covered through JTAG.So both be convenient to download, the FPGA allocation problem during the actual product that can solve product is again used, but shortcoming remains and increased external memory storage, increased the cost of product.

Another kind of collocation method is that hardware configuration information is kept in the external memory storage of embedded system, and through the mode of software the configuration information in the external memory storage is configured among the FPGA.As shown in Figure 4, the configuration sequential of CPU simulation FPGA is configured to hardware information among the FPGA.This technical scheme does not need extra increase memory device, has reduced the cost of product, both can be used for the product development debugging, can be used for actual product again.But; Because FPGA configuration information and the shared external memory storage of embedded system; The Products Development debug phase hardware designs personnel software design personnel that must seek help the hardware configuration information file is put in the software systems; Recompility downloads on the plank of SOC, and the hardware designs personnel could debug then.

In the collocation method of above-mentioned SOC(system on a chip) and FPGA; Need the Hardware configuration personnel earlier all FPGA to be configured during software debugging, and then software debugging, when the SOC(system on a chip) power down; Also need the hardware debug personnel to get involved once more; FPGA to all is configured, and is unfavorable for the division of labor operation of software development debugging and hardware development debugging, causes the increase of time of product development length and cost.And the configuration to FPGA in the hardware debug is configured FPGA all in the SOC(system on a chip) through external memory device or JTAG; When wherein configuration failure or the inefficacy of a certain FPGA; Then need once more all FPGA to be configured, further reduced debugging efficiency, increased the cost of product.

Summary of the invention

The present invention provides the collocation method of the hardware programmable device of a kind of SOC(system on a chip) and SOC(system on a chip), is used to solve existing on-chip system developing debugging cost problem of higher.

A kind of SOC(system on a chip) provided by the invention; Comprise central processing unit, software memory, software download and debugging interface, hardware programmable device, Hardware configuration unit and hardware configuration information download interface; Said central processing unit and said software memory, software download and debugging interface, and the Hardware configuration unit link to each other; Said hardware programmable device links to each other with said Hardware configuration unit and hardware configuration information download interface; Wherein, Also comprise: the Hardware configuration administrative unit that links to each other with said central processing unit; Said Hardware configuration administrative unit is used to generate the control signal of the said central processing unit configuration of indication corresponding hardware programming device, controls said central processing unit reads said corresponding hardware programming device from said software memory configuration information, and said corresponding hardware programming device is configured.

The collocation method of the hardware programmable device of a kind of SOC(system on a chip) provided by the invention comprises:

Generate the control signal of indication central processing unit configuration corresponding hardware programming device according to the debug of hardware and software demand; Control said CPU reads said corresponding hardware programming device from software memory configuration information, and said corresponding hardware programming device is configured.

The collocation method of the hardware programmable device of SOC(system on a chip) provided by the invention and SOC(system on a chip); Not only guaranteed the clear division of product development debug phase soft or hard work; And avoided the repeated configuration of unnecessary FPGA; Improve the efficient of production debugging, reduced the developing and debugging cost of SOC(system on a chip), also satisfied the configuration needs of the FPGA in product volume production stage.

Description of drawings

Fig. 1 is for carrying out the synoptic diagram of FPGA configuration in the hardware debug process in the prior art;

Fig. 2 is for carrying out the synoptic diagram that FPGA disposes through external memory storage in the prior art;

Fig. 3 is an another kind of hardware configuration method synoptic diagram in the prior art;

Fig. 4 is another hardware configuration method synoptic diagram in the prior art;

The structural representation of a kind of SOC(system on a chip) that Fig. 5 provides for the embodiment of the invention;

The structural representation of the another kind of SOC(system on a chip) that Fig. 6 provides for the embodiment of the invention;

The FPGA configuration flow figure of the SOC(system on a chip) software development debug phase that Fig. 7 provides for the embodiment of the invention;

The FPGA configuration flow figure of the SOC(system on a chip) hardware development debug phase that Fig. 8 provides for the embodiment of the invention;

The SOC(system on a chip) that Fig. 9 provides for the embodiment of the invention is at the FPGA in product volume production stage configuration flow figure.

Embodiment

The structural representation of a kind of SOC(system on a chip) that Fig. 5 provides for the embodiment of the invention.As shown in Figure 5, SOC(system on a chip) comprises central processing unit 51, software memory 52, software download and debugging interface 53, hardware programmable device 54, Hardware configuration unit 55, hardware configuration information download interface 56 and Hardware configuration administrative unit 57.

Said central processing unit 51 links to each other with said software memory 52, software download and debugging interface 53, Hardware configuration unit 55 and Hardware configuration administrative unit 57.Central processing unit 51 can be with software download and debugging interface 53 downloaded software data storage in software memory 52.Central processing unit 51 operation back reading software data from software memory 52 realize product function.Central processing unit 51 also can be configured to hardware programmable device 54 through Hardware configuration unit 55 with the hardware configuration information in the software memory 52.

Said hardware programmable device 54 can be field programmable gate array (FPGA); Link to each other with said Hardware configuration unit 55 and hardware configuration information download interface 56; That is to say; Hardware programmable device 54 both can be configured by Hardware configuration unit 55, also can directly be configured by the configuration information that hardware configuration information download interface 56 is downloaded.

Said Hardware configuration administrative unit 57 is used to generate the control signal of the said central processing unit configuration of indication corresponding hardware programming device; Control said central processing unit 51 and from said software memory 52, read the configuration information of stating the corresponding hardware programming device, and the corresponding hardware programming device is configured.

As, said Hardware configuration administrative unit 57 can be and the identical control device of said hardware programmable number of devices, and (General Purpose Input/Output's general input/output port of said control device and said central processing unit 51 GPIO) links to each other.This control device can be the function element of wire jumper, switch key and so on.

The quantity of wire jumper is identical with the quantity of hardware programmable device 54 in the Hardware configuration administrative unit 57; Wire jumper is corresponding one by one with hardware programmable device 54; " opening " state that can be through wire jumper as put 1 or " pass " state as putting 0; Whether control central processing unit 51 reads the configuration information of corresponding hardware programming device from software memory 52, and the corresponding hardware programming device is configured.As when wire jumper is set to 1, control central processing unit 51 reads the configuration information of corresponding hardware programming device from software memory 52, and the corresponding hardware programming device is configured.

The SOC(system on a chip) that the embodiment of the invention provides also can comprise the configuration indicating member that links to each other with said central processing unit 51, is used to show the configuration result of said hardware programmable device.

Said configuration indicating member can be light emitting diode (LED) lamp group, links to each other with the GPIO of said central processing unit 51.

Above-mentioned hardware programmable device 54 is field programmable gate array (FPGA), and Hardware configuration unit 55 can be CPLD, and hardware configuration information download interface 56 is JTAG (Joint Test Action Group; Combined testing action group).

Above-mentioned software memory 52 can be Nflash (NAND Flash), hard disk etc., and software download and debugging interface 53 can be serial ports, parallel port etc.

It will be understood by those skilled in the art that to SOC(system on a chip) also should be provided with the basic functional units that storage starts the SOC(system on a chip)s such as flash memory of software,, repeat no more here owing to be not emphasis of the present invention.

In the present embodiment; SOC(system on a chip) is controlled said central processing unit through the Hardware configuration administrative unit and is selected whether read configuration information from said software memory; And said hardware programmable device is configured; Need not to be configured when making the software development debugging, the hardware programmable device is configured, need not other config memory and come the storage hardware configuration information specially and can read configuration information through existing software memory such as Nflash fully from hardware configuration information download interface such as JTAG; Not only practice thrift carrying cost, and avoided hardware development commissioning staff's participation; And during the hardware development debugging; Hardware programmable device for some or some configuration failure; Can be through the Hardware configuration administrative unit be set; Make central processing unit from software memory, read the configuration information of the hardware programmable device of this or those configuration failures when carrying out application initializes, and the hardware programmable device of this or those configuration failures is configured, and the participation that need not the software development commissioning staff just can reconfigure the hardware programmable device from software memory; Not only guaranteed the clear division of product development debug phase soft or hard work; And avoided the repeated configuration of unnecessary FPGA, and improved the efficient of production debugging, also satisfied the configuration needs of the FPGA in product volume production stage.

The structural representation of the another kind of SOC(system on a chip) that Fig. 6 provides for the embodiment of the invention.In the present embodiment, the hardware programmable device is FPGA, and the Hardware configuration unit is CPLD, and the hardware configuration information download interface is JTAG, and software download and debugging interface are serial ports, and software memory is Nflash.

As shown in Figure 6, SOC(system on a chip) comprises: CPU 61, Nflash 62, serial ports 63, hardware programmable device 64, CPLD 65, JTAG 66, Hardware configuration administrative unit 67, Hardware configuration indicating member 68 and Norflash 69.

Wherein, CPU 61 is primary processors of SOC(system on a chip), and the function of SOC(system on a chip) all is under the control of CPU 61, to realize, and is all essential in Products Development debug phase and volume production stage.

Serial ports 63 is software developer's interface through hyper terminal realization software download and debugging on PC, and is indispensable in software debugging, optional in the product volume production.

JTAG 66 is the download interface of the configuration information of FPGA.Hardware designs personnel develop software through the FPGA of PC, the configuration information of FPGA is changeed jtag controller through USB download to JTAG66, download to FPGA through JTAG 66 again.JTAG 66 is essential when hardware debug, in the product volume production, does not need.

Hardware configuration administrative unit 67 is the one group of wire jumper that is connected the GPIO of CPU 61: wire jumper 0, wire jumper 1 ... wire jumper n.The numerical value 0 or 1 that reads wire jumper through software separates software development debugging and hardware development debugging, and is essential in the developing and debugging stage, optional in the product volume production stage.

Before system start-up, at first wire jumper to be set, the startup that resets then, in the process of startup, system can judge whether from Nflash, to read configuration data according to the numerical value that reads, and is that example describes with two FPGA here, and the implication of numerical value is as shown in table 1.

The implication of table 1 wire jumper numerical value

Hardware configuration indicating member 68 be one group of LED (light emitting diode): LED0 ... LEDn.Identifying current FPGA configuration information through one group of GPIO driving LED lamp is from Nflash 62, to read or from JTAG 66, download; Just identifying FPGA still is to dispose from JTAG from the Nflash configuration; Whether successfully whether the configuration information that also identifies simultaneously Nflash 62 is wrong, also promptly identify configuration result still failure.

As with the color of LED lamp and whether glimmer and identify configuration result, be that example describes with two FPGA, the implication of color and flicker is as shown in table 2.

The implication of table 2LED lamp color and flicker

Hardware programmable device 64 is carriers of the high-performance module in the SOC product, and the object of configuration all must lack with the volume production stage in the Products Development debugging.In the present embodiment, hardware programmable device 64 has a plurality of: FPGA0, FPGA1 ... FPGAn.

FPGA disposes three kinds of patterns: aggressive mode, Passive Mode and JTAG pattern.Aggressive mode is that FPGA initiatively initiates read operation to external memory storage.Passive Mode is the operation of the configuration FPGA that initiatively initiates of devices such as outside CPU or CPLD.The JTAG pattern is the mode with JTAG command configuration FPGA, and this pattern is supported daisy chain, can the cascade multiple FPGA.

In the SOC(system on a chip) that the embodiment of the invention provides, the configuration mode of FPGA can adopt passive configuration mode and JTAG configuration mode.Wherein, the configuring sponsor party of Passive Mode is CPU, and the initiator of JTAG configuration mode is PC.

The passive configuration mode of FPGA is through the configuration of piece of CPLD management multiple FPGA, and the general flow of configuration comprises:

CPU in the SOC(system on a chip) reads out configuration information through the low-speed interface of system from Nflash and writes CPLD;

CPLD receives after the data of low-speed interface, transfers the sequential of low-speed interface the configuration sequential of FPGA to, and configuration information is write among the FPGA;

Wait for that it is after configuration information all is configured to FPGA that configuration finishes, and the result that will dispose feeds back to CPU, the result that CPU will dispose passes through GPIO driving LED lamp, and configurations shown result makes to the developing and debugging personnel and knows.

The JTAG configuration mode of FPGA is that PC downloads the FPGA that disposes the multi-disc same kind through the cascade of JTAG, and general flow comprises:

With the JTAG pin cascade of each FPGA, it is parallelly connected with the TMS pin to be about to TCK on the SOC circuit board, and TDI connects with the TDO pin;

The hardware program of every FPGA is compiled, and is the configuration information of FPGA but generate file in download;

But the file in download that generates is corresponding with the waterfall sequence of FPGA, all download through JTAG;

Download the result who detects download after accomplishing,, need whether damage data, process of downloading and fpga chip and check if wrong.

At two kinds of above-mentioned configuration modes, adopt the mode of parallel connection for the passive configuration mode of FPGA, every FPGA can dispose separately, can not break down because of fpga chip wherein, and cause occurring the situation that other fpga chip all can't dispose.

CPLD 65 mainly contains two functions, and the one, during operate as normal, accomplish the low frequency protocol conversion or the management of CPU to the fpga chip group, this function is the basic function of CPLD among the SOC, does not belong to emphasis of the present invention, repeats no more here; The 2nd, when FPGA disposes, accomplish the configuration sequential that the low frequency agreement sequential of SOC is converted into FPGA.All essential in Products Development debugging and volume production stage.

Nflash 62 is the devices of depositing of the main application system code of SOC(system on a chip), and software needs frequent download in the developing and debugging stage, and is all essential in product development debug phase and volume production stage.

Norflash 69 be starting system on chip start-up code (BOOT) deposit device; Just no longer change the stable back of the start-up code of regular software system; The frequency of changing in the Products Development debug phase is very low, and Products Development debug phase and volume production stage all need.

Among Fig. 6, PC is the computing machine of SOC(system on a chip) being developed debugging, is software development debugging and hardware development debugging imperative equipment instrument, in the product volume production, does not need.USB changes the converter that JTAG is the USB commentaries on classics JTAG of FPGA, and general FPGA manufacturer all can provide, and is essential during hardware debug, do not need during the product volume production.

The flow process of the configuration of hardware programmable device 64 is divided into two parts, and the one, at the configuration flow of Products Development debug phase, the 2nd, at the configuration flow in volume production stage of product.

When SOC(system on a chip) is developed debugging, relate to the FPGA configuration flow in the hardware development debugging, also relate to the FPGA configuration flow in the software development debugging.

As shown in Figure 7, during the software development debugging, the configuration information of FPGA and the software of completion are carried out the software systems compiling together, obtain compiling file.After the BOOT of SOC(system on a chip) got up, control desk downloaded to SOC(system on a chip) with compiling file through serial ports, and was written among the Nflash 62.

In the control desk software program for execution, software program at first enters into application initializes then, need be configured FPGA in the application initializes stage.

When FPGA is configured; At first with wire jumper 0, wire jumper 1 ... wire jumper n all puts 0 or all put 1; With control CPU 61 from Nflash 62 read FPGA0, FPGA1 ... the configuration information of FPGAn, respectively to FPGA0, FPGA1 ... FPGAn is configured.When having avoided the software development debugging, need carry out the FPGA configuration, thereby make the hardware and software development debugging not disturb mutually from JTAG.

CPU 61 sends to CPLD 65 through low-speed interface with configuration information; CPLD 65 converts the low-speed interface sequential of CPU 61 into the configuration sequential of FPGA 64; Completion is to the configuration of FPGA; After the configuration of all FPGA is accomplished, the result who disposes is shown through the LED in the Hardware configuration indicating member 68.

Afterwards, carry out FPGA and reset, and operation software to be debugged, debug.

As shown in Figure 8, in hardware development when debugging,, at first the configuration information with FPGA downloads to the hardware programmable device 64 from JTAG, directly to FPGA0, FPGA1 ... FPGAn is configured.

Then SOC(system on a chip) is resetted, start after CPU 61 carries out BOOT, automatically from Nflash 62, read the software stored code, and carry out.

When application initializes; In the wire jumper in the Hardware configuration administrative unit 67, setting is arranged; Read configuration information with control CPU 61 from Nflash 62 FPGA of correspondence is configured, then after the application initializes in the software code, this corresponding FPGA is configured.

Particularly, the hardware development debug phase, can start the back with control CPU 61 and once more this corresponding FPGA is configured being provided with from the corresponding wire jumper of FPGA that Nflash 62 reads configuration from the configuration information that Nflash 62 reads corresponding FPGA.As wire jumper 1 is set to 1, then CPU 61 starts the configuration information that afterwards reads FPGA1 from Nflash 62, covers 66 pairs of FPGA1 information configured of JTAG, again FPGA1 is configured, and makes that the configuration of FPGA is more flexible.And; Invalid when the configuration information of the FPGA1 that downloads from JTAG, damage or when losing; Stored configuration information realizes the configuration to FPGA1 among the Nflash 62 capable of using, has solved the problem of the FPGA configuration failure that causes because of hardware configuration information inefficacy in the hardware development.

After the FPGA configuration is accomplished, move hardware program to be debugged, debug.

Can find out from above-mentioned developing and debugging flow process; Through the wire jumper of the Hardware configuration administrative unit 67 in the SOC(system on a chip), when carrying out the FPGA configuration, can very easily software development debugging and hardware development debugging be separated; Make software development commissioning staff and hardware development commissioning staff be independent of each other; Can main energy be placed on own the thing that will pay close attention to, practice thrift human cost effectively, improve the Products Development debugging efficiency.

As shown in Figure 9, SOC(system on a chip) is in the product volume production stage, and the back CPU 61 that at first powers on carries out BOOT.

After CPU 61 starts, from Nflash 62, the run time version of software is called in Installed System Memory, the while also reads out the configuration information of FPGA, and software program for execution gets into application initializes.

In the application initializes program, all FPGA are configured.At this moment all wire jumpers in the Hardware configuration administrative unit 67 in the SOC(system on a chip) all are set to from Nflash 62, read configuration information.

After all configurations are accomplished, get into the realization of product function.

In the SOC(system on a chip) that the embodiment of the invention provides,, make software development debugging and hardware development debugging not disturb mutually through the source of reading of Hardware configuration administrative unit control hardware configuration information; Guaranteed the clear division of software and hardware task; Reduce hardware and software development personnel's phase mutual interference effectively, reduced the manpower expense of coordinating, accelerated the developing and debugging speed of SOC(system on a chip); Shorten the Time To Market of product, thereby effectively reduced the whole R&D costs meeting of product.And the production debugging stage has only increased by one group of wire jumper and one group of LED lamp, with respect to the external memory storage that increases in traditional technical scheme, has practiced thrift the Material Cost of product effectively.

The collocation method of the hardware programmable device of the SOC(system on a chip) that the embodiment of the invention provides; Be used for the SOC(system on a chip) that the foregoing description provides is configured; Comprise: the control signal that generates indication central processing unit configuration corresponding hardware programming device according to the debug of hardware and software demand; Control said CPU reads said corresponding hardware programming device from software memory configuration information, and said corresponding hardware programming device is configured.

Like the software development commissioning staff when carrying out software debugging; All wire jumpers in the Hardware configuration administrative unit that the foregoing description provides are set to 1; Also be that the Hardware configuration administrative unit generates control signal 1...1, after CPU reads control signal, when carrying out application initializes; Read configuration information from Nflash, hardware programmable device such as FPGA are configured through CPLD.

Perhaps as, when the hardware development commissioning staff carries out hardware debug, accomplish JTAG configuration to FPGA after; Also need the configuration information of a certain FPGA be covered; Reconfigure, the wire jumper that then this FPGA is corresponding is set to 1, and the wire jumper that all the other FPGA are corresponding is set to 0.The control signal that after CPU starts, reads this FPGA is 1, then reads configuration information from Nflash, through CPLD this FPGA is configured, thereby realizes reconfiguring of this FPGA.

Alternatively, the collocation method of the hardware programmable device of the SOC(system on a chip) that the embodiment of the invention provides also can further comprise: the configuration result that shows said hardware programmable device.

As the Hardware configuration indicating member that adopts said system embodiment to provide shows, specifically sees above-mentioned explanation in embodiment illustrated in fig. 6 for details.

In the present embodiment; SOC(system on a chip) generates control signal through control; Control said central processing unit and select whether read configuration information from said software memory; So that said hardware programmable device is configured, need not to be configured when making the software development debugging from hardware configuration information download interface such as JTAG, and can read configuration information through software memory such as Nflash fully the hardware programmable device is configured; Thereby avoided hardware development commissioning staff's participation, guaranteed the clear division of product development debug phase soft or hard work.And also satisfied the configuration needs of the FPGA in product volume production stage.

Among said system and the method embodiment; SOC(system on a chip) is controlled reading of configuration information through Hardware configuration administrative unit such as wire jumper; Realize configuration to the FPGA of multi-disc same kind; Make software development debugging and hardware development debugging to separate, thereby the developing and debugging personnel put into the own place of being paid close attention to energy, reduced the human cost of developing and debugging.Also can make the problem of running in the developing and debugging personnel positioning product development debug process quickly and easily, shorten the research and development time of product.And reduced the SOC(system on a chip) in developing and debugging stage and the difference between the SOC(system on a chip) in volume production stage as much as possible, thus shortened time to market (TTM), reduced the device cost of product.

The FPGA collocation method of above-mentioned SOC(system on a chip) also can be expanded programmable system on chip (the System On a Programmable Chip that is applied to single-chip or multicore sheet; SOPC) in; Through being connected the wire jumper of the GPIO pin on the SOPC chip, realize easily the part configuration able to programme in the system, and can be with software and hardware work separately; Satisfy the demand of system development debugging and volume production, reduce the SOPC cost.

One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each method embodiment can be accomplished through the relevant hardware of programmed instruction.Aforesaid program can be stored in the computer read/write memory medium.This program the step that comprises above-mentioned each method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

What should explain at last is: above each embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although the present invention has been carried out detailed explanation with reference to aforementioned each embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, perhaps to wherein part or all technical characteristic are equal to replacement; And these are revised or replacement, do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.

Claims

1. SOC(system on a chip); It is characterized in that; Comprise central processing unit, software memory, software download and debugging interface, hardware programmable device, Hardware configuration unit and hardware configuration information download interface; Said central processing unit and said software memory, software download and debugging interface, and the Hardware configuration unit link to each other; Said hardware programmable device links to each other with said Hardware configuration unit and hardware configuration information download interface; Also comprise: the Hardware configuration administrative unit that links to each other with said central processing unit; Said Hardware configuration administrative unit is used to generate the control signal of the said central processing unit configuration of indication corresponding hardware programming device, controls said central processing unit reads said corresponding hardware programming device from said software memory configuration information, and said corresponding hardware programming device is configured.

2. SOC(system on a chip) according to claim 1 is characterized in that, said Hardware configuration administrative unit is and the identical control device of said hardware programmable number of devices that said control device links to each other with the general input/output port of said central processing unit.

3. SOC(system on a chip) according to claim 1 and 2 is characterized in that, also comprises the configuration indicating member that links to each other with said central processing unit, is used to show the configuration result of said hardware programmable device.

4. SOC(system on a chip) according to claim 3 is characterized in that, said configuration indicating member is the LED light lamp group, links to each other with the general input/output port of said central processing unit.

5. SOC(system on a chip) according to claim 1 and 2 is characterized in that, said hardware programmable device is a field programmable gate array, and said Hardware configuration unit is CPLD, and said hardware configuration information download interface is JTAG.

6. SOC(system on a chip) according to claim 1 and 2 is characterized in that, said software memory is Nflash, and said software download and debugging interface are serial ports.

7. SOC(system on a chip) according to claim 2 is characterized in that, said control device is wire jumper, switch or button.

8. the collocation method of the hardware programmable device of a SOC(system on a chip) is characterized in that, comprising:

9. the collocation method of the hardware programmable device of SOC(system on a chip) according to claim 8 is characterized in that, also comprises:

The configuration result that shows said hardware programmable device.