CN102662134A

CN102662134A - Analog self-check figure implementing device for charged coupled device (CCD) imaging system

Info

Publication number: CN102662134A
Application number: CN2012101370492A
Authority: CN
Inventors: 王文华; 张宇; 李国宁; 韩双丽
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2012-05-04
Filing date: 2012-05-04
Publication date: 2012-09-12
Anticipated expiration: 2032-05-04
Also published as: CN102662134B

Abstract

The invention discloses an analog self-check figure implementing device for a charged coupled device (CCD) imaging system, relates to the technical field of space remote sensing imaging, and solves the problem that the conventional self-check figure implementing device only can detect a function link from a field programmable gate array (FPGA) to an image data output interface but cannot detect critical function links such as a video analog-to-digital (AD) chip. The analog self-check figure implementing device is used for self-checking a circuit state of a remote sensing camera. A CCD video signal and an analog self-check signal enter the input end of a video AD module timely under the control of an FPGA module, and the CCD imaging system is self-checked. By the device, analog self-check figures and CCD video signals are not interfered with each other, and can be transmitted to the video AD module in different time, and an aim of detecting the working state of the whole CCD imaging system is fulfilled. The circuit can detect a plurality of video AD modules, the device is simple, feasible and easy and convenient to control, and the selected chip has high temperature reliability and radiation resistance and can meet the requirement of a space remote sensing imaging system.

Description

The analog self-correcting figure of CCD imaging system implement device

Technical field

The present invention relates to the spacer remote sensing technical field of imaging, be specifically related to the analog self-correcting figure of CCD imaging system implement device, be used for the circuit state self check of remote sensing camera.

Background technology

Since CCD (Charge Coupled Device; Charge-coupled image sensor) since the appearance; The photoelectric sensor imaging technique develops rapidly; Especially TDI-CCD (Time Delay and Integration CCD, time delay integration charge-coupled image sensor) with the characteristics of its time delay integration and push-scanning image, is widely used in Aero-Space remotely sensed image field.For the imaging system of CCD remote sensing camera, except CCD also has a lot of other important component parts, like optical system, ccd signal processing module, communication module, data transmission module, image compression system etc.Because the CCD device is very expensive; Can not frequently plug CCD during system integration test; Need not add CCD during subsystem assembling test yet, therefore must in the ccd signal processing module, design the data source of a series of self-correcting figures, can when subsystem is assembled, whether correctly connect by test interface on the one hand as emulation CCD; Whether normal, whether pixel output has the serial phenomenon if can detect the CCD sequential on the other hand.

The principle of TDI-CCD push-scanning image that at present literature research arranged, and designed several kinds of digital self-correcting figures in view of the above, satisfied the detection and the debugging needs of camera data transmission.Yet; Digital self-correcting figure is by FPGA (Field Programmable Gate Array; Field programmable gate array) produces through DLC(digital logic circuit); Therefore functional link can only be detected, and crucial functional links such as video AD chip can't be detected from FPGA to the view data output interface.There is limitation in the digital figure that FPGA directly produces, and the duty that can't detect video AD makes it become a big shortcoming of self-correcting figure.Therefore, be necessary to design a kind of digital processing link that can either detect the CCD image-generating unit, can detect the device of crucial ASH link (like the video AD module) again.

Summary of the invention

The present invention can only detect the functional link from FPGA to the view data output interface for solving existing self-correcting figure implement device; And can't detect the problem of crucial functional links such as video AD chip, the analog self-correcting figure of a kind of CCD imaging system implement device is provided.

The analog self-correcting figure of CCD imaging system implement device, this device comprise FPGA, simulation self-correcting figure implement device, video AD module, handover module and ccd signal processing module,

Said simulation self-correcting figure implement device comprises first electric capacity and second electric capacity; Handover module comprises chip for driving and DAC chip; Said FPGA sends and drives enable signal controlling and driving chip generation simulating signal; FPGA sends the logical sequence that the logical sequence signal produces said simulating signal to chip for driving, and FPGA control DAC chip output variable voltage is to chip for driving, and said chip for driving is through the simulating signal of second electric capacity output variable amplitude; Ccd signal processing module output CCD vision signal parallelly connected video AD module that inputs to simulating signal behind first electric capacity; When the function of selecting simulation self-correcting figure is closed; The CCD vision signal gets into the video AD module and carries out analog to digital conversion, and video AD module output digital image is to FPGA; When the function of selecting simulation self-correcting figure was opened, simulating signal got into the video AD module, realizes the self-correcting of analog figure through FPGA.

Beneficial effect of the present invention: the present invention can make simulation self-correcting figure and CCD vision signal not disturb mutually, and the video AD module is sent in timesharing with it, reaches the purpose that detects whole CCD imaging system duty.Device of the present invention can either detect the digital processing link of CCD image-generating unit; Can detect crucial ASH link again; Circuit can detect a plurality of video AD modules; Simple control is easy, and selected chip has very high temperature reliability and radiation resistance, can adapt to the needs of spacer remote sensing imaging system.

Description of drawings

Fig. 1 is the structural representation of the analog figure implement device of CCD imaging system of the present invention;

Fig. 2 is the workflow diagram of the analog figure implement device of CCD imaging system of the present invention;

Fig. 3 is the structural representation of embodiment two in the analog figure implement device of CCD imaging system of the present invention;

Fig. 4 is the workflow diagram that installs in the embodiment two in the analog figure implement device of CCD imaging system of the present invention.

Embodiment

Embodiment one, combination Fig. 1 and Fig. 2 explain this embodiment; The analog figure implement device of CCD imaging system, this device comprise FPGA, simulation self-correcting figure implement device, video AD module, handover module and ccd signal processing module, and said simulation self-correcting figure implement device comprises first electric capacity and second electric capacity; Handover module comprises chip for driving and DAC chip; Said chip for driving links to each other with second electric capacity, and described FPGA links to each other with DAC chip, chip for driving, and the principle of chip for driving is output VH and VL under the Digital Logic control of input IN signal; Wherein VH is the high level of simulating signal, and VL is the low level of simulating signal.Associative list 1, table 1 are the truth table of chip for driving work;

Table 1

OE	IN	OUT
			0	0	Three-state
0	1	Three-state
			1	0	V _H
1	1	V _L

For the function that realizes that the simulating signal amplitude is variable, this embodiment VH is set to fixed value (like 3.3V), and VL is set to variable voltage, and this variable voltage is produced under the control of FPGA by the DAC chip.FPGA sends and drives enable signal controlling and driving chip generation simulation signal generator, and FPGA sends the logical sequence that the logical sequence signal produces simulating signal, and through control DAC chip generation variable voltage, realizes the simulating signal of output variable amplitude; Described ccd signal processing module links to each other with first electric capacity; And parallelly connected entering video AD module with analogue signal circuit; Described video AD module links to each other with FPGA; When CCD video circuit operate as normal, the imaging control system need in time be closed simulation self-correcting graphing capability, and it is set to export high-impedance state.The ccd signal processing module produces CCD vision signal entering video AD module and carries out analog-to-digital conversion process; This moment is for the CCD vision signal; Load not only comprises the video AD module, has also increased a heavy load of being made up of high resistant and electric capacity, can be known by circuit analysis; This very big load is to CCD vision signal and the almost not influence of video quantizing process thereof, and the digital picture of output gets into FPGA.In like manner, when simulation self-correcting graphing capability was opened, the imaging control system need in time be closed CCD video imaging circuit.In addition, the black level reference position of two kinds of simulating signals can be different, and the control system that therefore forms images also needs the black level sampling location of the corresponding video AD of conversion in time.Simulating signal gets into the video AD module, gets into FPGA at last.

In conjunction with Fig. 2 this embodiment is described, this embodiment is the simulation self-correcting control flow of FPGA:

Behind the FPGA electrifying startup; Default mode is a CCD shooting state; This moment, chip for driving was output as high resistant, and the DAC chip is in holding state, the driving logical signal operate as normal of CCD; The dark pixel benchmark of video AD module is in the dark pixel position of actual CCD output, and digital picture is output as CCD imaging picture.When model selection was digital self-correcting, above state was constant, only digital picture output was switched to digital self-correcting figure and got final product.When model selection was the simulation self-correcting, FPGA at first shielded the drive signal of CCD, makes CCD not work; FPGA can send and the logical signal (dutycycle 50%) of CCD pixel clock with frequency to chip for driving then, changes the position of the dark pixel benchmark of video AD module to simulation self-correcting definition simultaneously.This moment, FPGA can reach the purpose of the signal low voltage amplitudes of adjusting chip for driving output through the output voltage of control DAC chip, and then the unsteady function of regulating of amplitude that realizes regulating simulation self-correcting figure.On the present digital picture of regular variation final body of signal amplitude is exactly the striped of grey scale change.Observe this striped and whether just can judge according to predetermined rule variation whether the work of video AD module is normal.

Embodiment two, combination Fig. 3 and Fig. 4 explain this embodiment; This embodiment is with the difference of the analog figure implement device of embodiment one described CCD imaging system; First electric capacity in the self-correcting figure of simulation described in this embodiment implement device and second electric capacity is by digital potentiometer and the replacement of video algorithms amplifier, and chip for driving and DAC chip are by voltage management chip and relay generation in the said handover module Replace;Described FPGA links to each other with the voltage management chip with digital potentiometer; The simulation signal generator of replaced C CD video output results from the negative-feedback circuit of AD operational amplifier; FPGA produces the logical sequence of simulating signal; Satisfy the sequential relationship of correlated-double-sampling simultaneously, and export the simulating signal of variable amplitude through the resistance realization of adjustment digital potentiometer in good time; Described voltage management chip links to each other with relay; Described relay links to each other with the video AD module; Described video AD module links to each other with FPGA; Simulating signal and CCD vision signal are coupled into through the relay switching way carries out the analog to digital conversion quantification treatment in the video AD module, control relay circuit is made up of a controlled voltage management chip and a relay.The conventional state of relay is a conducting CCD vision signal, blocks simulation self-correcting figure signal.After circuit powered on, relay kept conventional state, and the voltage management chip does not produce voltage, and the ccd signal processing module produces CCD vision signal entering video AD module and carries out analog-to-digital conversion process, and the digital picture of output gets into FPGA; When needs are opened simulation self-correcting graphing capability; FPGA control voltage management chip produces voltage, makes relay switch switch to unconventional state, and analog passband signal is crossed relay entering video AD module and carried out the analog-to-digital conversion quantification treatment; Get into FPGA at last, realize the self-checking function of image-generating unit.Therefore, imaging system need not carried out the shielding of some signal or control the output high resistant simulation self-correcting or CCD imaging circuit, only needs to send the conversion that a relay control signal just can be realized two states.

In conjunction with Fig. 4 this embodiment is described, this embodiment is the simulation self-correcting control procedure of FPGA described in the embodiment two:

Behind the FPGA electrifying startup; Default mode is a CCD shooting state; This moment, relay was acquiescence normally off (being that the CCD vision signal gets into the video AD module); The driving logical signal operate as normal of CCD, the dark pixel benchmark of video AD module are in the dark pixel position of actual CCD output, and digital picture is output as CCD imaging picture.When model selection was digital self-correcting, above state was constant, only digital picture output was switched to digital self-correcting figure and got final product.When model selection was the simulation self-correcting, the FPGA at first voltage management chip output of pilot relay control circuit can supply the voltage of relay switching, and relay switch switches to simulation self-correcting signal; FPGA can send and the logical signal (dutycycle 50%) of CCD pixel clock with frequency to AD computing negative feedback amplifier circuit module then; Change the position of the dark pixel benchmark of video AD module to simulation self-correcting definition simultaneously, the resistance of regulating digital potentiometer this moment just can realize regulating the function of the signal amplitude of simulating the self-correcting figure.On the present digital picture of regular variation final body of signal amplitude is exactly the striped of grey scale change.Observe this striped and whether just can judge according to predetermined rule variation whether the work of video AD module is normal.

Practice result proves that under two kinds of embodiments, the simulating signal and the CCD vision signal of simulation self-correcting figure can be switched without interfering with each other, and all can operate as normal.

Claims

1.CCD the analog self-correcting figure of imaging system implement device; This device comprises FPGA, simulation self-correcting figure implement device, video AD module, handover module and ccd signal processing module; It is characterized in that said simulation self-correcting figure implement device comprises first electric capacity and second electric capacity, handover module comprises chip for driving and DAC chip; Said FPGA sends and drives enable signal controlling and driving chip generation simulating signal; FPGA sends the logical sequence that the logical sequence signal produces said simulating signal to chip for driving, and FPGA control DAC chip output variable voltage is to chip for driving, and said chip for driving is through the simulating signal of second electric capacity output variable amplitude; Ccd signal processing module output CCD vision signal parallelly connected video AD module that inputs to simulating signal behind first electric capacity; When the function of selecting simulation self-correcting figure is closed; The CCD vision signal gets into the video AD module and carries out analog to digital conversion, and video AD module output digital image is to FPGA; When the function of selecting simulation self-correcting figure was opened, simulating signal got into the video AD module, realizes the self-correcting of analog figure through FPGA.

2. the analog self-correcting figure of CCD imaging system according to claim 1 implement device; It is characterized in that; First electric capacity in the said simulation self-correcting figure implement device and second electric capacity are replaced by digital potentiometer and video algorithms amplifier, and chip for driving and DAC chip are replaced by voltage management chip and relay in the said handover module; Said FPGA sends the resistance that controlled variable is adjusted digital potentiometer to digital potentiometer; Said FPGA sends the logical sequence of simulating signal simultaneously to the video algorithms amplifier; The video algorithms amplifier according to the simulating signal of the resistance of digital potentiometer output variable amplitude to relay; Relay is a normally off, and said ccd signal processing module produces CCD vision signal entering video AD module and carries out analog to digital conversion, and output digital image is to FPGA; When selecting simulation self-correcting function to open; FPGA control voltage management chip produces voltage, and relay switches to simulation self-correcting function, and analog passband signal is crossed relay entering video AD module and carried out the analog-to-digital conversion quantification treatment after FPGA realizes the self-correcting of mimic diagram.