CN102655416A - Minimum transmission differential signal receiver system and built-in self testing method thereof - Google Patents
Minimum transmission differential signal receiver system and built-in self testing method thereof Download PDFInfo
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- CN102655416A CN102655416A CN2011100519607A CN201110051960A CN102655416A CN 102655416 A CN102655416 A CN 102655416A CN 2011100519607 A CN2011100519607 A CN 2011100519607A CN 201110051960 A CN201110051960 A CN 201110051960A CN 102655416 A CN102655416 A CN 102655416A
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Abstract
The invention discloses a minimum transmission differential signal receiver system and a built-in self testing method thereof. The system comprises a clock channel, multiple data channels, a minimum transmission differential signal decoding unit and a self testing unit, wherein the clock channel receives and outputs a clock signal, each data channel receives, processes and outputs a corresponding data signal according to the clock signal; the minimum transmission differential signal decoding unit receives the data signal after processing, and can decode the data signal after the processing; and the self testing unit receives the clock signal and an external parallel signal, generates a test signal according to the clock signal and the external parallel signal, and can perform built-in self testing on the data channels and the minimum transmission differential signal decoding unit. In addition, the built-in self testing method which is suitable for the minimum transmission differential signal receiver system is provided.
Description
Technical field
The present invention relates to a kind of receiver system and method for testing thereof; And be particularly related to a kind of transition minimized differential signaling (Transition Minimized Differential Signaling; TMDS) receiver system and built-in self-test thereof (Built-in-self-test, BIST) method.
Background technology
TMDS is the technology of a high speed data transfer, and (Digital VisualInterface, DVI) (High-Definition Multimedia Interface HDMI) waits the image coffret with high picture quantity multimedia interface to can be used for digital visual interface.Generally speaking, the TMDS receiver system has four passages, and wherein three is data channel; Receive the picture signal of yuv format or rgb format respectively; Another then is the clock passage, and in order to the receive clock signal, and the maximum transmission speed of each passage is 1.65Gbps.
In the TMDS receiver system, typical built-in self-test method normally replaces to fall original data channel, and the test circuit of building in the utilization produces signal, to reach the purpose of selftest.Said method need dispose extra test circuit in System on Chip/SoC, can increase the cost of chip in addition.Moreover general TMDS receiver system has three data passages usually, needs to use more test circuit, also can cause the cost of chip area cost.
Summary of the invention
The present invention provides a kind of TMDS receiver system, and the clock signal that it utilizes the clock passage to produce reaches the purpose of built-in self-test, can make circuit system on area, have more advantage.
The present invention provides a kind of built-in self-test, and (clock signal that it utilizes the clock passage to produce reaches the purpose of built-in self-test for Built-in-self-test, BIST) method.
The present invention provides a kind of TMDS receiver system, and it comprises a clock passage, a plurality of data channel, a TMDS decoding unit and a selftest unit.The clock passage receives, handles and export a clock signal.Each data channel receives, handles and export corresponding data-signal according to clock signal.The TMDS decoding unit receives the data-signal after handling, and the data-signal after handling is decoded.A selftest unit receive clock signal and an outside parallel signal, and produce a test signal in view of the above, so that data passage and TMDS decoding unit are carried out a built-in self-test.
In one embodiment of this invention, above-mentioned selftest unit comprises a frequency synthesizer (Frequency Synthesizer) and an ALU.Frequency synthesizer receive clock signal, and produce a frequency multiplication (multiple frequency) signal in view of the above, wherein the frequency of frequency-doubled signal is more than a times of frequency of clock signal.ALU receives frequency-doubled signal and outside parallel signal, and frequency-doubled signal and outside parallel signal are carried out a logical operation, to produce test signal.
In one embodiment of this invention; Above-mentioned ALU to frequency-doubled signal and outside parallel signal carries out or (OR) computing, with (AND) computing, XOR (XOR) computing and with or (XNOR; Also be referred to as XNOR) computing at least one of them, to produce test signal.
In one embodiment of this invention, above-mentioned outside parallel signal is disposed at the outside signal generator of TMDS receiver system by one and produces.
In one embodiment of this invention, each above-mentioned data channel comprises an equalizer (equalizer) and data recovery (data recovery) unit.The selftest unit carries out built-in self-test to the data recovery unit of data passage.
In one embodiment of this invention, above-mentioned clock passage comprise a phase-locked loop (phase-lockloop, PLL).Phase-locked loop reception, synchronous also clock signal are to selftest unit and data channel.
The present invention provides a kind of BIST method, is suitable for a TMDS receiver system.Said BIST method comprises: receive an outside parallel signal; A clock signal and outside parallel signal according to the TMDS receiver system produce a test signal; And utilize test signal, the TMDS receiver system is carried out built-in self-test.
In one embodiment of this invention, the step of above-mentioned generation test signal comprises: according to clock signal, produce a frequency-doubled signal, wherein the frequency of frequency-doubled signal is more than a times of frequency of clock signal; And frequency-doubled signal and outside parallel signal carried out a logical operation, to produce test signal.
In one embodiment of this invention, above-mentioned logical operation comprise exclusive disjunction, and computing, XOR and with exclusive disjunction at least one of them.
Based on above-mentioned; In exemplary embodiment of the present invention; The clock signal that the TMDS receiver system utilizes the clock passage to be provided is originated as the signal of built-in self-test; Collocation frequency synthesizer and outside parallel signal carry out built-in self-test, can make circuit system on area, have more advantage.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 illustrates the functional block diagram of the TMDS receiver system of one embodiment of the invention.
Fig. 2 illustrates the signal waveforms of clock signal, data-signal and the frequency-doubled signal of one embodiment of the invention.
Fig. 3 illustrates the signal waveforms of clock signal, data-signal, frequency-doubled signal, outside parallel signal and the test signal of one embodiment of the invention.
Fig. 4 is the flow chart of steps of the built-in self-test method of one embodiment of the invention.
[main element symbol description]
The 100:TMDS receiver system
110: the clock passage
112: the phase-locked loop
120a, 120b, 120c: data channel
122a: equalizer
124a: selector
126a: data recovery unit
The 130:TMDS decoding unit
140: the selftest unit
142: frequency synthesizer
144: ALU
200: signal generator
RX0, RX1, RX2: data-signal
RXC: clock signal
RCX_*, RCX_5p4x, RCX_3p2x, RCX_2p5x, RCX_5x: frequency-doubled signal
Sp: outside parallel signal
S
B: test signal
Embodiment
Fig. 1 illustrates the functional block diagram of the TMDS receiver system of one embodiment of the invention.Please refer to Fig. 1, the TMDS receiver system 100 of present embodiment comprises a clock passage 110, a plurality of data channel 120a, 120b, 120c, a TMDS decoding unit 130 and a selftest unit 140.
In the present embodiment, clock passage 110 comprises a phase-locked loop 112.Phase-locked loop 112 receives a clock signal RXC, and exports clock signal RXC to selftest unit 140 and data channel 120a, 120b, 120c after synchronously.
With data-signal RX0 is example, and before 130 couples of data-signal RX0 of TMDS decoding unit decoded, the data-signal RX0 that equalizer 122a can be received data passage 120a earlier carried out equilibrium treatment.Afterwards, data recovery unit 126a carries out data to data-signal RX0 again and recovers, repairs, so that data-signal RX0 to the TMDS decoding unit 130 after recoverys, the repairing to be provided.Then, after TMDS decoding unit 130 receives data-signal RX0, RX1, RX2, again these data-signals are decoded.
On the other hand, in the present embodiment, a clock signal RXC that 140 reception phase-locked loops 112, selftest unit provide and an outside parallel signal Sp, and produce a test signal S in view of the above
B, carry out built-in self-test with data recovery unit and TMDS decoding unit 130 to each data channel.
In detail, selftest unit 140 comprises a frequency synthesizer 142 and an ALU 144.Frequency synthesizer 142 receive clock signal RXC, and produce a frequency-doubled signal RCX_* in view of the above, wherein the frequency of frequency-doubled signal RCX_* is more than a times of frequency of clock signal RXC.Fig. 2 promptly illustrates the signal waveforms of clock signal, data-signal and the frequency-doubled signal of one embodiment of the invention.In the present embodiment; The frequency of frequency-doubled signal RCX_* for example is 1.25 times, 1.5 times, 2.5 times, 5 times of frequency of clock signal RXC etc.; In Fig. 2, represent with RCX_5p4x, RCX_3p2x, RCX_2p5x, RCX_5x respectively, but frequency-doubled signal RCX_* of the present invention is not limited to this.In other words, through the effect of frequency synthesizer 142, the TMDS receiver system 100 of present embodiment can obtain 1.25 times, 1.5 times, 2.5 times, 5 times the signal output of clock signal RXC.
Then, ALU 144 can carry out a logical operation to frequency-doubled signal RCX_* and outside parallel signal Sp after receiving frequency-doubled signal RCX_* and outside parallel signal Sp, to produce test signal S
BAt this; Outside parallel signal Sp is disposed at outside 200 generations of signal generator of TMDS receiver system 100 by one; But the present invention is not limited to this, and the source of outside parallel signal Sp can be outside buffer output, also can be the output of ALU 144.And the signal generator 200 of present embodiment for example is a vector generator (pattern generator), and by ten (10-bit) signals of external control, vector generator changes into the output of serial vector with various parallel vector data at random thus again.In addition; In the present embodiment; The logical operation that 144 couples of frequency-doubled signal RCX_* of ALU and outside parallel signal Sp are carried out for example be or (OR) computing, with (AND) computing, XOR (XOR) computing and with or (XNOR) computing at least one of them, to produce test signal S
B
Furthermore, Fig. 3 illustrates the signal waveforms of clock signal, data-signal, frequency-doubled signal, outside parallel signal and the test signal of one embodiment of the invention.With frequency-doubled signal RCX_5p4x is example, and frequency synthesizer 142 changes the frequency of clock signal RXC, and its raising frequency is obtained frequency-doubled signal RCX_5p4x.Then, 144 couples of frequency-doubled signal RCX_5p4x of ALU and outside parallel signal Sp carry out the XNOR computing, to produce test signal S
B, as shown in Figure 3.In other words, the TMDS receiver system 100 of present embodiment is originated its raising frequency through changing the frequency of clock signal with the signal as selftest.In other embodiments, the TMDS receiver system also can come the signal source as selftest with the operation interval of its frequency reducing or change clock signal.Be with, in the present embodiment, but the output combination in any of the output of signal generator 200 and frequency synthesizer 142 is done computing, and guarantees signal non-surge (glitch is referred to as the short-time pulse ripple again).
Fig. 4 is the flow chart of steps of the built-in self-test method of one embodiment of the invention.Please referring to figs. 1 through Fig. 4, the built-in self-test method of present embodiment for example is suitable for the TMDS receiver system 100 of Fig. 1, and it comprises the steps.
At first, in step S400, receive an outside parallel signal Sp through ALU 144.Then, in step S402, the clock signal RXC according to phase-locked loop 112 provides produces a frequency-doubled signal RXC_* through frequency synthesizer 142.Afterwards, in step S404, carry out a logical operation, to produce test signal S through 144 couples of frequency-doubled signal RXC_* of ALU and outside parallel signal Sp
BThen, in step S406, utilize test signal S
B, the TMDS receiver system is carried out built-in self-test.It should be noted that only in order to illustrate, the present invention is not limited to this to the order of step S400 and S402.
In addition, the built-in self-test method of present embodiment can be obtained enough teachings, suggestion and implement explanation in the narration by the exemplary embodiment of Fig. 1～Fig. 3, so repeats no more.
In sum; In exemplary embodiment of the present invention; The clock signal that the TMDS receiver system utilizes the clock passage to be provided is originated as the signal of built-in self-test; Collocation frequency synthesizer and outside parallel signal carry out built-in self-test, do not need can make circuit system on area, have more advantage according to data channel additional configuration test circuit.
Though the present invention with embodiment openly as above; Right its is not in order to limit the present invention; Those skilled in the art are not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (9)
1. transition minimized differential signaling receiver system comprises:
One clock passage receives, handles and export a clock signal;
A plurality of data channel according to this clock signal, receive, handle and export corresponding data-signal;
One transition minimized differential signaling decoding unit, the data-signal after receiving these and handling, and the data-signal after these are handled is decoded; And
One selftest unit receives this clock signal and an outside parallel signal, and produces a test signal in view of the above, so that these data channel and this transition minimized differential signaling decoding unit are carried out a built-in self-test.
2. transition minimized differential signaling receiver system as claimed in claim 1, wherein this selftest unit comprises:
One frequency synthesizer receives this clock signal, and produces a frequency-doubled signal in view of the above, and wherein the frequency of this frequency-doubled signal is more than a times of frequency of this clock signal; And
One ALU receives this frequency-doubled signal and should the outside parallel signal, and to this frequency-doubled signal and should carry out a logical operation by the outside parallel signal, to produce this test signal.
3. transition minimized differential signaling receiver system as claimed in claim 2; Wherein this ALU to this frequency-doubled signal and should the outside parallel signal carry out exclusive disjunction, with computing, XOR and with exclusive disjunction at least one of them, to produce this test signal.
4. transition minimized differential signaling receiver system as claimed in claim 1 wherein should the outside parallel signal be disposed at the outside signal generator of this transition minimized differential signaling receiver system by one and produces.
5. transition minimized differential signaling receiver system as claimed in claim 1, wherein respectively this data channel comprises an equalizer and a data recovery unit, this selftest unit carries out this built-in self-test to the data recovery unit of these data channel.
6. transition minimized differential signaling receiver system as claimed in claim 1, wherein this clock passage comprises a phase-locked loop, this phase-locked loop receives, synchronously and export this clock signal to this selftest unit and these data channel.
7. a built-in self-test method is suitable for a transition minimized differential signaling receiver system, and this built-in self-test method comprises:
Receive an outside parallel signal;
According to a clock signal of this transition minimized differential signaling receiver system and should the outside parallel signal, produce a test signal; And
Utilize this test signal, this transition minimized differential signaling receiver system is carried out built-in self-test.
8. built-in self-test method as claimed in claim 7, this step that wherein produces this test signal comprises:
According to this clock signal, produce a frequency-doubled signal, wherein the frequency of this frequency-doubled signal is more than a times of frequency of this clock signal; And
To this frequency-doubled signal and should carry out a logical operation by the outside parallel signal, to produce this test signal.
9. built-in self-test method as claimed in claim 8, wherein this logical operation comprise or the OR computing, with AND computing, XOR XOR computing and with or the XNOR computing at least one of them.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109032023A (en) * | 2018-08-08 | 2018-12-18 | 上海精密计量测试研究所 | A kind of built-in self-test method of FPGA internal DC M, PLL |
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| CN1592387A (en) * | 2003-05-01 | 2005-03-09 | 创世纪微芯片公司 | Use of auxiliary channel for training of video monitor |
| US7088398B1 (en) * | 2001-12-24 | 2006-08-08 | Silicon Image, Inc. | Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data |
| JP2008122399A (en) * | 2006-11-15 | 2008-05-29 | Silicon Image Inc | Interface testing circuit and method |
| US20100235135A1 (en) * | 2009-03-13 | 2010-09-16 | Conner George W | General Purpose Protocol Engine |
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| US7088398B1 (en) * | 2001-12-24 | 2006-08-08 | Silicon Image, Inc. | Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data |
| CN1592387A (en) * | 2003-05-01 | 2005-03-09 | 创世纪微芯片公司 | Use of auxiliary channel for training of video monitor |
| JP2008122399A (en) * | 2006-11-15 | 2008-05-29 | Silicon Image Inc | Interface testing circuit and method |
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Application publication date: 20120905 |