CN102646452A - Programmable memory and writing and reading method thereof - Google Patents
Programmable memory and writing and reading method thereof Download PDFInfo
- Publication number
- CN102646452A CN102646452A CN2011100420042A CN201110042004A CN102646452A CN 102646452 A CN102646452 A CN 102646452A CN 2011100420042 A CN2011100420042 A CN 2011100420042A CN 201110042004 A CN201110042004 A CN 201110042004A CN 102646452 A CN102646452 A CN 102646452A
- Authority
- CN
- China
- Prior art keywords
- unit
- bit length
- programmable memory
- programmable
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a programmable memory and a writing and reading method thereof. The programmable memory comprises a plurality of single-pass programmable memory units, a searching unit, a writing unit and a reading unit, wherein the programmable memory units correspond to a plurality of addresses; the searching unit is used for searching the nearest writable and programmable memory unit from the single-pass programmable memory units or searching the last group of programmed programmable memory units from the single-pass programmable memory units during reading action; the writing unit is used for writing bit length of input data and the input data from the nearest writable and programmable memory unit; and the reading unit is used for sequentially reading data from the last group of programmed programmable memory units. The programmable memory comprising the single-pass programmable memory units has the advantage of reasonably utilizing storage space.
Description
Technical field
The present invention relates to a kind of programmable storage and write and read method, relate in particular to and a kind ofly comprise the programmable storage of a plurality of single programmable memories unit and write and read method.
Background technology
In the manufacture process of integrated circuit; Because the variation of the technological parameter between the equipment board, make other integrated circuit manufacturing accomplish after between each unit of cargo (lot) and the goods, between each wafer (wafer) and the wafer, even each crystal grain (die) and intergranule on the same wafer; There is the technological parameter variation of degree varies; Cause integrated circuit component, for example: resistance, electric capacity, transistor etc., the variation of producing component parameter.Therefore, the circuit of forming by element, for example oscillator or voltage adjuster (Voltage Regulator) etc., its frequency or output voltage values can with design load error to some extent.If the parameter variation amount of these circuit is excessive, and surpass the error range that specifications are worked out, when test, will be judged as defective products.Therefore, integrated circuit manufacturer often need carry out the error of trim step with correction circuit, so as to promoting fine ratio of product (yield).Generally speaking, trim step is used disposable programmable (One-Time Programming is hereinafter to be referred as the OTP) element of fuse (fuse) or tinsel etc. mostly, reaches the function of fine setting.
The OTP method of adjustment that general integrated circuit often uses is repaired methods such as (poly fuse or title E-fuse) as laser preparing (laser trim) or fuse.Laser repairing method uses many group OTP elements, and metal wire sections for example is to carry out sequencing (programming) step.In the process of sequencing, high-octane laser can use to burn the different metallic line segment.On the other hand, the fuse method for repairing and mending uses many group OTP elements, and for example polysilicon line segment or metal wire sections are to carry out the sequencing step.In the process of sequencing, big curtage can use to burn different polysilicon line segment or metal wire sections.The said procedure process is an irreversible destructive action, and just these OTP elements can't be used after sequencing once more.
In order to reach the purpose of multiple programmable; Multiple programmable (Multiple-Time Programming; Hereinafter to be referred as MTP) element; For example: Erasable Programmable Read Only Memory EPROM (EPROM), electronics Erasable Programmable Read Only Memory EPROM (EEPROM), flash memory MTP elements such as (FLASH MEMORY) can be used to realize the purpose of multiple programmable.Yet the MTP element needs extra circuit and complicated processing step just can obtain, and its technology cost is higher, and high with the relevance of semiconductor technology, so be difficult for disperseing the production capacity risk.
Therefore,, then can reduce manufacturing step and cost, and possess the elasticity of repeatedly setting if the OTP element can adopt to reach the function of multiple programmable.U.S.'s bulletin patent discloses a kind of programmable storage framework No. 6728137 in known technology.With reference to Fig. 1, this programmable storage 10 is to utilize the otp memory blocks of organizing 15 to reach the function of multiple programmable more.This programmable storage 10 through control circuit 11 to write and reading of data via column decoder 12 and row decoder 13.In when action, this programmable storage 10 must extra using recording element 14 writes down which or which single programmable memory block 15 by sequencing.
For the foregoing reasons, industry presses for a kind of programmable storage that comprises a plurality of single programmable memories unit, to address the above problem.
Summary of the invention
In order to solve the problems referred to above that prior art exists, the present invention discloses a kind of programmable storage and writes and read method.
According to one embodiment of the invention, this programmable storage comprises a plurality of single programmable memories unit, a search unit, a writing unit and a reading unit.Corresponding a plurality of addresses, said a plurality of single programmable memories unit.This search unit in order in a write activity in said a plurality of single programmable memories unit; Search the immediate programmable memory cell that writes; Or read in the action in said a plurality of single programmable memories unit one, search last and organize programmed memory unit.This writing unit is used for from this immediate programmable memory cell that writes, and writes bit (bit) length and this input data of input data with being right after.The memory cell that this reading unit is used for organizing from this last sequencing is reading of data in regular turn.
Of the present invention another implemented the wiring method that example discloses a kind of programmable storage, and wherein this programmable storage comprises a plurality of single programmable memories unit, corresponding a plurality of addresses.This wiring method comprises the following step: from the immediate programmable memory cell that writes of an initial address searching; And this immediate programmable memory cell that writes carries out following data write step with being right after certainly: the bit length that writes input data; And write this input data.
Another enforcement example of the present invention discloses a kind of read method of programmable storage, and wherein this programmable storage comprises a plurality of single programmable memories unit, corresponding a plurality of addresses.This programmable storage writes data according to the wiring method that above-mentioned enforcement example is disclosed.This read method comprises the following step: last organizes programmed memory unit from an initial address searching; And organize reading of data in the memory cell of sequencing in regular turn from this last.
The programmable storage that comprises a plurality of single programmable memories unit provided by the invention has the advantage of rational Application storage space.
Description of drawings
Fig. 1 is for showing the block diagram of a known programmable storage;
Fig. 2 is the block diagram of the programmable storage of one embodiment of the invention;
Fig. 3 is the process flow diagram of wiring method of the programmable storage of one embodiment of the invention;
Fig. 4 is the block diagram of this search unit of demonstration one embodiment of the invention;
Fig. 5 shows the writing mode of the programmable storage of one embodiment of the invention;
Fig. 6 is the process flow diagram of read method of the programmable storage of one embodiment of the invention; And
Fig. 7 shows the mode that reads of the programmable storage of one embodiment of the invention.
Description of reference numerals in the above-mentioned accompanying drawing is following:
10 programmable storages
11 control circuits
12 column decoders
13 row decoders
14 recording elements
15 otp memory blocks
20 programmable storages
21 inspection units
22 memory arrays
24 search unit
Cell is given in 242 addresses
244 inspection units
246 displacement units
26 writing units
28 reading units
100,200,300 otp memory unit
110,220,330 Mark Columns
S20～S22 step
S50～S52 step
Embodiment
The present invention is a kind of programmable storage and writes and read method in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step and structure will be proposed in following description.Apparently, the execution of the present invention specific details that is not defined in those skilled in the relevant art and had the knack of.On the other hand, well-known structure or step are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these detailed descriptions, the present invention can also be implemented among other the embodiment widely, and scope of the present invention constrained not, and it is as the criterion with appended claim.
For explaining the method with read method that writes of programmable storage of the present invention more glibly, below the programmable storage framework of carrying out method of the present invention will be described earlier.The block diagram of the programmable storage 20 of Fig. 2 one embodiment of the invention, it comprises a plurality of single programmables (OTP) memory cell 22, a search unit 24, a writing unit 26 and a reading unit 28.These otp memory unit 100,200 and 300 are positioned at a memory array 22.24 designs of this search unit are in order to searching the immediate programmable memory cell that writes in this memory array 22 in a write activity, or read one and in this memory array 22, to search last in the action and organize programmed memory unit.This writing unit 26 is designed for from this immediate programmable memory cell that writes, and writes bit length and this input data of input data with being right after.This reading unit 28 is designed in the memory cell of organizing sequencing from this last reading of data in regular turn.
With reference to Fig. 2, in an embodiment of the present invention, this programmable storage 20 comprises an inspection unit 21 in addition, in order to check the residue bit length of this programmable storage 20.21 designs of this inspection unit are in order to reading the residue bit length of this programmable storage 20, and relatively this residue bit length and one waits to import the bit length of data Data_in.When this residue bit length was imported the bit length of data Data_in greater than this, these 20 beginnings of programmable storage were carried out the data write step.
Fig. 3 is the process flow diagram of wiring method of the programmable storage of one embodiment of the invention.This programmable storage comprises a plurality of single programmable memories unit, its corresponding a plurality of addresses.This wiring method comprises the following step: from the immediate programmable memory cell (step S20) that writes of an initial address searching, and this immediate programmable memory cell that writes carries out following data write step with being right after certainly: write the bit length of input data and write this input data (step S22).Below will further specify the wiring method of programmable storage of the present invention.
With reference to Fig. 2, when this programmable storage 20 carried out a write activity, the immediate programmable memory cell that writes was at first searched in this search unit 24 in this memory array 22, to prepare to write data.Because the otp memory unit in this memory array 22 is the disposable programmable element, so after the sequencing of a certain otp memory unit, data can't be written into this memory cell once more.Therefore, this programmable storage 20 needs this search unit 24 to select not by the otp memory unit of sequencing.Fig. 4 shows the block diagram of this search unit 24 of one embodiment of the invention.This search unit 24 comprises an address and gives cell 242, an inspection unit 244 and a displacement unit 246.This address gives cell 242 in order to provide an initial address or a scheduler to this memory array 22.This inspection unit 244 is in order to check the written data bit length of this start address or the pairing single programmable memory of this scheduler unit.This displacement unit 246 provides this scheduler to this address to cell 242 in order to the check result according to this inspection unit 244.
The existing method of operation that this programmable storage 20 of the present invention is described with an embodiment.Please be simultaneously with reference to Fig. 4 and Fig. 5, when this programmable storage 20 was carried out a write activity, this address at first provided an initial address for cell 242, and for example address " 0x0000 " is to this memory array 22.Then, this pairing otp memory unit, inspection unit 244 inspection address " 0x0000 " (present embodiment is a memory cell 100) sequencing whether.In an embodiment of the present invention, this inspection unit 244 through the stored data of a Mark Column 110 of checking this otp memory unit 100 to judge the whether sequencing of this memory cell 100.If this Mark Column 110 stores bit " 0 ", represent this otp memory unit 100 not write data as yet, pairing otp memory unit, location, old place " 0x0000 " 100 is the immediate programmable memory cell that writes.With reference to Fig. 5, this Mark Column 110 stores bit " X " in the present embodiment, represents this otp memory unit 100 sequencing, and has write the data of X bit length.Therefore, this displacement unit 246 can be with bit " 0x0000 " and the bit length that has write (being the X bit length here) totalling, to obtain a scheduler (address " 0x0000+X ").
Then, this address provides this scheduler (address " 0x0000+X ") to this memory array 22 for cell 242.This inspection unit 244 is according to the written data bit length of the corresponding otp memory unit (present embodiment is a memory cell 200) of this scheduler inspection.As shown in Figure 5, this otp memory unit 200 has write the data of Y bit length.So this displacement unit 246 is once more with address " 0x0000+X " and the Y bit length totalling that writes, to obtain next scheduler (address " 0x0000+X+Y ").
Then, this address provides this next scheduler (address " 0x0000+X+Y ") to this memory array 22 for cell 242.This inspection unit 244 is according to the written data bit length of the corresponding otp memory unit (present embodiment is a memory cell 300) of this scheduler inspection.As shown in Figure 5; Mark Column 330 in this otp memory unit 300 stores bit " 0 "; Represent this otp memory unit 300 not write data as yet, pairing otp memory unit, location, old place " 0x0000+X+Y " 300 is the immediate programmable memory cell that writes.
Compared to known framework, whether disclosed programmable storage 20 utilizes the Mark Column of otp memory unit to judge the sequencing of this memory cell.Therefore, disclosed programmable storage 20 does not need extra recording element to write down the otp memory unit of sequencing.In addition, this programmable storage 20 can be according to the bit length config memory space of data when writing data again at every turn, and the data bit element length that writes of record is in Mark Column again.Therefore, as long as, can learn that this writes the up-to-date address of memory of data unit through checking the stored data of Mark Column of otp memory unit.In other words, use disclosed programmable storage 20 can make full use of the storage area of memory cell.
On the other hand, after input data Data_in writes to these otp memory unit in this memory array 22, a read step will be performed to read the data that these write.Fig. 6 is the process flow diagram of read method of the programmable storage of one embodiment of the invention.According to after abovementioned steps writes data, this read method comprises the following step: last organizes programmed memory unit (step S50) from an initial address searching, and organizes reading of data (step S52) in the memory cell of sequencing in regular turn from this last.The existing read method that this programmable storage 10 of the present invention is described with an embodiment.
Please be simultaneously with reference to Fig. 4 and Fig. 7, when this programmable storage 20 carried out reading action, this search unit 24 can be searched last and organize programmed memory unit in this memory array 22, to prepare reading of data.When operation, at first this address provides an initial address for cell 242, and for example address " 0x0000 " is to this memory array 22.Then, the written data bit length of this pairing otp memory unit, inspection unit 244 inspection address " 0x0000 " (present embodiment is a memory cell 100).In the present embodiment, the stored data of the Mark Column 110 of this inspection unit 244 these memory cells 100 of inspection.If this Mark Column 110 stores bit " 0 ", represent each memory cell in this memory array 22 all not write data, read action so will stop this.
In the present embodiment, this Mark Column 110 stores bit " Z ", represents this otp memory unit 100 sequencing, and has write the data of Z bit length.So this displacement unit 246 can be with bit " 0x0000 " and the bit length that has write (being the Z bit length here) totalling, to obtain a scheduler (address " 0x0000+Z ").Then, this address provides this scheduler (address " 0x0000+Z ") to this memory array 22 for cell 242.The written data bit length of these pairing memory cells in inspection unit 244 inspection addresses " 0x0000+Z " (present embodiment is a memory cell 200).If when the written data bit length of this memory cell equalled zero, then the last address of this address " 0x0000+Z " also was address " 0x0000 ", pairing otp memory unit 100 be this last organize the memory cell of sequencing.
In addition, if the written data bit length of the pairing memory cell in address " 0x0000+Z " is greater than zero the time, then this displacement unit 246 is once more with address " 0x0000+Z " and the bit length totalling that writes, to obtain another scheduler.Then repetition above-mentioned steps is to select last to organize the memory cell of sequencing from these otp memory unit according to the last address of another scheduler.This reading unit 28 will be organized from this last to read in regular turn in memory cell of sequencing and write data.
The element that each unit can be realized through the mode of devices at full hardware according to an embodiment of the invention, the mode of full software realizes or comprise hardware and software is realized.In addition, this unit also can be realized through computer program product.This computer program product can by computer can with or the computer-readable media access of getting, its provide procedure code with through or be connected to a computer or the operation of any instruction execution system.This computer can with or the computer-readable media access of getting can be any device, its can contain, store, communicate by letter, propagate or convey program with through or be connected to a computer or the operation of any instruction execution system.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still maybe be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to embodiment and disclose, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appended claim.
Claims (17)
1. the wiring method of a programmable storage, this programmable storage comprises a plurality of single programmable memories unit, corresponding a plurality of addresses, said a plurality of single programmable memories unit, this wiring method comprises the following step:
From the immediate programmable memory cell that writes of an initial address searching; And
Carry out following data write step from this immediate programmable memory cell that writes with being right after:
Write the bit length of input data; And
Write this input data.
2. wiring method as claimed in claim 1 before carrying out the data write step, also comprises the following step:
Read the residue bit length of this programmable storage;
Relatively should remain the bit length of bit length and these input data; And
When this residue bit length is imported the bit length of data greater than this, carry out the data write step.
3. wiring method as claimed in claim 1 wherein from the immediate step that writes programmable memory cell of an initial address searching, comprises the following step:
From this start address, the written data bit length of the single programmable memory unit that inspection is corresponding; And
According to check result, select this immediate programmable memory cell that writes, to write this input data with being right after.
4. wiring method as claimed in claim 3 wherein from the step of the written data bit length of the corresponding single programmable memory unit of this start address inspection, comprises the following step:
(a1) read the written data bit length of the pairing single programmable memory of this start address unit, wherein this written data bit length is greater than zero;
(a2) this start address and this have been write the bit length totalling, to obtain one time one address;
(a3) will this time address as the start address upgraded, repeat above-mentioned steps, the written data bit length up to the pairing single programmable memory of the start address of this renewal unit equals zero; And
The pairing single programmable memory of given step (a3) unit is the immediate programmable memory cell that writes.
5. wiring method as claimed in claim 3 wherein from the step of the written data bit length of the corresponding single programmable memory unit of this start address inspection, comprises the following step:
Read the written data bit length of the pairing single programmable memory of this start address unit, wherein this data bit element length equals zero; And
Specifying pairing this single programmable memory unit of this start address is this immediate programmable memory cell that writes.
6. wiring method as claimed in claim 1, wherein each single programmable memory unit has the data bit element storage area of a bit length.
7. the read method of a programmable storage; This programmable storage comprises a plurality of single programmable memories unit; Corresponding a plurality of addresses, this programmable storage writes data according to wiring method as claimed in claim 1, and this read method comprises the following step:
Last organizes programmed memory unit from an initial address searching; And
Organize reading of data in the memory cell of sequencing in regular turn from this last.
8. read method as claimed in claim 7, wherein last organizes the step of programmed memory unit from an initial address searching, comprises the following step:
From this start address, the written data bit length of the single programmable memory unit that inspection is corresponding; And
According to check result, select this last organize the memory cell of sequencing, with reading of data in regular turn.
9. read method as claimed in claim 8 wherein from the step of the written data bit length of the corresponding single programmable memory unit of this start address inspection, comprises the following step:
Read the written data bit length of the pairing single programmable memory of this start address unit, wherein this written data bit length is greater than zero;
With this start address and this written data bit length totalling, to obtain one time one address;
With the start address of this time address as a renewal, repeat above-mentioned steps, the written data bit length up to the pairing single programmable memory of the start address of this renewal unit equals zero; And
If the written data bit length of pairing this single programmable memory unit of start address of this renewal is zero, return a last address of the start address of this renewal; And
Specify pairing this single programmable memory unit, this last address to organize the memory cell of sequencing for this last.
10. read method as claimed in claim 8, wherein each single programmable memory unit has the data bit element storage area of a bit length.
11. a programmable storage comprises:
A plurality of single programmable memories unit, corresponding a plurality of addresses;
One search unit; In order in a write activity in said a plurality of single programmable memories unit; Search the immediate programmable memory cell that writes, or read in the action in said a plurality of single programmable memories unit, search last and organize programmed memory unit one;
One writing unit is used for from this immediate programmable memory cell that writes, and writes bit length and this input data of input data with being right after; And
One reading unit, the memory cell that is used for organizing from this last sequencing is reading of data in regular turn.
12. programmable storage as claimed in claim 11, wherein each single programmable memory unit has the data bit element storage area of a bit length.
13. programmable storage as claimed in claim 11, wherein this programmable memory cell also comprises an inspection unit, in order to check the residue bit length of this programmable storage.
14. programmable storage as claimed in claim 11, wherein this search unit also comprises:
Cell is given in one address, in order to an initial address or a scheduler to said a plurality of single programmable memories unit to be provided;
One inspection unit is in order to check the written data bit length of this start address or the pairing single programmable memory of this scheduler unit;
One displacement unit provides this scheduler to this address to cell in order to the check result according to this inspection unit.
15. programmable storage as claimed in claim 14; Wherein when this programmable storage is carried out this write activity; When the written data bit length of this start address or the pairing single programmable memory of this scheduler unit equalled zero, then pairing this single programmable memory unit of this start address or this scheduler was this immediate programmable memory cell that writes.
16. programmable storage as claimed in claim 14; Wherein when this programmable storage is carried out this write activity; When the written data bit length of the pairing single programmable memory of this start address unit greater than zero the time; Then this displacement unit is with this start address and this bit length totalling, to obtain this scheduler.
17. programmable storage as claimed in claim 14; When wherein this reads action when this programmable storage execution; When the written data bit length of this start address or the pairing single programmable memory of this scheduler unit equals zero; An address to this address was to cell before this displacement unit will provide this start address or this scheduler, and pairing single programmable memory unit, this last address be this last organize the memory cell of sequencing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110042004.2A CN102646452B (en) | 2011-02-22 | 2011-02-22 | Programmable storage and write thereof and read method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110042004.2A CN102646452B (en) | 2011-02-22 | 2011-02-22 | Programmable storage and write thereof and read method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102646452A true CN102646452A (en) | 2012-08-22 |
| CN102646452B CN102646452B (en) | 2016-01-20 |
Family
ID=46659229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110042004.2A Active CN102646452B (en) | 2011-02-22 | 2011-02-22 | Programmable storage and write thereof and read method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102646452B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1298154A (en) * | 1999-11-29 | 2001-06-06 | 三菱电机株式会社 | Memory reference system for stored data in selective reference to storage |
| JP2003015942A (en) * | 2001-07-03 | 2003-01-17 | Casio Comput Co Ltd | Method of writing data into memory, data write processing program and data write device |
| US20100177547A1 (en) * | 2009-01-15 | 2010-07-15 | Biao Shen | Memory device and memory access method |
| CN101923513A (en) * | 2010-08-11 | 2010-12-22 | 深圳市同洲电子股份有限公司 | Data writing and reading method of memory, system and FLASH memory |
-
2011
- 2011-02-22 CN CN201110042004.2A patent/CN102646452B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1298154A (en) * | 1999-11-29 | 2001-06-06 | 三菱电机株式会社 | Memory reference system for stored data in selective reference to storage |
| JP2003015942A (en) * | 2001-07-03 | 2003-01-17 | Casio Comput Co Ltd | Method of writing data into memory, data write processing program and data write device |
| US20100177547A1 (en) * | 2009-01-15 | 2010-07-15 | Biao Shen | Memory device and memory access method |
| CN101923513A (en) * | 2010-08-11 | 2010-12-22 | 深圳市同洲电子股份有限公司 | Data writing and reading method of memory, system and FLASH memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102646452B (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107408087B (en) | Apparatus and method for simultaneously accessing multiple memory planes of a memory during memory access operations | |
| KR100992583B1 (en) | Zone boundary adjustment for defects in non-volatile memories | |
| CN101957726B (en) | Phase transition storage in dual inline memory module | |
| KR101477768B1 (en) | Memory device and redundancy method | |
| US9691452B2 (en) | Apparatuses and methods for concurrently accessing different memory planes of a memory | |
| US9411696B2 (en) | Semiconductor memory device and method of operating the same | |
| CN102403039A (en) | Semiconductor memory device and method of operating same | |
| US8644076B2 (en) | Programmable memory device and memory access method | |
| US20090248955A1 (en) | Redundancy for code in rom | |
| US20170011809A1 (en) | Semiconductor memory device, method for repairing bad column and setting method for setting redundant information thereof | |
| JP2007294039A (en) | Nonvolatile semiconductor storage device | |
| CN103578563A (en) | Fail address detector, semiconductor memory device and method of detecting fail address | |
| CN106373610A (en) | Semiconductor memory device and operating method thereof | |
| US8458537B2 (en) | Nonvolatile semiconductor memory device | |
| JP2008108326A (en) | Storage device and its self-test method | |
| US9230692B2 (en) | Apparatuses and methods for mapping memory addresses to redundant memory | |
| CN108231121B (en) | Semiconductor memory device and operation setting method thereof | |
| US20120269018A1 (en) | Memory system having memory and memory controller and operation method thereof | |
| CN101563675B (en) | A new implementation of column redundancy for a flash memory with a high write parallelism | |
| US7512507B2 (en) | Die based trimming | |
| US20140281678A1 (en) | Memory controller and memory system | |
| CN102646452A (en) | Programmable memory and writing and reading method thereof | |
| JP4299984B2 (en) | Semiconductor memory device | |
| US9196378B2 (en) | Semiconductor memory device and operating method thereof | |
| CN110851072B (en) | Solid state storage device using state prediction method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |