CN102646452B - Programmable storage and write thereof and read method - Google Patents
Programmable storage and write thereof and read method Download PDFInfo
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- CN102646452B CN102646452B CN201110042004.2A CN201110042004A CN102646452B CN 102646452 B CN102646452 B CN 102646452B CN 201110042004 A CN201110042004 A CN 201110042004A CN 102646452 B CN102646452 B CN 102646452B
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Abstract
The invention provides a kind of programmable storage and write thereof and read method, this programmable storage comprises multiple single programmable memory unit, and searches unit, a writing unit and a reading unit.The corresponding multiple address of described multiple single programmable memory unit.This search unit in order in a write activity in described multiple single programmable memory unit, search and immediately write programmable memory cell, or in a read action in described multiple single programmable memory unit, search last and organize programmed memory unit.This writing unit is used for immediately writing programmable memory cell from this, immediately follows writes bit length and this input data of input data.This reading unit is used for organizing from this last in memory cell of sequencing and sequentially reads data.The programmable storage comprising multiple single programmable memory unit provided by the invention has the advantage of reasonable application memory space.
Description
Technical field
The present invention relates to a kind of programmable storage and write thereof and read method, particularly relate to a kind of comprise multiple single programmable memory unit programmable storage and write and read method.
Background technology
In the manufacture process of integrated circuit, due to the technological parameter variation between equipment board, after making other IC manufacturing complete between every parcel (lot) and goods, between each wafer (wafer) and wafer, each crystal grain (die) in even same wafer and between crystal grain, there is the technological parameter variation of degree varies, cause integrated circuit component, such as: resistance, electric capacity, transistor etc., the change of producing component parameter.Therefore, the circuit be made up of element, such as oscillator or voltage adjuster (VoltageRegulator) etc., its frequency or output voltage values can with design load error to some extent.If the parameter variation amount of these circuit is excessive, and exceeding the error range of specifications formulation, will defective products be judged as when testing.Therefore, integrated circuit fabrication plant business often needs to carry out trim step with the error of correction circuit, so as to promoting fine ratio of product (yield).Generally speaking, trim step uses disposable programmable (One-TimeProgramming, hereinafter referred to as the OTP) element of fuse (fuse) or tinsel etc. mostly, reaches the function of fine setting.
The OTP method of adjustment that general integrated circuit often uses repairs methods such as (polyfuse or title E-fuse) for laser preparing (lasertrim) or fuse.Laser repairing method uses many group OTP elements, and such as metal wire sections, to carry out sequencing (programming) step.In the process of sequencing, high-octane laser can use to burn different metal wire sections.On the other hand, fuse method for repairing and mending uses many group OTP elements, and such as polysilicon line segment or metal wire sections, to carry out programmed steps.In the process of sequencing, big current or voltage can use to burn different polysilicon line segments or metal wire sections.Said procedure process is an irreversible destructive action, and namely these OTP elements after programming, cannot again be used.
In order to reach the object of multiple programmable, multiple programmable (Multiple-TimeProgramming, hereinafter referred to as MTP) element, such as: the MTP elements such as Erasable Programmable Read Only Memory EPROM (EPROM), Electrical Erasable programmable read only memory (EEPROM), flash memory (FLASHMEMORY), can be used to realize the object of multiple programmable.But MTP element needs extra circuit and complicated processing step just can obtain, and its process costs is higher, and high with the relevance of semiconductor technology, therefore not easily disperses production capacity risk.
Therefore, if OTP element can adopt the function reaching multiple programmable, then can reduce manufacturing step and cost, and possess the elasticity repeatedly set.In known technology, No. 6728137th, U.S.'s issued patents discloses a kind of programmable storage framework.With reference to Fig. 1, this programmable storage 10 utilizes the otp memory block 15 of many groups to reach the function of multiple programmable.This programmable storage 10 by control circuit 11 to write via column decoder 12 and row decoder 13 and to read data.When action, this programmable storage 10 must additionally utilize recording element 14 to be programmed to record which or which single programmable memory block 15.
Programmable storage 10 in known framework is when re-writing data at every turn, and no matter the bit length of data is much, all can write in one group of new single programmable memory element.Therefore, even if the data of write only have a bit (1-bit) length, known manner all can use one group of complete single programmable memory element with storage data.In other words, known framework, when writing input data, can waste unnecessary storage space.
For the foregoing reasons, industry in the urgent need to a kind of programmable storage comprising multiple single programmable memory unit, to solve the problem.
Summary of the invention
In order to solve the problems referred to above that prior art exists, the present invention discloses a kind of programmable storage and write thereof and read method.
According to one embodiment of the invention, this programmable storage comprises multiple single programmable memory unit, and searches unit, a writing unit and a reading unit.The corresponding multiple address of described multiple single programmable memory unit.This search unit in order in a write activity in described multiple single programmable memory unit, search and immediately write programmable memory cell, or in a read action in described multiple single programmable memory unit, search last and organize programmed memory unit.This writing unit is used for immediately writing programmable memory cell from this, immediately follows writes bit (bit) length and this input data of input data.This reading unit is used for organizing from this last in memory cell of sequencing and sequentially reads data.
Of the present invention another implements the wiring method that example discloses a kind of programmable storage, and wherein this programmable storage comprises multiple single programmable memory unit, corresponding multiple address.This wiring method comprises the following step: write programmable memory cell from an initial address searching is immediate; And immediately follows carry out following data write step from this immediate programmable memory cell that writes: the bit length of write one input data; And write this input data.
Another enforcement example of the present invention discloses a kind of read method of programmable storage, and wherein this programmable storage comprises multiple single programmable memory unit, corresponding multiple address.The wiring method write data that this programmable storage discloses according to above-mentioned enforcement example.This read method comprises the following step: from an initial address searching, last organizes programmed memory unit; And read data in the memory cell sequentially organizing sequencing from this last.
The programmable storage comprising multiple single programmable memory unit provided by the invention has the advantage of reasonable application memory space.
Accompanying drawing explanation
Fig. 1 is the block diagram of the known programmable storage of display one;
Fig. 2 is the block diagram of the programmable storage of one embodiment of the invention;
Fig. 3 is the process flow diagram of the wiring method of the programmable storage of one embodiment of the invention;
Fig. 4 is the block diagram of this search unit of display one embodiment of the invention;
Fig. 5 shows the writing mode of the programmable storage of one embodiment of the invention;
Fig. 6 is the process flow diagram of the read method of the programmable storage of one embodiment of the invention; And
Fig. 7 shows the reading manner of the programmable storage of one embodiment of the invention.
Description of reference numerals in above-mentioned accompanying drawing is as follows:
10 programmable storages
11 control circuits
12 column decoders
13 row decoders
14 recording elements
15OTP memory block
20 programmable storages
21 inspection units
22 memory arrays
24 search unit
242 addresses are to cell
244 inspection units
246 displacement units
26 writing units
28 reading units
100,200,300OTP memory cell
110,220,330 Mark Columns
S20 ~ S22 step
S50 ~ S52 step
Embodiment
The present invention is a kind of programmable storage and write thereof and read method in the direction that this inquires into.In order to the present invention can be understood up hill and dale, by following description, detailed step and structure are proposed.Apparently, execution of the present invention is not defined in the specific details that those skilled in the relevant art have the knack of.On the other hand, well-known structure or step are not described in details, to avoid the restriction causing the present invention unnecessary.Preferred embodiment of the present invention can be described in detail as follows, but except these are described in detail, the present invention can also implement in other examples widely, and scope of the present invention not circumscribed, it is as the criterion with appended claim.
For the method for the write and read method of explaining programmable storage of the present invention more glibly, will the programmable storage framework performing method of the present invention first be described below.The block diagram of the programmable storage 20 of Fig. 2 one embodiment of the invention, it comprises multiple single programmable (OTP) memory cell 22, and searches unit 24, writing unit 26 and a reading unit 28.These otp memory unit 100,200 and 300 are positioned at a memory array 22.This search unit 24 designs and immediately writes programmable memory cell in order to search in this memory array 22 in a write activity, or in a read action, searches last in this memory array 22 organize programmed memory unit.This writing unit 26 is designed for and immediately writes programmable memory cell from this, immediately follows writes bit length and this input data of input data.This reading unit 28 is designed in the memory cell organizing sequencing from this last and sequentially reads data.
With reference to Fig. 2, in an embodiment of the present invention, this programmable storage 20 separately comprises an inspection unit 21, in order to check the residue bit length of this programmable storage 20.This inspection unit 21 designs the residue bit length reading this programmable storage 20, and compares the bit length of this residue bit length and a data Data_in to be entered.When this residue bit length is greater than the bit length of this input data Data_in, this programmable storage 20 begins to carry out data write step.
Fig. 3 is the process flow diagram of the wiring method of the programmable storage of one embodiment of the invention.This programmable storage comprises multiple single programmable memory unit, its corresponding multiple address.This wiring method comprises the following step: write programmable memory cell (step S20) from an initial address searching is immediate, and immediately follows carry out following data write step from this immediate programmable memory cell that writes: the bit length of write one input data and these input data (step S22) of write.The wiring method of programmable storage of the present invention will be further illustrated below.
With reference to Fig. 2, when this programmable storage 20 carries out a write activity, first this search unit 24 is searched and is immediately write programmable memory cell, to prepare to write data in this memory array 22.Because the otp memory unit in this memory array 22 is disposable programmable element, therefore when after the sequencing of a certain otp memory unit, data cannot be written into this memory cell again.Therefore, this programmable storage 20 needs this search unit 24 to select the otp memory unit be not programmed.Fig. 4 shows the block diagram of this search unit 24 of one embodiment of the invention.This search unit 24 comprises an address to cell 242, inspection unit 244 and a displacement unit 246.This address to cell 242 in order to provide a start address or a scheduler to this memory array 22.This inspection unit 244 is in order to check the written data bit length of the single programmable memory unit corresponding to this start address or this scheduler.This displacement unit 246 is in order to provide this scheduler to this address to cell 242 according to the check result of this inspection unit 244.
The method of operation of this programmable storage 20 of the present invention is now described with an embodiment.Referring to Fig. 4 and Fig. 5, when this programmable storage 20 performs a write activity, first this address provides a start address to cell 242, such as address " 0x0000 ", to this memory array 22.Then, whether this inspection unit 244 checks otp memory unit (the present embodiment the is memory cell 100) sequencing corresponding to address " 0x0000 ".In an embodiment of the present invention, this inspection unit 244 is by checking that whether the data stored by a Mark Column 110 of this otp memory unit 100 judge this memory cell 100 sequencing.If this Mark Column 110 stores bit " 0 ", represent this otp memory unit 100 and not yet write data, the otp memory unit 100 corresponding to location, old place " 0x0000 " is and immediately writes programmable memory cell.With reference to Fig. 5, this Mark Column 110 stores bit " X " in the present embodiment, represents this otp memory unit 100 sequencing, and has write the data of X bit length.Therefore, bit " 0x0000 " and the bit length write (being herein X bit length) can add up, to obtain a scheduler (address " 0x0000+X ") by this displacement unit 246.
Then, this address provides this scheduler (address " 0x0000+X ") to this memory array 22 to cell 242.This inspection unit 244 checks the written data bit length of corresponding otp memory unit (the present embodiment is memory cell 200) according to this scheduler.As shown in Figure 5, this otp memory unit 200 has write the data of Y bit length.Therefore address " 0x0000+X " and the Y bit length of write add up, to obtain next scheduler (address " 0x0000+X+Y ") by this displacement unit 246 again.
Then, this address provides this next scheduler (address " 0x0000+X+Y ") to this memory array 22 to cell 242.This inspection unit 244 checks the written data bit length of corresponding otp memory unit (the present embodiment is memory cell 300) according to this scheduler.As shown in Figure 5, Mark Column 330 in this otp memory unit 300 stores bit " 0 ", represent this otp memory unit 300 and not yet write data, the otp memory unit 300 corresponding to location, old place " 0x0000+X+Y " is and immediately writes programmable memory cell.
Compared to known framework, whether disclosed programmable storage 20 utilizes the Mark Column of otp memory unit to judge the sequencing of this memory cell.Therefore, disclosed programmable storage 20 does not need extra recording element to record the otp memory unit of sequencing.In addition, this programmable storage 20, can according to the bit length config memory space of data when re-writing data at every turn, then the data bit element length recording write is in Mark Column.Therefore, as long as the data stored by Mark Column by checking otp memory unit, the up-to-date address of the memory cell of these write data can be learnt.In other words, disclosed programmable storage 20 is used can to make full use of the storage area of memory cell.
On the other hand, after input data Data_in writes to these otp memory unit in this memory array 22, a read step will be performed the data reading these writes.Fig. 6 is the process flow diagram of the read method of the programmable storage of one embodiment of the invention.After abovementioned steps write data, this read method comprises the following step: from an initial address searching, last organizes programmed memory unit (step S50), and reads data (step S52) in the memory cell sequentially organizing sequencing from this last.The read method of this programmable storage 10 of the present invention is now described with an embodiment.
Referring to Fig. 4 and Fig. 7, when this programmable storage 20 carries out a read action, this search unit 24 can be searched last and organize programmed memory unit in this memory array 22, to prepare to read data.Operationally, first this address provides a start address to cell 242, such as address " 0x0000 ", to this memory array 22.Then, this inspection unit 244 checks the written data bit length of the otp memory unit (the present embodiment is memory cell 100) corresponding to address " 0x0000 ".In the present embodiment, this inspection unit 244 checks the data stored by Mark Column 110 of this memory cell 100.If this Mark Column 110 stores bit " 0 ", each memory cell represented in this memory array 22 does not all write data, therefore by this read action of termination.
In the present embodiment, this Mark Column 110 stores bit " Z ", represents this otp memory unit 100 sequencing, and has write the data of Z bit length.Therefore bit " 0x0000 " and the bit length write (being Z bit length) can add up, to obtain a scheduler (address " 0x0000+Z ") by this displacement unit 246 herein.Then, this address provides this scheduler (address " 0x0000+Z ") to this memory array 22 to cell 242.This inspection unit 244 checks the written data bit length of the memory cell (the present embodiment is memory cell 200) corresponding to address " 0x0000+Z ".If when the written data bit length of this memory cell equals zero, then the last address of this address " 0x0000+Z ", also i.e. address " 0x0000 ", corresponding otp memory unit 100 be this last organize the memory cell of sequencing.
In addition, if when the written data bit length of the memory cell corresponding to address " 0x0000+Z " is greater than zero, then address " 0x0000+Z " and the bit length of write add up, to obtain another scheduler by this displacement unit 246 again.Then repeat above-mentioned steps, from these otp memory unit, select last to organize the memory cell of sequencing with the last address according to another scheduler.This reading unit 28 sequentially reads write data by the memory cell organizing sequencing from this last.
Each unit realizes by the mode of devices at full hardware according to an embodiment of the invention, the mode of full software realizes or the element that comprises hardware and software realized.In addition, this unit also realizes by computer program product.This computer program product can be able to be used by computer or the medium of readable in computer accesses, and it provides procedure code to pass through or to be connected to a computer or the operation of any instruction execution system.This computer can with or readable in computer medium access can be any device, it can contain, stores, communicate, propagate or convey program with pass through be connected to a computer or any instruction execution system operation.
Technology contents of the present invention and technical characterstic disclose as above, but those skilled in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement.Therefore, protection scope of the present invention should be not limited to embodiment and disclosed, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by appended claim.
Claims (15)
1. a wiring method for programmable storage, this programmable storage comprises multiple single programmable memory unit, the corresponding multiple address of described multiple single programmable memory unit, and this wiring method comprises the following step:
Write programmable memory cell from an initial address searching is immediate;
Read the residue bit length of this programmable storage;
Relatively this residue bit length and inputs the bit length of data; And
When this residue bit length is greater than the bit length of these input data, immediately follows carry out following data write step from this immediate programmable memory cell that writes:
Write the bit length of these input data; And
Write this input data.
2. wiring method as claimed in claim 1, wherein from the immediate step writing programmable memory cell of an initial address searching, comprises the following step:
From this start address, check the written data bit length of corresponding single programmable memory unit; And
According to check result, this is selected immediately to write programmable memory cell, immediately follows to write this input data.
3. wiring method as claimed in claim 2, wherein checks the step of the written data bit length of corresponding single programmable memory unit, comprises the following step from this start address:
(a1) read the written data bit length of the single programmable memory unit corresponding to this start address, wherein this written data bit length is greater than zero;
(a2) this start address and this have been write bit length to add up, to obtain an address;
(a3) using the start address that this time address upgrades as, above-mentioned steps is repeated, until the written data bit length of single programmable memory unit corresponding to the start address of this renewal equals zero; And
Single programmable memory unit corresponding to given step (a3) is immediately write programmable memory cell.
4. wiring method as claimed in claim 2, wherein checks the step of the written data bit length of corresponding single programmable memory unit, comprises the following step from this start address:
Read the written data bit length of the single programmable memory unit corresponding to this start address, wherein this data bit element length equals zero; And
This single programmable memory unit corresponding to this start address is specified to write programmable memory cell for this is immediate.
5. wiring method as claimed in claim 1, wherein each single programmable memory unit has the data bit element storage area of a bit length.
6. the read method of a programmable storage, this programmable storage comprises multiple single programmable memory unit, corresponding multiple address, this programmable storage is according to wiring method write data as claimed in claim 1, and this read method comprises the following step:
From an initial address searching, last organizes programmed memory unit; And
Sequentially organize from this last in memory cell of sequencing and read data.
7. read method as claimed in claim 6, wherein from an initial address searching, last organizes the step of programmed memory unit, comprises the following step:
From this start address, check the written data bit length of corresponding single programmable memory unit; And
According to check result, select this last organize the memory cell of sequencing, sequentially to read data.
8. read method as claimed in claim 7, wherein checks the step of the written data bit length of corresponding single programmable memory unit, comprises the following step from this start address:
Read the written data bit length of the single programmable memory unit corresponding to this start address, wherein this written data bit length is greater than zero;
This start address and this written data bit length are added up, to obtain an address;
Using the start address that this time address upgrades as, repeat above-mentioned steps, until the written data bit length of single programmable memory unit corresponding to the start address of this renewal equals zero; And
If the written data bit length of this single programmable memory unit corresponding to the start address of this renewal is zero, return to a last address of the start address of this renewal; And
Specify this single programmable memory unit corresponding to this last address be this last organize the memory cell of sequencing.
9. read method as claimed in claim 7, wherein each single programmable memory unit has the data bit element storage area of a bit length.
10. a programmable storage, comprises:
Multiple single programmable memory unit, corresponding multiple address;
One searches unit, in order in a write activity in described multiple single programmable memory unit, search and immediately write programmable memory cell, or in a read action in described multiple single programmable memory unit, search last and organize programmed memory unit;
One writing unit, for immediately writing programmable memory cell from this, immediately follows writes bit length and this input data of input data;
One reading unit, for organize sequencing from this last memory cell in sequentially read data; And
One inspection unit, in order to check the residue bit length of this programmable storage.
11. programmable storages as claimed in claim 10, wherein each single programmable memory unit has the data bit element storage area of a bit length.
12. programmable storages as claimed in claim 10, wherein this search unit also comprises:
One address to cell, in order to provide a start address or a scheduler to described multiple single programmable memory unit;
One inspection unit, in order to check the written data bit length of the single programmable memory unit corresponding to this start address or this scheduler;
One displacement unit, in order to provide this scheduler to this address to cell according to the check result of this inspection unit.
13. programmable storages as claimed in claim 12, wherein when this programmable storage performs this write activity, when the written data bit length of the single programmable memory unit corresponding to this start address or this scheduler equals zero, then this start address or this single programmable memory unit corresponding to this scheduler write programmable memory cell for this is immediate.
14. programmable storages as claimed in claim 12, wherein when this programmable storage performs this write activity, when the written data bit length of the single programmable memory unit corresponding to this start address is greater than zero, then this start address and this bit length add up by this displacement unit, to obtain this scheduler.
15. programmable storages as claimed in claim 12, wherein when this programmable storage performs this read action, when the written data bit length of the single programmable memory unit corresponding to this start address or this scheduler equals zero, this displacement unit will provide the last address of this start address or this scheduler to this address to cell, and this single programmable memory unit corresponding to last address be this last organize the memory cell of sequencing.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1298154A (en) * | 1999-11-29 | 2001-06-06 | 三菱电机株式会社 | Memory reference system for stored data in selective reference to storage |
| CN101923513A (en) * | 2010-08-11 | 2010-12-22 | 深圳市同洲电子股份有限公司 | Data writing and reading method of memory, system and FLASH memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003015942A (en) * | 2001-07-03 | 2003-01-17 | Casio Comput Co Ltd | Method of writing data into memory, data write processing program and data write device |
| JP5328020B2 (en) * | 2009-01-15 | 2013-10-30 | セイコーインスツル株式会社 | Memory device and memory access method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1298154A (en) * | 1999-11-29 | 2001-06-06 | 三菱电机株式会社 | Memory reference system for stored data in selective reference to storage |
| CN101923513A (en) * | 2010-08-11 | 2010-12-22 | 深圳市同洲电子股份有限公司 | Data writing and reading method of memory, system and FLASH memory |
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