CN1298154A - Memory reference system for stored data in selective reference to storage - Google Patents
Memory reference system for stored data in selective reference to storage Download PDFInfo
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- CN1298154A CN1298154A CN 00126428 CN00126428A CN1298154A CN 1298154 A CN1298154 A CN 1298154A CN 00126428 CN00126428 CN 00126428 CN 00126428 A CN00126428 A CN 00126428A CN 1298154 A CN1298154 A CN 1298154A
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Abstract
In this system for accessing the desired data of a ROM from a processor and a controller, word length information for indicating the length of the data is stored immediately before the respective data beforehand in the ROM. At the time of reading the desired data, when a processing control part supplies a read start address corresponding to the desired data to a memory chip, the desired data of the length indicated by the word length information in the read address of the ROM corresponding to the address generated by an address generation circuit, a comparator and an incremental part are read and supplied to the processing control part 66. In such a manner, the processor and the controller selectively read only the desired data if a variable length just by supplying the read start address and the memory access efficiency is improved.
Description
The present invention relates to memory access system, particularly including selectively, visit is stored in the memory access system that the data in the storer are used in advance.
So far in the system of reference-to storage, when storer is read data, need specify the regular length of address that sense data uses and the data of reading by intrasystem processor and controller one side, for example the fixing word length of data.One example of existing memory access mode below is described.
Figure 12 is the simple structural drawing of existing memory access system.Among the figure, the existing memory access system comprises: have address generator circuit 36 and the memory chip 34 of having stored the storer 38 of a plurality of data D; And the desirable data D of storage in the readout memory 38 and carry out the processor and the controller 33 of predetermined process.
In the work of the desirable data D that processor and controller 33 are stored in readout memory 38, the word length information 35A of the data length that representing of reading that desirable data D uses fixed and read the address generator circuit 36 that start address 35B supplies with memory chip 34.Here, read start address and be address, read the storer 38 that desirable data D uses from storer 38, corresponding to the address of initial appointment corresponding to desirable data D.Storer 38 for example is a graphic memory of having stored 3 D graphic data.
The address generator circuit 36 of memory chip 34 is according to the fixing word length information 35A that is supplied with and read start address 35B, and that reads successively that desirable data D uses reads address 37.Then, read address 37 according to what take place successively, assigned address is read desirable data D from storer 38, exports to processor and controller 33 as data 39.
Like this, utilize processor and controller 33 so far, specify the word length information 35A of the fixing word length of expression and read start address 35B, can read desirable data 39.
; so far when storer is read data; utilize processor and controller 33 to specify the word length information 35A of the fixing word length of expression without exception, so can not from storer 38, only read the data of desirable random length selectively among a plurality of data D of continuous storage.Therefore, store unwanted (undesirable) data in the storer 38, or when storer 38 is read desirable data, haveed no alternative but read unwanted data, produced the waste of memory access.Need when memory access in the system of big bandwidth, the waste of such memory access becomes the reason that the entire system performance descends.In addition, the bandwidth during memory access is stipulated with (data transfer clock * data bus bandwidth).If for example carry out 10 data transfer p.s. during memory access, then use 10Hz * data bus bandwidth (data volume that is transmitted in the data transfer for example is 8) to stipulate.
In addition, open flat 11-184831 communique and special open the technology that the data length that utilizes desirable data when a kind of visit in the desirable data that storer is carried out is provided in the flat 7-200506 communique conducts interviews the spy.In these communiques, the concrete program and its needed concrete structure that do not provide the memory access that utilizes data length to carry out to use be we can say the shortage realizability.
The object of the present invention is to provide a kind of memory access system that can improve memory access efficient.
In order to achieve the above object, memory access system in a certain respect of the present invention has: storage part, handling part and address generating unit.Storage part comprises: the storer of having stored a plurality of information at least; And according to reading address information, according to the memory controller of address sense information from storer of appointment.For the desired information of storing in the readout memory, the start address information of reading that the address of reading beginning in the storer corresponding with desired information is used is represented in handling part output at least, from the desired information that the storer input is read out, carry out predetermined process by memory controller.Address generating unit utilization represent desired information kind categorical data and from the start address information of reading of handling part output, length according to desired information, the address information of reading that desired information uses is read in generation, exports to memory controller.
Therefore, in above-mentioned memory access system, the address generating unit utilization categorical data corresponding and read start address information with desired information, length according to desired information, generation is read the address information of reading that desired information uses from storer, export to memory controller,, can only read desired information from storer so specify by the address of being undertaken by memory controller.
Therefore, utilize the categorical data corresponding and read start address information, can only read desired information from storer with desired information.In other words, can omit reading of the gibberish of carrying out from storer, can increase the bandwidth that is equivalent to above-mentioned clipped and visit storer, and then can also improve the efficient of the predetermined process of handling part.
In above-mentioned memory access system, the address generating unit has determines the length determination portion used corresponding to the length of the desired information of categorical data.
Therefore, in above-mentioned memory access system, determine the length of desired information according to categorical data by the length determination portion of address generating unit.
Therefore, corresponding to the desired information length of categorical data determine be not in handling part but in the generating unit of address, carry out, even so the memory access of carrying out with categorical data does not increase the load of handling part yet and keeps the efficient of predetermined process.
In above-mentioned memory access system, the length determination portion has and each of a plurality of different types of data and each tables of data that disposes accordingly of a plurality of length data of the length of expression desired information, according to categorical data, from tables of data read corresponding to the length data of the corresponding desired information of the type data.
Therefore, in above-mentioned memory access system, the length data determination portion has and each of a plurality of categorical datas and each tables of data that disposes accordingly of a plurality of length data, according to the categorical data corresponding with desired information, reads corresponding length data from this tables of data.
Therefore, in the length data determination portion, owing to prepared such tables of data, so, can determine the length data of this desired information simply according to the categorical data of desired information.Therefore, can only read desired information from storer effectively with categorical data.
In above-mentioned memory access system, each in a plurality of information in the storer comprises more than one desirable data, and categorical data is represented separately dissimilar of the more than one desirable data that comprise in the desired information.
Therefore, in above-mentioned memory access system, can represent separately dissimilar of the more than one desirable data that comprise in the desired information with the categorical data of desired information.
Therefore, reading under the situation of desired information from storer with categorical data, reading of desired information by once can be read different types of more than one desirable data, so can more effectively only read desirable data from storer.
In above-mentioned memory access system, for the desired information of storing in the readout memory, handling part is also exported to the address generating unit with the categorical data corresponding with desired information.
Therefore, in above-mentioned memory access system, supplied with the address generating unit because read the categorical data that desired information uses from handling part,, read desired information from storer so can use categorical data according to the predetermined process content of handling part from storer.
Therefore, can read the desired information of representing with the categorical data that is suitable for the predetermined process content, can improve the efficient of the predetermined process of handling part from storer.
In above-mentioned memory access system, in storer also corresponding to each storage class data of a plurality of information.And memory controller is read the categorical data corresponding with desired information according to based on specifying from the pairing address of reading address information of the start address information of reading of handling part output from storer.
Therefore, in above-mentioned memory access system,,, read the categorical data corresponding with desired information from storer according to the appointment of address according to the address information of reading corresponding with the start address information of reading of desired information.
Therefore,, can obtain the categorical data corresponding simply, can more effectively read desired information from storer with desired information by only each of categorical data and a plurality of information being stored in the storer accordingly.
In above-mentioned memory access system, also have Data Control portion.Desired information and the categorical data corresponding that the input of Data Control portion is read from storer with desired information, determine on one side the kind separately of the more than one desirable data that comprise in this desired information according to categorical data, on one side this desired information is exported to handling part.
Therefore, in above-mentioned memory access system, each of more than one desirable data from the desired information that storer is read, determine its kind by Data Control portion on one side with categorical data, it is supplied with handling part on one side, although handling part is not known the categorical data of the desired information of reading, on one side also can determine to import the kind separately of the more than one desirable data that comprise in this desired information, Yi Bian with its input.
Therefore, can improve the efficient of the whole processing that comprise the predetermined process of carrying out with the desired information in the handling part.
In above-mentioned memory access system, predetermined process is that the image displaying that rendering image is used is handled.And each of a plurality of information in the storer is the image definition information that definition institute image represented is used.
Like this, the memory access system of can will have above-mentioned such series of features is applied to carry out the system that image displaying is handled, and desirable image definition information is only read from the storer of a plurality of images definition information of having stored definition institute image represented and using by this system.
Therefore, handle in the system of usefulness, can only read desirable image definition information effectively, carry out image displaying and handle, can improve the efficient that image displaying is handled from storer at image displaying.
In above-mentioned memory access system, under the situation that update image is described in image displaying is handled, define the part that this image of information definition should upgrade with image.
Therefore, in above-mentioned memory access system, under the situation that update image is described in image displaying is handled, from storer, only read the image definition information of answering the updated images part corresponding when describing.
Therefore, under the situation that one side update image is described on one side, during describing in the image definition information not corresponding information, the unwanted information of updated images part from storer, do not read, so the access efficiency height of storer, and then the efficient that image displaying is handled is also high.
The memory access system of another aspect of the present invention has: storage part, handling part and address generating unit.Storage part comprises: the storer of having stored a plurality of information at least; And according to specify the memory controller of sense information from storer based on the address of reading address information.For the desired information of storing in the readout memory, the start address information of reading that the start address of reading in the storer corresponding with desired information is used is represented in handling part output, by the desired information that the memory controller input is read from storer, carry out predetermined process.Address generating unit utilization is represented length information that the length of desired information is used and from the start address information of reading of handling part output, generates according to length data and reads the address information of reading that desired information uses, and exports to memory controller.
Therefore, in above-mentioned memory access system, the address generating unit utilization length data corresponding and read start address information with desired information, length according to desired information, generation is read the address information of reading that desired information uses from storer, export to memory controller,, can only read desired information from storer so specify by the address of being undertaken by memory controller.
Therefore, utilize the length data corresponding and read start address information, can only read desired information from storer with desired information.In other words, can omit reading of the gibberish of carrying out from storer, can increase the bandwidth that is equivalent to above-mentioned clipped and visit storer, and then can also improve the efficient of the predetermined process of handling part.
In above-mentioned memory access system, predetermined process is that the image displaying that rendering image is used is handled.And each of a plurality of information in the storer is the image definition information that definition institute image represented is used.
Therefore can above-mentioned memory access system be applied to carry out the system that image displaying is handled, the storer that this system defines information from a plurality of images of having stored definition institute image represented and using is only read desirable image and is defined information.
Therefore, handle in the system of usefulness, can only read desirable image definition information effectively, carry out image displaying and handle, can improve the efficient that image displaying is handled from storer at image displaying.
In above-mentioned memory access system, under the situation that update image is described in image displaying is handled, define the part that this image of information definition should upgrade with image.
Therefore, in above-mentioned memory access system, under the situation that update image is described in image displaying is handled, from storer, only read the image definition information of answering the updated images part corresponding when describing.
Therefore, under the situation that one side update image is described on one side, when describing in the image definition information not corresponding information, the unwanted information of updated images part from storer, do not read, so the access efficiency height of storer, and then the efficient that image displaying is handled is also high.
In above-mentioned memory access system, the address generating unit has: address generating unit, address increment portion and stop control part.The address information of reading in the storer corresponding with reading start address information takes place in the address generating unit.Address increment portion Input Address generating unit takes place reads address information, increases progressively back output successively.Stop control part and read the end of reading that address information is represented desired information, control, so that address increment portion stops to read increasing progressively of address information corresponding to having judged according to length data by what address increment portion increased progressively.
Therefore, in above-mentioned memory access system, read the address and read the address after increasing progressively one by one though in the generating unit of address, generate to make by address increment portion, but, stop this and increase progressively work by stopping control part according to the situation of reading the address of reading end that has generated the expression desired information by length data.
Therefore, in the generating unit of address, generate the address of reading only be equivalent to the length represented by the length data of desired information, so can only read desired information from storer reliably and easily.
Memory accessing circuit of the present invention is to supply with the memory accessing circuit that storer is used with read the address that desirable data use from storer, and it has length determination portion and address generating unit.The length determination portion is accepted the categorical data whether above-mentioned desirable data of decision comprise the data of any type, the data length of specified data, the length data of output expression data length.The address generating unit is according to start address and length data, calculated address.Start address is represented the beginning address of desirable data.
Therefore, in above-mentioned memory accessing circuit, accept the categorical data of desirable data by the length determination portion, in case the length data of the data length of the desirable data of output indication, just by the beginning address of address generating unit according to the address of the beginning of length data and the desirable data of expression, generation is read the address that desirable data are used from storer, supplies with storer.
Therefore, with the categorical data and the start address of desirable data, can only read desirable data from storer.In other words, can omit and read useless data, visit storer thereby correspondingly enlarge bandwidth from storer.
In above-mentioned memory accessing circuit, the length determination portion has tables of data, is used for storage representation to be stored in a plurality of data of the data length of the data in the storer respectively, and tables of data is accepted categorical data, and one in a plurality of data is exported as length data.
In above-mentioned memory accessing circuit, categorical data is stored in the storer, and the length determination portion is accepted categorical data from storer.
In above-mentioned memory accessing circuit, categorical data is comprised in the desirable data, and start address is represented the place of storage class data.
In above-mentioned memory accessing circuit, the address generating unit is carried out the device of predetermined process from utilizing desirable data, accepts start address and categorical data.
In above-mentioned memory accessing circuit, also have the data storage control part.The data storage control part has a plurality of registers, selects one or more register in a plurality of registers according to categorical data.In the data storage control part,, then desirable data are write selected one or more register according to the type of each data if accept desirable data from storer.
In above-mentioned memory accessing circuit, the data storage control part has a plurality of doors corresponding with a plurality of registers, and each is connected from the register of correspondence and storer and accepts on the common points of desirable data, carries out conducting according to categorical data.
In above-mentioned memory accessing circuit, the data storage control part have be connected on a plurality of registers, storage is from the cache memory of the desirable data of storer output, cache memory is according to exporting stored data from the address of address generating unit output.
In above-mentioned memory accessing circuit, desirable data comprise the 3 D graphic data of at least one in following 9 categorical datas of expression, these 9 categorical datas are: define the x coordinate figure used on polygonal each summit, y coordinate figure, z coordinate figure, about the x coordinate of structural drawing, about y coordinate, red information, green information, the blue information of structural drawing and the alpha information of representing transmissivity, categorical data is specified the one or more type of the data that comprise 3 D graphic data.
Fig. 1 is the structured flowchart of the memory access system of the first embodiment of the present invention.
Fig. 2 is the structured flowchart of the memory access system of the second embodiment of the present invention.
Fig. 3 is the address generating unit among Fig. 2 and the structured flowchart of data storage control part.
Fig. 4 A～Fig. 4 F is the sequential chart that the gate control in the key diagram 3 is used.
Fig. 5 is the structured flowchart of the memory access system of the third embodiment of the present invention.
Fig. 6 is one of the three-dimensional picture storer of an expression fourth embodiment of the present invention illustration.
Fig. 7 is one of the structure memory used of three-dimensional picture of an expression fourth embodiment of the present invention illustration.
Fig. 8 is the structural drawing of the three-dimensional picture storer of the fifth embodiment of the present invention.
Fig. 9 is the structural drawing of the graphic memory of the expression sixth embodiment of the present invention.
Figure 10 is the structural drawing of the memory access system of the seventh embodiment of the present invention.
Figure 11 is the address generating unit among Figure 10 and the structured flowchart of data storage control part.
Figure 12 is the simple structural drawing of existing memory access system.
Below, with reference to description of drawings each embodiment of the present invention.In addition, in each embodiment, the data storage that should read is in the continuous zone of storer, stipulated the continuous length of these data with word length, but word length do not determined.
In addition, though each embodiment has provided the situation of the read-out system that is applicable to ROM (abbreviation of ROM (read-only memory)), also can be applicable to the read-out system of RAM (abbreviation of random access memory).
(first embodiment)
In the present embodiment, in the system of reference-to storage, stored the word length information of the word length of the data that expression should read before each data in storer, read data by the length of this word length information appointment.Therefore, can read the data of variable-length.
Fig. 1 is the structured flowchart of the memory access system of the first embodiment of the present invention.Memory access system comprises memory chip MC1 and processor and controller 71 among the figure, above-mentioned memory chip MC1 comprises: address generator circuit 9, comparer 11, increase progressively the address specifying part ADS and the sense buffer RB of portion 12, ROM61, related setting with ROM61, above-mentioned processor and controller 71 have the processing controls portion 66 that the laggard capable predetermined process of the desirable data of storing among the ROM61 is used of reading.
In ROM61,, before each data D, stored the word length information WL of the word length of representing these data D as the desirable a plurality of variable length data D that read object storage.The length of word length information WL is regular length FL.Each data D is stored in the regional later continuous zone of having stored corresponding word length information WL.
Under the situation of the desirable data D that processor and controller 71 are stored in reading ROM61, will read the start address 3 of reading of usefulness by processing controls portion 66 and export to address generator circuit 9.Here, what is called is read start address, corresponding in order to read desirable data (information) from storer storer the address of initial appointment.In addition, read the beginning address that start address is represented desirable data.
From ROM61 with read start address 3 corresponding address and begin the continuous data D of length that has stored word length information WL and after word length information WL, represented with this word length information WL.
Address generator circuit 9 takes place to read address 4 among the ROM61 corresponding with reading start address 3, supply address specifying part ADS, comparer 11 and increase progressively portion 12.Increasing progressively portion 12 exports reading of being supplied with after address 4 increases settings.Pass through address generator circuit 9 from the address 4 of reading that increases progressively portion's 12 outputs, be supplied to address specifying part ADS.Therefore, in the specifying part ADS of address, Yi Bian read address 4 later the read address 4 corresponding with reading start address 3 increased progressively, Yi Bian supplied with one by one.Here, what is called is read the address, represents in order to read desirable data (information) address of appointment in storer.
Address specifying part ADS reads address 4 according to what supply with one by one, ROM61 is carried out the address specify, so can read word length information WL from ROM61, supplies with comparer 11 by sense buffer RB.In addition, the desirable data D of storage also is read out after word length information WL, exports to processing controls portion 66 as data 7.
If comparer 11 has been supplied to word length information WL, just to comparing by the word length of the desirable data D that reads so far that reads address 4 expressions that supplies with one by one and the word length of representing with word length information WL.Comparative result, if (word length of representing with word length information WL 〉=by the word length of supplying with one by one of reading the desirable data D that reads so far that represents address 4), then proceed to increase progressively work by increasing progressively portion 12.After this, if become (word length of representing with word length information WL＜by the word length of the desirable data D that reads so far that reads address 4 expressions that supplies with one by one), then comparer 11 will stop to increase progressively the stop signal CS that work uses and export to the portion of increasing progressively 12, stop to increase progressively work so increase progressively portion 12.So finish data D the reading of the length represented with word length information WL from ROM61.
Therefore, being read out, export to processor and controller 71 as data 7 with the data D that reads the length that this word length information of usefulness WL of storage represents after the corresponding word length information WL that reads storage in the address 4 of start address 3 of ROM61.
In the present embodiment, specify the word length of reading desirable data by processor and controller one side not needing to resemble in the past.In the present embodiment, owing to store the word length information WL of the length of specifying these data D in advance before each data D that becoming in ROM61 read object, so processor and controller 71 are read start address 3 as long as specify, just can not read unwanted data, and only read desirable data D selectively.Therefore, can will read desirable data D at high speed after the data bus bandwidth increase.
(second embodiment)
In the present embodiment, in the system of reference-to storage, a plurality of data sets that constitute by desirable dissimilar more than one data have been stored up at store memory.And, in storer, before each data set, stored the Data Labels information of the regular length that the type of representing each data in this data set uses.Only read data during sense data by the type of the content appointment of this Data Labels information.Therefore, can be with variable-length and only read the data of desirable type.
In addition, the type of the so-called here data with the Data Labels information representation is the information of the type of these data of using of each data in the expression monodrome ground determination data group.
Fig. 2 is the structured flowchart of the memory access system of the second embodiment of the present invention.Among the figure, memory access system comprises memory chip MC2 and processor and controller 72, and above-mentioned memory chip MC2 comprises: the address specifying part ADS and the sense buffer RB of ROM62, related setting with ROM62.Processor and controller 72 comprise: the data storage control part 32 that the data that address generating unit 22, temporary transient storage are read from ROM62 are used and read the processing controls portion 67 that the laggard capable predetermined process of desirable data is used from ROM62.
Processing controls portion 67 is with clock signal clk, reset signal RST and read commencing signal RS and export to data storage control part 32.Will be explained below these signals.
In ROM62, stored a plurality of data set DGi (i=1,2,3 ...) and the Data Labels information D Fi this data set DGi before corresponding with data set DGi (i=1,2,3 ...).
In each data set DGi, comprise data of different types Dj continuous more than (j=1,2,3 ...).Data Labels information D Fi represents the information that the type of each data Dj of comprising among the corresponding data set DGi is used by the sign of multidigit.
Fig. 3 is the address generating unit 22 among Fig. 2 and the structured flowchart of data storage control part 32.Address generating unit 22 comprises among the figure: for from the ROM62 sense data, generate and export the address generator circuit 10 of reading address 4 usefulness among the ROM62 one by one; Read portion that increases progressively 13 and the comparer of being supplied with address 4 14 from what address generator circuit 10 was exported one by one; And flag register 24 and table TB.
Increase progressively portion 13 input from address generator circuit 10 outputs read address 4, export after increasing setting.Be supplied to address specifying part ADS from the address 4 of reading that increases progressively portion's 13 outputs by address generator circuit 10.
The content 15 of the Data Labels information D Fi that reads from ROM62 is written into flag register 24.According to the content 15 that is written into the Data Labels information D Fi in the flag register 24, carry out the address and specify, read the content of table TB.In table TB, with content 15 corresponding address of the Data Labels information D Fi that reads from ROM62 be that table address 5 is stored word length information WL1 respectively accordingly.Word length information WL1 represents that the Data Labels information D Fi that represents with corresponding table address 5 determines the word length of the more than one data Dj of type.Therefore according to the content of flag register 24, carrying out the address by his-and-hers watches TB specifies, can read the continuous word length of length of the more than one data Dj that is equivalent to the represented type of the Data Labels information D Fi that reads from ROM62, supply with comparer 14 as word length information WL1.
By comparer 14 with increase progressively the work that increases progressively that portion 13 compares work and reads address 4.These work are identical with above-mentioned first embodiment's, so explanation simply here.
In other words in comparer 14,, monitor by increasing progressively portion 13 to make and read address 4 and increase progressively one by one in order to read data from ROM62 by the word length size of the word length information WL1 appointment of reading from table TB.In this monitors, to read from ROM62 under the data conditions of the length scale of representing with word length information WL1, comparer 14 is supplied with stop signal CS and is increased progressively portion 13, makes the portion of increasing progressively 13 stop to read the work that increases progressively of address 4.Increase progressively portion 13 proceeded to read address 4 before stop signal CS is supplied to the work that increases progressively.Read address 4 by address generator circuit 10 by what increase progressively that portion 13 increases progressively back output one by one, supplied with the address specifying part ADS of memory chip MC2 one by one.
Data storage control part 32 comprises: the flag register 25 of the content 15 of the Data Labels information D Fi that temporary transient storage is read from ROM62, multistage gate control portion 50 and the internal register group 77 that comprises a plurality of registers.
Flag register 25 is individually stored a plurality of positions of Data Labels information D Fi.Corresponding to each position of the Data Labels information D Fi in the flag register 25, be provided with each register of each gate control portion 50 and internal register group 77.
Here, Data Labels information D Fi supposition is an information of for example using 4 bit representations.Therefore, in flag register 25, individually store 4 bit data, comprise four registers 771～774 in addition in the internal register group 77.
Each data 16 of reading continuously from ROM62 are stored in each register 771～774 of internal register group 77 respectively via door G1～G4.16 of the data of at this moment, reading are stored among the G1～G4 in the register by the door correspondence of door enabling signal conducting corresponding among door enabling signal GE1～GE4.
Gate control portion 50 comprises transmission gate circuit TG1 and TG2 and latchs and export latch cicuit LT by the signal of transmission gate circuit transmission according to clock signal clk.Transmission gate circuit TG1 and TG2 utilize the gating signal GS by the value representation of position corresponding in the flag register 25 to control.Corresponding gating signal GS is 0 o'clock, transmission gate circuit TG1 conducting, and gating signal GS is 1 o'clock, transmission gate circuit TG2 conducting.
Fig. 4 A～Fig. 4 F is the sequential chart of the control usefulness of the door G1～G4 in the key diagram 3.With reference to Fig. 4 A～Fig. 4 F and Fig. 3, supply with when reading commencing signal RS by the initial rising edge of clock CLK, if the value of the position corresponding with door G1 in the flag register 25 be " 1 ", then a door enabling signal GE1 becomes " high level ", a G1 conducting.Therefore, the data 16 of at this moment reading are stored in the register 774 by door G1.
At the next rising edge of clock CLK, read among the latch cicuit LT that commencing signal RS is maintained at the first order, if the value of the position in the flag register corresponding with door G2 25 be " 1 ", then a door enabling signal GE2 becomes " high level ", a G2 conducting.Therefore, the data 16 of at this moment reading are stored in the register 773 by door G2.Below, the data 16 of reading can be stored in respectively in register 772 and 771 equally.
Secondly, the concrete working condition of present embodiment is described with reference to Fig. 2 and Fig. 3.At first, will read start address 3 from processing controls portion 67 and supply with address generating unit 22 in order to read the data of more than one desirable type from ROM62.The address generator circuit 10 of address generating unit 22 takes place to read address 4 with reading of being supplied with among the corresponding ROM62 of start address 3, supply address specifying part ADS, comparer 14 and increase progressively portion 13.
Address specifying part ADS is read address 4 according to what supply with, ROM62 is carried out the address to be specified, so specify by this address, the Data Labels information D Fi that reads from ROM62 passes through sense buffer RB, and the content 15 that is used as Data Labels information D Fi is supplied with data storage control part 32 and address generating units 22.At this moment, suppose in the flag register 25 of the flag register 24 of address generating unit 22 and data storage control part 32 and stored " 1100 " respectively.
As mentioned above, specify, can read corresponding word length information WL1 from table TB according to address based on the content " 1100 " of flag register 24.In the case, read " 2 ", supply with comparer 14 as word length information WL1.In comparer 14, to comparing with the word length of the data of reading from ROM 62 so far of reading that address 4 represents and " 2 " word length of supplying with from table TB, when this comparative result represents that the word length of data surpasses " 2 " word length, stop signal CS is increased progressively portion 13 from comparer 14 supplies, stop the work that increases progressively of reading address 4 of the portion that increases progressively 13.
On the other hand, when not surpassing " 2 " word length, proceed the work that increases progressively of reading address 4 of the portion that increases progressively 13, so proceed to read the data of the data set DGi of storage after Data Labels information D Fi from ROM62.Its result, the data of the data set DGi of " 2 " word length size are supplied to data storage control part 32 as data 16 after reading from ROM62.
Here, suppose and read data set DGi shown in Figure 2, comprise data D1 and D2 as data 16.Therefore, according to sequential chart shown in Figure 4, have only the door G1 and the G2 conducting of data storage control part 32, so data D1 is deposited in register 774, data D2 is deposited in register 773.After this, from register 774 and 773 sense datas, data D1 and D2 are determined type on one side, as data 17 from data storage control part 32 supply with processing controls portions 67 on one side.
In addition, here, though Data Labels information D Fi is by 4 information that constitute, always not this situation.
When Data Labels information D Fi is maximal value, the data of all types of expression energy composition data group DGi.And under the situation of the type of the data of each bit representation composition data group DGi of Data Labels information D Fi, the data Dj that reads represents it is data corresponding to which type.If tentation data D1 is made of a word, then the data of expression two words of storage after Data Labels information D Fi (=" 1100 ") are the data (data D1 and D2) that correspond respectively to Class1 and 2.
In the present embodiment, specify the word length of the data (desirable data) that should read continuously by processor and controller 72 not needing to resemble in the past.In the present embodiment, stored the Data Labels information D Fi of the type of representing the data Dj that comprises among this data set DGi in advance before in ROM62 each data set DGi, 72 of processor and controllers need to specify the read start addresss 3 corresponding with desirable data set DGi to get final product.Therefore, do not dispose the unwanted data Dj among the ROM62, do not read the data Dj of unwanted type yet, can effectively utilize ROM62, and can increase data bus bandwidth and carry out high speed and read, efficiently reference-to storage from ROM62.
(the 3rd embodiment)
In the present embodiment, in the system of reference-to storage, to represent that by processor and controller the Data Labels information and corresponding with the desirable data start address of reading of regular length of the type of desirable data supply with storer one side, be provided with the mechanism of only reading in storer one side by the data of the type of the Data Labels information appointment of being supplied with.Therefore, can be with variable-length and only read desirable data selectively.
Fig. 5 is the structured flowchart of the memory access system of the third embodiment of the present invention.Among the figure, memory access system comprises memory chip MC3 and processor and controller 73, above-mentioned memory chip MC3 comprises: stored the ROM63 of a plurality of data set DGi, related setting with ROM63 address specifying part ADS, sense buffer RB, flag register 24, show TB, increase progressively portion 6, comparer 7 and address generator circuit 8, above-mentioned processor and controller 73 comprise from ROM63 reads the processing controls portion 68 that the laggard capable predetermined process of desirable data is used.
Above data of different types Dj of each data set DGi storage among the ROM63.Here suppose the more than one data of in each data set DGi, having stored continuously among data D1～D4 for example.
The structure of table TB and identical from the method for table TB sense data and Fig. 3, explanation is omitted.In addition, identical with Fig. 3 explanation of address generator circuit 8, comparer 7 and the working condition that increases progressively portion 6, explanation is omitted.
At work, at first in order to read the data of more than one desirable type from ROM63, processing controls portion 68 will read start address 3 and represent that the Data Labels information D F that desirable data type is used supplies with memory chip MC3.
The Data Labels information D F that is supplied to memory chip MC3 is stored in the flag register 24, and is same, reads start address 3 and is supplied to address generator circuit 8.
After, Yi Bian by address generator circuit 8, comparer 7 and increase progressively portion 6 and compare processing,, address specifying part ADS are supplied with in the address 4 of reading that generates Yi Bian increase progressively one by one.
At this moment,, read corresponding word length information WL1, supply with comparer 7 with this Data Labels information D F from showing TB according to based on the address appointment of the Data Labels information D F of the content of register 24 as a token of.
Therefore, 7 pairs of comparers are compared by the word length of the data of supplying with one by one of reading from ROM63 so far of reading address 4 expressions and the word length of representing with word length information WL1, surpass the word length of representing with word length information WL1 if judge the word length of the data of reading, then stop signal CS is exported to the portion of increasing progressively 6.Increase progressively the supply of portion 6, stop to read the work that increases progressively of address 4, thereby stop from the work of ROM63 sense data corresponding to stop signal CS.
In ROM63, specify according to the address based on reading address 4 of being undertaken by address specifying part ADS, proceed the work of reading, its result can read the data of the length of representing with word length information WL1.In the case, if supposition word length information WL1 represents two words, then can read the data of reading two word sizes of storing in the address among the ROM63 corresponding with reading start address 3.In the case, suppose the data set DG2 among Fig. 5 carried out the address appointment that then sense data D1 and D2 continuously as the data 18 of desirable type, are supplied with processing controls portion 68 respectively by sense buffer RB.
When Data Labels information D F is maximal value, the data of all types of expression energy composition data group DGi.And under the situation of the section of each bit representation composition data group DGi of Data Labels information D F, the data Dj that reads represents it is data corresponding to which data segment.Under the situation that data D1 is made of a word, Data Labels information D F (=" 1100 ") the expression data (data D1 and D2) corresponding with data segment 1 and 2 difference are desirable data.Here, each section of tentation data group DGi is all types of consistent with data, then can from memory chip MC3 only read with ROM63 read the corresponding data Dj that reads a desirable above type of storage the address 4 of start address 3.
(the 4th embodiment)
In the 4th embodiment, provided memory access system with first embodiment be applied to the access graphics storer (for computing machine on display rendering image or character and write the memory of data of describing usefulness) situation.In the case, 66 pairs of contents of reading from ROM61 of processing controls portion are carried out graphics process (image displaying processing).
In the present embodiment, the word length information WL that the beginning of each data in the graphic memory of having stored 3 D graphic data is provided with the data that expression reads in continuously can read the data by the length scale of word length information WL appointment continuously.
Fig. 6 is one of the three-dimensional picture storer of expression the 4th an embodiment illustration.A plurality of data D have been stored in the three-dimensional picture storer 2 in Fig. 6.Each data DK comprises the information of describing that defines polygonal each summit continuously, and this polygonal each summit is made of following each amount: X (x coordinate figure), Y (y coordinate figure), Z (z coordinate figure), U (about the x coordinate of structural drawing), V (about the y coordinate of structural drawing), R (red information), G (green information), B (blue information) and α (transmissivity information).Before each data D, stored the word length information WL of these data D.By specifying, read word length information WL based on the address of the address of supplying with from processor and controller 71 of reading start address 3 pairing three-dimensional picture storeies 2.By the ROM61 among Fig. 1 being replaced the three-dimensional picture storer 2 among Fig. 6, read under the situation of data necessary D from graphic memory 2 when the polygonal summit of definition, 71 of processor and controllers will be corresponding with these data reads memory chip MC1 one side that start address 3 supplies with graphic memories 2 and gets final product.
Fig. 7 is one of the structure memory used of three-dimensional picture of expression the 4th an embodiment illustration.In structure memory shown in Figure 71, stored arbitrary dimension (variable-length) a plurality of structured data TXDi (i=1,2,3 ...) be data D.By the ROM61 among Fig. 1 being replaced the structure memory 1 among Fig. 7, when reading desirable data D from structure memory 1, even processor and controller 71 be the size of specified structure data TXDi (data D) not, and the start address 3 of reading that only will be corresponding with this desirable structured data TXDi is supplied with memory chip MC1, just can only read desirable structured data.
(the 5th embodiment)
In the present embodiment, provided the situation that the memory access system of second embodiment is applied to the access graphics storer.In the case, 67 pairs of contents of reading from ROM62 of processing controls portion are carried out graphics process.
Fig. 8 is three-dimensional picture storer 42 structural drawing of the fifth embodiment of the present invention.In three-dimensional picture storer 42, storing data set DGi in the address 4 by start address 3 pairing the reading of reading of processor and controller appointment, this data set DGi is made of with the data of an above type of representing with this Data Labels information D Fi after this Data Labels information D Fi Data Labels information D Fi.Stored the data that define more than at least a in 9 types of data using on polygonal each summit in data set DGi continuously, this polygonal each summit is made of following each amount: X (x coordinate figure), Y (y coordinate figure), Z (z coordinate figure), U (about the x coordinate of structural drawing), V (about the y coordinate of structural drawing), R (red information), G (green information), B (blue information) and α (transmissivity information).
ROM62 among Fig. 2 is being replaced under the situation of the three-dimensional picture storer 42 among Fig. 8, in three-dimensional picture storer 42, from the type that the start address 3 pairing Data Labels information D Fi that read storage the address 4 are illustrated in the more than one data that should be updated in polygonal the describing of reading of processor and controller 72 supplies.At Data Labels information D Fi is under the situation of 9 information " 110000000 ", and everybody necessary 9 types with defining above-mentioned polygonal summit respectively data are corresponding one by one.
Now, when the Data Labels information D Fi that read in address 4 storage corresponding with reading start address 3 was Data Labels information D F1 among Fig. 8, expression was new X (x coordinate figure) and new Y (y coordinate figure) according to the data of the type that this Data Labels information D F1 reads.Therefore, start address 3 is read in 72 appointments of processor and controller, just can supply with the Data Labels information D F1 of type of the data that expression reads and the data (new X (x coordinate figure) and new Y (y coordinate figure)) of the type that should be updated as data 17.
In the past, in the frame memory that in three-dimensional picture is handled, frequently uses etc., the data of the type of describing middle frequent variations that is called coordinate data/depth data have been disposed, disposed simultaneously about the data of indeclinable type almost in the describing of the data of color, so the utilization ratio of storer is bad.Yet, as shown in this embodiment since in storer the data of the type that should upgrade in describing of configuration only, so can prevent the configuration of the unwanted data in the storer and read unwanted data (describing not data updated) from storer.Therefore can improve the utilization ratio of graphic memory, and can increase the visit that data bus bandwidth is carried out graphic memory, can also improve the overall performance of 3 d graphics system.
(the 6th embodiment)
In the present embodiment, provided the situation that the memory access system of the 3rd embodiment is applied to the access graphics storer.Fig. 9 is the structural drawing that expression is applicable to the graphic memory of the 6th embodiment.Among Fig. 9, stored a plurality of data set DGi in three-dimensional picture storer 43, above-mentioned a plurality of data set DGi comprise data more than the type in 9 categorical datas polygonal each summit that definition is made of above-mentioned X, Y, Z, U, V, R, G, B and α using.In the case, 68 pairs of contents of reading from ROM63 of processing controls portion are carried out graphics process.
Here, the situation that has replaced the ROM63 shown in Figure 5 among the 3rd embodiment with the three-dimensional picture storer 43 among Fig. 9 is described.At first, read the Data Labels information D F of start address 3 and the desirable more than one data type of expression from the processor and controller 73 outputs of desire visit three-dimensional picture storer 43.Read start address 3 and the Data Labels information D F that supply with from processor and controller 73 are the information of reading usefulness behind the more than one categorical data that decision should be upgraded in describing three-dimensional picture storer 43.As mentioned above, be under the situation of 9 information " 110000000 " at Data Labels information D F, everybody is corresponding one by one with the type that defines above-mentioned necessary each data in polygonal summit.The data of the type that in the case, represent the data of desirable type, promptly should upgrade in describing are X (x coordinate figure) and Y (y coordinate figure).Therefore, X (x coordinate figure) and the Y (y coordinate figure) after only will upgrading supplies with processor and controller 73 1 sides continuously.
In addition, in the frame memory that in three-dimensional picture is handled, frequently uses etc., dispose the data that are called the type of frequent variations in the describing of coordinate data/depth data in the past, disposed in the describing of the data of expression color the almost data of indeclinable type simultaneously.Yet, because present embodiment is applied to comprise the memory access system of such storer, thus can be in storer the data of the type that should upgrade in describing of configuration only, can prevent to read unwanted data (describing not data updated) from storer.Therefore can improve the utilization ratio of storer, and can increase data bus bandwidth, only read desirable data from the three-dimensional picture storer at high speed, can improve the overall performance of three-dimensional picture disposal system.
(the 7th embodiment)
The 7th embodiment is described.Figure 10 is the structural drawing of the memory access system of the seventh embodiment of the present invention.System architecture among Figure 10 and compare with Fig. 2, difference is: have data storage control part 31, surrogate data method storage control part 32, and also be supplied to data storage control part 31 from the address 4 of reading of the ROM62 of address generating unit 22 outputs.Other structures among Figure 10 are identical with Fig. 2, and explanation is omitted.
Figure 11 is the address generating unit 22 among Figure 10 and the structured flowchart of data storage control part 31.Identical among the figure among the structure of address generating unit 22 and Fig. 3, explanation is omitted.
The structure of the structure of the data storage control part 31 among Figure 11 and the data storage control part 32 among Fig. 3 is compared, and difference is: data storage control part 31 is provided with the cache memory 20 of temporary transient storage data 16 usefulness the input stage of the data 16 of reading from ROM62.The structure of the data storage control part 32 among other structures of data storage control part 31 and Fig. 3 is identical, and explanation is omitted.
Cache memory 20 is stored the data 16 that are supplied to one by one, simultaneously according to coming assigned address with the data 16 parallel addresses of supplying with 4 of reading.In specify this address, from cache memory 20 sense datas 16.As mentioned above, the data 16 that are read out are stored in the register of the correspondence in the internal register group 77 by the door G1 that the content 15 according to Data Labels information D Fi is switched on, and after this supply with processing controls portion 67 as data 17.
Here, though Data Labels information D Fi reads from ROM62, shown in the 3rd embodiment, also can be the Data Labels information that is stored in processor and controller inside.
In the present embodiment, do not need memory chip to be specified the word length of desirable data from processor and controller one side.In the present embodiment, from the data that ROM62 only reads necessary type selectively continuously, supply with processor and controller 72.
Here, if be example, then can replace ROM62 with graphic memory with the graph data in the 3 d graphics system.In the case, 67 pairs of contents of reading from storer of processing controls portion are carried out graphics process.In the internal configurations of this graphic memory X, Y, Z, R, G, B, U, V and be called α each by 32 data of 9 types that constitute (counting 288).
Under the state with same movement of objects was depicted in situation on the picture, just X or Y changed in describing.Even under these circumstances, in graphics process in the past, need read 9 types all above-mentioned data (data of 288 sizes of meter) from graphic memory.Different therewith, in the present embodiment, only read out in the data (X or Y) (maximum 64) of vicissitudinous type in describing, during describing, can obtain and identical in the past effect, compared with the past from the data volume that graphic memory is read simultaneously, be in the past 2/9.
In the frame memory that in three-dimensional picture, frequently uses etc., dispose the data of the type of frequent variations in the demonstration that is called coordinate data/depth data in the past, disposed the data of the almost indeclinable type of the data of representing color simultaneously.Owing to present embodiment is applied to such frame memory,, can prevents the configuration of the unwanted data in the frame memory and read unwanted data from frame memory so can in this frame memory, only dispose the data of the type that should upgrade.Therefore, can reduce the load about memory access in the three-dimensional picture significantly, the result can improve the overall performance of three-dimensional picture disposal system.
If adopt above-mentioned memory access system, then can and read start address information with the categorical data corresponding with desired information, only read desired information from storer selectively.In other words, can omit reading of gibberish, increase the bandwidth that be equivalent to above-mentioned clipped relevant, and carry out visit at a high speed, and then improve the predetermined process efficient of handling part with memory access.
If adopt above-mentioned memory access system in addition, then can and read start address information with the length data corresponding with desired information, only read desired information from storer selectively.In other words, can omit reading of gibberish, increase the bandwidth that be equivalent to above-mentioned clipped relevant, and carry out visit at a high speed, and then improve the predetermined process efficient of handling part with memory access.
Claims (23)
1. memory access system is characterized in that having: storage part, handling part and address generating unit,
Above-mentioned storage part comprises: the storer of having stored a plurality of information at least; And according to the memory controller of specifying sense information from storer based on the address of reading address information,
In order to read the desired information of storing in the above-mentioned storer, above-mentioned handling part is exported the start address information of reading that the address of reading beginning in the expression above-mentioned storer corresponding with above-mentioned desired information is used at least, the above-mentioned desired information that is read out from the input of above-mentioned storer by above-mentioned memory controller, carry out predetermined process
The generating unit utilization of above-mentioned address represent above-mentioned desired information kind categorical data and from the above-mentioned start address information of reading of above-mentioned handling part output, length according to above-mentioned desired information, the above-mentioned address information of reading that above-mentioned desired information is used is read in generation, exports to above-mentioned memory controller.
2. memory access system according to claim 1 is characterized in that:
Above-mentioned address generating unit has determines the length determination portion used corresponding to the length of the above-mentioned desired information of the above-mentioned type data.
3. memory access system according to claim 2 is characterized in that:
Above-mentioned length determination portion has and each of a plurality of different categorical datas and each tables of data that disposes accordingly of a plurality of length data of representing the length of above-mentioned desired information,
According to the above-mentioned type data that are supplied to above-mentioned address generating unit, from above-mentioned tables of data read with corresponding to the corresponding above-mentioned length data of the above-mentioned desired information of the type data.
4. memory access system according to claim 3 is characterized in that: above-mentioned address generating unit also has address generating unit, address increment portion and stops control part,
Above-mentioned address generating unit takes place and the above-mentioned above-mentioned address information of reading of reading in the corresponding above-mentioned storer of start address information,
Above-mentioned address increment portion imports the above-mentioned address information of reading that above-mentioned address generating unit takes place, and increases progressively back output one by one,
The above-mentioned control part that stops to be according to having judged that according to above-mentioned length data the above-mentioned address information of reading that is increased progressively by above-mentioned address increment portion represents that the situation of reading end of above-mentioned desired information controls, so that above-mentioned address increment portion stops above-mentioned the increasing progressively of address information of reading.
5. memory access system according to claim 1 is characterized in that:
In a plurality of information in the above-mentioned storer each comprises more than one desirable data,
The categorical data of above-mentioned desired information is represented separately dissimilar of the above-mentioned more than one desirable data that comprise in the above-mentioned desired information.
6. memory access system according to claim 1 is characterized in that:
In order to read the above-mentioned desired information of storing in the above-mentioned storer, the above-mentioned type data that above-mentioned handling part also will be corresponding with above-mentioned desired information are exported to above-mentioned address generating unit.
7. memory access system according to claim 1 is characterized in that:
In above-mentioned storer, also stored the above-mentioned type data corresponding to each of above-mentioned a plurality of information,
Above-mentioned memory controller basis is based on specifying with the above-mentioned corresponding above-mentioned address of reading address information of start address information of reading from above-mentioned handling part output, read the above-mentioned type data corresponding from above-mentioned storer, export to above-mentioned address generating unit with above-mentioned desired information.
8. memory access system according to claim 7, it is characterized in that: also have Data Control portion, above-mentioned desired information that the input of this Data Control portion is read from above-mentioned storer and the above-mentioned type data corresponding with this desired information, on one side determine the above-mentioned more than one desirable data kind separately that comprises in this desired information according to the above-mentioned type data, on one side this desired information is exported to above-mentioned handling part.
9. memory access system according to claim 1 is characterized in that: the processing of afore mentioned rules is that the image displaying that rendering image is used is handled,
Each of a plurality of information in the above-mentioned storer is the image definition information that definition institute image represented is used.
10. memory access system according to claim 9 is characterized in that: under the situation that update image is described in above-mentioned image displaying is handled, define the part that this image of information definition should upgrade with above-mentioned image.
11. a memory access system is characterized in that having: storage part, handling part and address generating unit,
Above-mentioned storage part comprises: the storer of having stored a plurality of information at least; And according to the memory controller of specifying sense information from storer based on the address of reading address information,
In order to read the desired information of storing in the above-mentioned storer, the start address information of reading that the address of reading beginning in the above-mentioned storer corresponding with above-mentioned desired information is used is represented in above-mentioned handling part output, import the above-mentioned desired information of reading from above-mentioned storer by above-mentioned memory controller, carry out predetermined process
Length information that the length of above-mentioned desired information is used and the above-mentioned start address information of exporting from above-mentioned handling part of reading are represented in the generating unit utilization of above-mentioned address, read the above-mentioned address information of reading that above-mentioned desired information is used according to above-mentioned length data generation, export to above-mentioned memory controller.
12. memory access system according to claim 11 is characterized in that:
The processing of afore mentioned rules is that the image displaying that rendering image is used is handled,
Each of a plurality of information in the above-mentioned storer is the image definition information that definition institute image represented is used.
13. memory access system according to claim 12 is characterized in that: under the situation that update image is described in above-mentioned image displaying is handled, define the part that this image of information definition should upgrade with above-mentioned image.
14. memory access system according to claim 11 is characterized in that: above-mentioned address generating unit has address generating unit, address increment portion and stops control part,
Above-mentioned address generating unit takes place and the above-mentioned above-mentioned address information of reading of reading in the corresponding above-mentioned storer of start address information,
The input of above-mentioned address increment portion increases progressively back output one by one by the above-mentioned address information of reading that above-mentioned address generating unit takes place,
The above-mentioned control part that stops above-mentionedly being read the situation of reading end that address information is represented above-mentioned desired information according to having judged according to above-mentioned length data by what above-mentioned address increment portion increased progressively, control, so that above-mentioned address increment portion stops above-mentioned the increasing progressively of address information of reading.
15. a memory accessing circuit, it is to supply with the memory accessing circuit that storer is used with read the address that desirable data use from storer, it is characterized in that having: length determination portion and address generating unit,
Above-mentioned length determination portion is accepted the categorical data that the above-mentioned desirable data of decision comprise the data of any type, determines the data length of above-mentioned desirable data, the length data of the above-mentioned data length of output expression,
Above-mentioned address generating unit generates above-mentioned address according to start address and above-mentioned length data, and above-mentioned start address is represented the beginning address of above-mentioned desirable data.
16. memory accessing circuit according to claim 15, it is characterized in that: above-mentioned length determination portion has tables of data, being used for storage representation is stored in a plurality of data of the above-mentioned data length of the data in the above-mentioned storer respectively, above-mentioned tables of data is accepted the above-mentioned type data, and one in above-mentioned a plurality of data is exported as above-mentioned length data.
17. memory accessing circuit according to claim 15 is characterized in that: the above-mentioned type data are stored in the above-mentioned storer, and above-mentioned length determination portion is accepted the above-mentioned type data from above-mentioned storer.
18. memory accessing circuit according to claim 15 is characterized in that: the above-mentioned type data are comprised in the above-mentioned desirable data, and above-mentioned start address represents to store the place of the above-mentioned type data.
19. memory accessing circuit according to claim 15 is characterized in that: above-mentioned address generating unit is carried out the device of predetermined process from utilizing above-mentioned desirable data, accepts above-mentioned start address and the above-mentioned type data.
20. memory accessing circuit according to claim 15 is characterized in that:
Above-mentioned memory accessing circuit also has the data storage control part, and this data storage control part has a plurality of registers, selects one or more register in above-mentioned a plurality of register according to the above-mentioned type data,
Above-mentioned data storage control part is accepted above-mentioned desirable data from above-mentioned storer, and above-mentioned desirable data are write above-mentioned selecteed one or more register according to the type of each data.
21. memory accessing circuit according to claim 20, it is characterized in that: above-mentioned data storage control part has a plurality of doors corresponding with above-mentioned a plurality of registers, each is connected from the register of above-mentioned correspondence and above-mentioned storer and accepts on the common points of above-mentioned desirable data, carries out conducting according to the above-mentioned type data.
22. memory accessing circuit according to claim 20, it is characterized in that: above-mentioned data storage control part have be connected on above-mentioned a plurality of register, storage is from the cache memory of the above-mentioned desirable data of above-mentioned storer output, above-mentioned cache memory output is according to the stored data in above-mentioned address from the output of above-mentioned address generating unit.
23. memory accessing circuit according to claim 15, it is characterized in that: above-mentioned desirable data comprise the 3 D graphic data of at least one in following 9 categorical datas of expression, these 9 categorical datas are: define the x coordinate figure used on polygonal each summit, y coordinate figure, z coordinate figure, about the x coordinate of structural drawing, about y coordinate, red information, green information, the blue information of structural drawing and the alpha information of representing transmissivity, the above-mentioned type data are specified the one or more type of the data that comprise above-mentioned 3 D graphic data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33819999A JP2001154910A (en) | 1999-11-29 | 1999-11-29 | Memory access system |
| JP338199/1999 | 1999-11-29 |
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| Publication Number | Publication Date |
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| CN1298154A true CN1298154A (en) | 2001-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00126428 Pending CN1298154A (en) | 1999-11-29 | 2000-08-31 | Memory reference system for stored data in selective reference to storage |
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| CN (1) | CN1298154A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338600C (en) * | 2003-01-03 | 2007-09-19 | 宇东科技股份有限公司 | Method for reading sensor |
| CN100357912C (en) * | 2003-04-30 | 2007-12-26 | 雅马哈株式会社 | Storage device |
| CN100394403C (en) * | 2006-05-31 | 2008-06-11 | 杭州华三通信技术有限公司 | Limited processor storage access method, system and accessible storage unit |
| US7436760B2 (en) | 2003-08-21 | 2008-10-14 | Transpacific Ip, Llp | Method for reading sensor |
| CN102646452A (en) * | 2011-02-22 | 2012-08-22 | 原相科技股份有限公司 | Programmable memory and writing and reading method thereof |
-
1999
- 1999-11-29 JP JP33819999A patent/JP2001154910A/en not_active Withdrawn
-
2000
- 2000-08-31 CN CN 00126428 patent/CN1298154A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338600C (en) * | 2003-01-03 | 2007-09-19 | 宇东科技股份有限公司 | Method for reading sensor |
| CN100357912C (en) * | 2003-04-30 | 2007-12-26 | 雅马哈株式会社 | Storage device |
| US7436760B2 (en) | 2003-08-21 | 2008-10-14 | Transpacific Ip, Llp | Method for reading sensor |
| CN100394403C (en) * | 2006-05-31 | 2008-06-11 | 杭州华三通信技术有限公司 | Limited processor storage access method, system and accessible storage unit |
| CN102646452A (en) * | 2011-02-22 | 2012-08-22 | 原相科技股份有限公司 | Programmable memory and writing and reading method thereof |
| CN102646452B (en) * | 2011-02-22 | 2016-01-20 | 原相科技股份有限公司 | Programmable storage and write thereof and read method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001154910A (en) | 2001-06-08 |
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