CN102637059A - Time deviation processing device and processing method thereof - Google Patents
Time deviation processing device and processing method thereof Download PDFInfo
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Abstract
The invention discloses a time deviation processing device and a processing method thereof. The device comprises a data sending chip, and a data receiving chip and N data lines, wherein the data receiving chip comprises a sequence control unit, a command generating unit, a delayed control unit, a data grabbing unit and a data comparing unit; the command generating unit sends a command to notice the data sending chip so as to send data, and the delayed control unit comprises N adjustable delay lines; the N data lines and the N adjustable delay lines are correspondingly connected, and the data grabbing unit comprises N latches used for grabbing time delay data; and the N adjustable delay lines and the N latches are correspondingly connected, the data comparing unit comprises N comparators, and the N latches and the N comparators are correspondingly connected. The time deviation processing device provided by the invention can measure time deviation and automatically eliminate the measured time deviation, can measure time deviation in a periodicity manner and automatically eliminate the deviation, is low in cost, and is very suitable for popularization and application.
Description
Technical field
The present invention relates to the time deviation between the multidigit high speed parallel interface between the chip in the communication technology, relate in particular to a kind of time deviation treating apparatus and disposal route thereof.
Background technology
Got into since 21 century, global communications industry is grown up with surprising rapidity, has shown great potential and swift and violent growth momentum, and its development changes the layout of information industry just in the world.Time deviation between the chip between the multidigit high speed parallel interface has significant effects to the development of communicating by letter.Multidigit high speed parallel interface between the chip; As shown in Figure 1, CHIP0 is that data are sent chip, and CHIP1 is the Data Receiving chip; CLOCK is a clock; DATA LINE is the data line of N position, and under the control of clock CLOCK, the N bit data is sent chip (CHIP0) from data and transferred to Data Receiving chip (CHIP1).High-speed DRAM interface (comprising DDR/DDR2/DDR3 etc.) for example, high speed NAND Flash interface, MDDI interface at a high speed or the like.
Life period deviation between each signal of data line DATA (SKEW, the i.e. different and deviation that causes of signal lag), and there are three aspects in the source of this time deviation (SKEW):
Signal sends the time deviation (SKEW) that chip (CHIP0) produces by data, i.e. tSKEW_OUT,
The SKEW that signal is produced by printed circuit board (PrintedCircuitBoard, be called for short PCB), i.e. tSKEW_PCB,
The time deviation (SKEW) that signal is produced by Data Receiving chip (CHIP1), i.e. tSKEW_IN,
The existence of these time deviations (SKEW) causes the valid window of data DATA to diminish, and is as shown in Figure 2.T is the speed cycle of data DATA, and Tskew is the total SKEW between data DATA.For traditional low-rate signal, because T is very big, the influence of Tskew can be left in the basket, and along with the speed lifting of data, the influence of Tskew just can't be left in the basket.For example suppose that Tskew is 0-1ns (how second, part per billion second); When the speed of data was 50Mbps (megabit per second), T was 20ns, and this moment, the valid window of data was 18ns, so can ignore the influence of Tskew; When the speed of data was 500Mbps, T was 2ns, this moment data valid window in addition be 0.This shows that for the high-speed interface data control of time deviation (SKEW) is extremely important.
Multidigit high speed parallel interface in the ideal, data send chip (CHIP0) and send long numeric data constantly one, and through the transmission of long numeric data line, Data Receiving chip (CHIP1) receives long numeric data constantly simultaneously at another.In the application of reality, because time deviation, the moment possibility that Data Receiving chip (CHIP1) receives long numeric data is different.Therefore, need measure and eliminate time deviation, target be to let make the Data Receiving chip receive the long numeric data that data are sent the chip transmission at synchronization as far as possible.
Classic method mainly is to control according to the reason that time deviation (SKEW) produces, and for example in order to reduce tSKEW_PCB, requires all signals to be consistent at the cabling of printed circuit board (pcb) as far as possible.The drawback of the method is the time deviation (SKEW) that will reach enough little, to chip and printed circuit board (pcb) require highly, and can't eliminate the process deviation and the individual deviation of product.
Summary of the invention
The object of the present invention is to provide a kind of time deviation treating apparatus and disposal route thereof, can the Measuring Time deviation and eliminate automatically, and less demanding to chip and printed circuit board (pcb); And when supply voltage and temperature change, can the periodic measurement time deviation and eliminate automatically, cost is low, is highly suitable for promotion and application.
Above-mentioned purpose realizes through following technical proposals:
A kind of time deviation treating apparatus comprises data transmission chip, Data Receiving chip and N position datawire; Said Data Receiving chip comprises timing control unit, order generation unit, time-delay regulon, data placement unit and data comparing unit; Said order generation unit is used for sending order and notifies said data to send chip transmission data, by said timing control unit control; Said time-delay regulon comprises N adjustable delay line, and the delay value of each said adjustable delay line is controlled by said timing control unit; Said N position datawire is connected with N adjustable delay line is corresponding; Said data placement unit comprises N latch, is used to grasp the data after the time-delay, by said timing control unit and clock control; Said N adjustable delay line is connected with N latch is corresponding; Said data comparing unit comprises N comparer, by said timing control unit control; A said N latch is connected with N comparer is corresponding; Said timing control unit, control command generation unit, time-delay regulon, data placement unit and data comparing unit.
Each said adjustable delay line is a K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0;
The deviation processing method of above-mentioned time deviation treating apparatus comprises the measuring method of time deviation, comprises the steps:
The first step: said timing control unit, with sequence number (representing) assignment of effective gating signal of time-delay regulon, m=K-1 with m;
Second step: said timing control unit control time-delay regulon, make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: said timing control unit is controlled said order generation unit, sends order and notifies said data transmission chip to send characteristic and the characteristic correspondence is sent to N comparer;
The 4th step: N latch of said timing control unit control, data are grasped in the back of delaying time, and N time-delay back extracting data correspondence is sent to N comparer;
The 5th step: extracting data and characteristic compared after said each comparer of timing control unit control will be delayed time, and whether record time-delay back extracting data are compared correct with characteristic;
The 6th step: said timing control unit judges whether m is zero;
If m is not equal to zero: then m=m-1 jumped to for second step;
If m equals zero: then carried out for the 7th step: said timing control unit compares K record data of each K level adjustable delay line; Obtain the delay value of each K level adjustable delay line needs according to comparative result, confirm the progression of the delay unit that each K level adjustable delay line need insert and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need insert and be uploaded to timing control unit;
The 8th step: the measuring method of concluding time deviation.
Said time deviation disposal route comprises the removing method of time deviation, and said removing method finishes the back operation in measuring method; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line needs of confirming according to the measuring method of time deviation insert, the progression of the delay unit that N K level adjustable delay line of said timing control unit control inserts;
Second step: said timing control unit is controlled said order generation unit, sends order and notifies said data to send the data that the chip transmission needs transmission;
The 3rd step: N K level adjustable delay line delayed time respectively to data according to the progression of the delay unit of each K level adjustable delay line access;
The 4th step: said timing control unit and clock control data placement unit grasp the data after the time-delay.
Time deviation treating apparatus of the present invention and disposal route thereof can the Measuring Time deviations and eliminate automatically, and less demanding to chip and printed circuit board (pcb); And when supply voltage and temperature change, can the periodic measurement time deviation and eliminate automatically, cost is low, is highly suitable for promotion and application.
Description of drawings
Fig. 1 is the structural representation of multidigit high speed parallel interface between the chip;
Fig. 2 is the synoptic diagram that the existence of time deviation causes the valid window of data to diminish;
Fig. 3 is the synoptic diagram of the Data Receiving chip of time deviation treating apparatus of the present invention;
Fig. 4 is the synoptic diagram of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 5 is a kind of synoptic diagram of delay unit of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 6 is the synoptic diagram of another kind of delay unit of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 7 is the process flow diagram of measuring method of the time deviation of time deviation disposal route of the present invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, time deviation treating apparatus of the present invention and disposal route thereof are further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Embodiment one
Time deviation treating apparatus of the present invention comprises data transmission chip CHIP0, Data Receiving chip CHIP1 and N position datawire DATA LINE, and data are sent chip CHIP0 from data and are transferred to Data Receiving chip CHIP1 through N position datawire DATA LINE; N position datawire DATA LINE uses the 1st position datawire respectively, the 2nd position datawire, and the 3rd position datawire ..., the N position datawire is represented.Time deviation treating apparatus of the present invention comprises the Measuring Time deviation and eliminates time deviation the processing of time deviation.
As shown in Figure 3, said Data Receiving chip CHIP1 comprises timing control unit, order generation unit, time-delay regulon, data placement unit and data comparing unit.
Said order generation unit is used for sending order and notifies said data to send chip CHIP0 transmission data, is controlled by said timing control unit:
In the process of Measuring Time deviation, timing control unit control command generation unit sends the order notification data and sends chip CHIP0 transmission characteristic (this characteristic only is used for the Measuring Time deviation);
In the process of eliminating time deviation, timing control unit control command generation unit sends the order notification data and sends the data that chip CHIP0 transmission needs transmission.
Said time-delay regulon comprises N adjustable delay line, and the delay value of each said adjustable delay line is controlled by said timing control unit.
N adjustable delay line used the 1st adjustable delay line respectively, the 2nd adjustable delay line, and the 3rd adjustable delay line ..., N adjustable delay line represented.The N position datawire is connected with N adjustable delay line is corresponding, and promptly the 1st position datawire is connected with the 1st adjustable delay line, and the 2nd position datawire is connected with the 2nd adjustable delay line ..., the N position datawire is connected with N adjustable delay line.
Said data placement unit comprises N latch, is used to grasp the data after the time-delay, by said timing control unit and clock CLOCK control:
Measuring and eliminating in the process of time deviation, said timing control unit and clock CLOCK control the data after said data placement unit grasps time-delay.If just under clock CLOCK control, the data that said data placement unit grasps after the time-delay had both comprised that valid data also comprised invalid data; Increase said timing control unit and control jointly, select valid data, further handle.
N latch used the 1st latch respectively, the 2nd latch, and the 3rd latch ..., N latch represented.N adjustable delay line is connected with N latch is corresponding, and promptly the 1st adjustable delay line is connected with the 1st latch, and the 2nd adjustable delay line is connected with the 3rd latch ..., N adjustable delay line is connected with N latch.
Said data comparing unit comprises N comparer, by said timing control unit control.
In the process of Measuring Time deviation, whether said data comparing unit will be delayed time, and data are grasped in the back and characteristic compares, and grasp data after the record time-delay and compare correct with characteristic;
In the process of eliminating time deviation, said data comparing unit is uploaded to timing control unit with the delay value that each said adjustable delay line needs.
N comparer used the 1st comparer respectively, the 2nd comparer, and the 3rd comparer ..., N comparer represented.N latch is connected with N comparer is corresponding, and promptly the 1st latch is connected with the 1st comparer, and the 2nd latch is connected with the 2nd comparer ..., N latch is connected with N comparer.
Preferably, the input end of comparer is two; In the process of Measuring Time deviation, the input of comparer is respectively the data after characteristic and the time-delay.
Said timing control unit, the control command generation unit, the time-delay regulon, data placement unit and data comparing unit:
In the process of Measuring Time deviation, said timing control unit control command generation unit, time-delay regulon, data placement unit and data comparing unit; Timing control unit control transfers to the data comparing unit with characteristic.
In the process of eliminating time deviation, said timing control unit control command generation unit, time-delay regulon and data placement unit.
Preferably, said comparer be the D type flip-flop (D type flip-flop, DFF).
Preferably, as shown in Figure 4, each said adjustable delay line is a K level adjustable delay line; Be composed in series by K delay unit (representing) with DLY_CELL; K delay unit (DLY_CELL) used the K delay unit respectively, (K-1) number delay unit, (K-2) number delay unit; ..., No. 1 delay unit is represented; The K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0.
Each delay unit comprises three input ends (use i0 respectively, i1, s representes), 1 output terminal (representing with o) and 1 enable signal end (representing with en).An input end of each delay unit is connected with the signal (representing with i) that needs time-delay, this input end of delay unit is defined as the input end i0 of the signal that needs time-delay; Another input end of each delay unit is connected with gating signal, and this input end of delay unit is defined as gating signal end s; The 3rd input end of delay unit connected with the output terminal o of other delay unit, and this input end of delay unit is defined as series connection end i1; The enable signal end en of each delay unit is connected with enable signal.
The time-delay of each delay unit is Tdelay_cell;
In the gating signal (being K-1) of K delay unit effectively the time, K delay unit access adjustable delay line, the delay value of adjustable delay line is K * Tdelay_cell; The time-delay of promptly data being carried out is K * Tdelay_cell;
In the gating signal (being K-2) of (K-1) number delay unit effectively the time, K-1 delay unit access adjustable delay line, the delay value of adjustable delay line is (K-1) * Tdelay_cell; The time-delay of promptly data being carried out is (K-1) * Tdelay_cell;
Effectively the time, 1 delay unit inserts the adjustable delay line in the gating signal of No. 1 delay unit (promptly 0), and the delay value of adjustable delay line is Tdelay_cell; The time-delay of promptly data being carried out is 1 * Tdelay_cell.
Preferably, as shown in Figure 5, each said delay unit comprises one and door (representing with and), two rejection gates (representing with nor) and one or more time-delay door (representing with buf); A plurality of time-delay door buf series connection.Time-delay Tdelay_cell=2 * Tnor+n * the Tbuf of each delay unit; (Tnor and Tbuf are respectively the gate delay of rejection gate nor and time-delay door buf, and n is the number of time-delay door buf).The number (being the size of n) of Tdelay_cell decision time-delay door buf that can be as required in actual the use.
With two input ends of door and, an input end is as gating signal input end s, and another input end is as the input end i0 of the signal of needs time-delay; With the input as rejection gate nor of the output terminal of door and, the output of an enable signal or a last delay unit is as the input (i.e. series connection end i1) of rejection gate nor; The output of rejection gate nor is as the input of time-delay door buf, and a plurality of time-delay door buf connect; The output of time-delay door buf is as the input of another rejection gate nor, and enable signal is as another input of this rejection gate nor, and the output of this rejection gate nor is as the input of next number delay unit or the output of this adjustable delay line.
When enable signal (en) was low level, the adjustable delay lineman did, and when gating signal input end (s) is high level, selects to pass through.
Preferably, as shown in Figure 6, each said delay unit comprises one or (representing with or), two Sheffer stroke gates (representing with nand) and one or more time-delay door (representing with buf); A plurality of time-delay door buf series connection.Time-delay Tdelay_cell=2 * Tnand+n * the Tbuf of each delay unit; (Tnand and Tbuf are respectively the gate delay of Sheffer stroke gate nand and time-delay door buf, and n is the number of time-delay door buf).The number (being the size of n) of Tdelay_cell decision time-delay door buf that can be as required in actual the use.
Or two input ends of door or, an input end is as gating signal input end s, and another input end is as the input end i0 of the signal of needs time-delay; Or the output terminal of door or is as the input of Sheffer stroke gate nand, and the output of an enable signal or a last delay unit is as the input (i.e. i1 is held in series connection) of Sheffer stroke gate nand; The output of Sheffer stroke gate nand is as the input of a time-delay buf, and the output of time-delay door buf is as the input of another time-delay door buf, and enable signal is as the input of this time-delay door buf, and a plurality of time-delay door buf connect; The output of time-delay door buf is as the input of another Sheffer stroke gate nand, and enable signal is as another input of this Sheffer stroke gate nand, and the output of this Sheffer stroke gate nand is as the input of next number delay unit or the output of this adjustable delay line.
When enable signal (en) was high level, the adjustable delay lineman did, and when gating signal input end (s) is low level, selects to pass through.
Embodiment two
The time deviation disposal route of embodiment one time deviation processing device, said time deviation disposal route comprises the measuring method of time deviation, comprises the steps:
The first step: said timing control unit, sequence number (representing) assignment of effective gating signal of the regulon of will delaying time (being N K level adjustable delay line), m=K-1 with m;
Second step: said timing control unit control time-delay regulon (being N K level adjustable delay line), make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: said timing control unit is controlled said order generation unit, sends order and notifies said data transmission chip to send characteristic and the characteristic correspondence is sent to N comparer;
The 4th step: N latch of said timing control unit control, data are grasped in the back of delaying time, and N time-delay back extracting data correspondence is sent to N comparer;
The 5th step: extracting data and characteristic compared after said each comparer of timing control unit control will be delayed time, and whether record time-delay back extracting data are compared correct with characteristic;
The 6th step: said timing control unit judges whether m is zero;
If m is not equal to zero: then m=m-1 jumped to for second step;
If m equals zero: then carried out for the 7th step: said timing control unit compares K record data of each K level adjustable delay line; According to comparative result (to not right critical point) obtain the delay value that each K level adjustable delay line needs, confirm the progression of the delay unit that each K level adjustable delay line need insert and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need insert and be uploaded to timing control unit;
The 8th step: the measuring method of concluding time deviation.
Explain for example:
N=3, N position datawire are 3 position datawires, are respectively the 1st position datawires, the 2nd position datawire, the 3rd position datawire;
N adjustable delay line is 3 adjustable delay lines, is respectively the 1st adjustable delay line, the 2nd adjustable delay line, the 3rd adjustable delay line;
N latch is 3 latchs, is respectively the 1st latch, the 2nd latch, the 3rd latch;
N comparer is 3 comparers, is respectively the 1st comparer, the 2nd comparer, the 3rd comparer;
K=5; Being that each K level adjustable delay line is 5 grades of adjustable delay lines, comprising 5 delay units, is respectively No. 5 delay units, No. 4 delay units, No. 3 delay units, No. 2 delay units, No. 1 delay unit; The gating signal of 5 delay units is respectively 4,3, and 2,1,0.
In the measuring method of time deviation, for the 1st position datawire:
The first step: said timing control unit, with sequence number (representing) assignment of effective gating signal of the 1st 5 grades of adjustable delay lines, m=K-1=4 with m;
Second step: said timing control unit is controlled the 1st 5 grades of adjustable delay lines, makes the 4th gating signal of the 1st 5 grades of adjustable delay lines effective, and other gating signals are invalid;
The 3rd step: said timing control unit is controlled said order generation unit, sends order and notifies said data transmission chip to send characteristic bit (1) and characteristic bit (1) correspondence is sent to the 1st comparer;
The 4th step: said timing control unit is controlled the 1st latch, grasps data behind the time-delay 5Tdelay_cell, and the extracting data are sent to the 1st comparer behind the 5Tdelay_cell that will delay time;
The 5th step: said timing control unit is controlled the 1st comparer and will delay time and grasp data behind the 5Tdelay_cell and compare with characteristic bit (1), and whether the record extracting data of delaying time behind the 5Tdelay_cell are compared correct with characteristic; The hypothetical record data are not right;
The 6th step: said timing control unit judges whether m is zero;
M is non-vanishing,
M=m-1=3 repeats second and went on foot for the 6th step, grasps data behind the 4Tdelay_cell that wherein delays time; The hypothetical record data are not right;
M is non-vanishing,
M=m-1=2 repeats second and went on foot for the 6th step, grasps data behind the 3Tdelay_cell that wherein delays time; The hypothetical record data are not right;
M is non-vanishing,
M=m-1=1 repeats second and went on foot for the 6th step, grasps data behind the 2Tdelay_cell that wherein delays time; The hypothetical record data are not right;
M is non-vanishing,
M=m-1=0 repeats second and went on foot for the 6th step, grasps data behind the 1Tdelay_cell that wherein delays time; The hypothetical record data are right;
In like manner, simultaneously the 2nd position datawire and the 3rd position datawire are carried out above-mentioned steps.
M equals zero: then carried out for the 7th step:
Represent that with following table 3 position datawires grasp data are compared correctness with characteristic result after different delayed time:
According to comparative result, draw:
For the 1st position datawire:
Said timing control unit compares 5 record data of the 1st 5 grades of adjustable delay lines; According to comparative result (to not right critical point; 1Tdelay_cell promptly delays time; The critical point of time-delay 2Tdelay_cell) obtain: the 1st the delay value 1Tdelay_cell that 5 grades of adjustable delay lines need, the progression of confirming the delay unit that the 1st 5 grades of adjustable delay lines need insert is 1 grade and is uploaded to timing control unit.
For the 2nd position datawire:
Said timing control unit compares 5 record data of the 2nd 5 grades of adjustable delay lines; According to comparative result (to not right critical point; 2Tdelay_cell promptly delays time; The critical point of time-delay 3Tdelay_cell) obtain: the 2nd the delay value 2Tdelay_cell that 5 grades of adjustable delay lines need, the progression of confirming the delay unit that the 2nd 5 grades of adjustable delay lines need insert is 2 grades and is uploaded to timing control unit.
For the 3rd position datawire:
Said timing control unit compares 5 record data of the 3rd 5 grades of adjustable delay lines; According to comparative result (to not right critical point; 4Tdelay_cell promptly delays time; The critical point of time-delay 5Tdelay_cell) obtain: the 3rd the delay value 4Tdelay_cell that 5 grades of adjustable delay lines need, the progression of confirming the delay unit that the 3rd 5 grades of adjustable delay lines need insert is 4 grades and is uploaded to timing control unit.
The 8th step: the measuring method of concluding time deviation.
Said time deviation disposal route comprises the removing method of time deviation, and said removing method finishes the back operation in measuring method; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line needs of confirming according to the measuring method of time deviation insert, the progression of the delay unit that N K level adjustable delay line of said timing control unit control inserts;
Second step: said timing control unit is controlled said order generation unit, sends order and notifies said data to send the data that the chip transmission needs transmission;
The 3rd step: N K level adjustable delay line delayed time respectively to data according to the progression of the delay unit of each K level adjustable delay line access;
The 4th step: said timing control unit and clock CLOCK control data placement unit grasp the data after the time-delay.
In the removing method of time deviation, do not need the data comparing unit.
Preferably, the measuring method cycling service of said time deviation, after the removing method operation once of said time deviation, the removing method operation of time deviation.
Time deviation treating apparatus of the present invention and disposal route thereof can the Measuring Time deviations and eliminate automatically, and less demanding to chip and printed circuit board (pcb); And when supply voltage and temperature change, can the periodic measurement time deviation and eliminate automatically, cost is low, is highly suitable for promotion and application.
Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (12)
1. a time deviation treating apparatus comprises data transmission chip, Data Receiving chip and N position datawire; It is characterized in that:
Said Data Receiving chip comprises timing control unit, order generation unit, time-delay regulon, data placement unit and data comparing unit;
Said order generation unit is used for sending order and notifies said data to send chip transmission data, by said timing control unit control;
Said time-delay regulon comprises N adjustable delay line, and the delay value of each said adjustable delay line is controlled by said timing control unit; Said N position datawire is connected with N adjustable delay line is corresponding;
Said data placement unit comprises N latch, is used to grasp the data after the time-delay, by said timing control unit and clock control; Said N adjustable delay line is connected with N latch is corresponding;
Said data comparing unit comprises N comparer, by said timing control unit control; A said N latch is connected with N comparer is corresponding;
Said timing control unit, control command generation unit, time-delay regulon, data placement unit and data comparing unit.
2. time deviation treating apparatus according to claim 1 is characterized in that:
Each said adjustable delay line is a K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0.
3. time deviation treating apparatus according to claim 1 is characterized in that:
The input end of said comparer is two; In the process of Measuring Time deviation, the input of comparer is respectively the data after characteristic and the time-delay.
4. time deviation treating apparatus according to claim 1 is characterized in that:
Said comparer is the D type flip-flop.
5. time deviation treating apparatus according to claim 2 is characterized in that:
Each said delay unit comprises one and door, two rejection gates and one or more time-delay door; The series connection of a plurality of time-delay door; Time-delay Tdelay_cell=2 * Tnor+n * the Tbuf of each delay unit, wherein, Tnor and Tbuf are respectively the gate delay of rejection gate and time-delay door, and n is the number of time-delay door.
6. time deviation treating apparatus according to claim 2 is characterized in that:
Each said delay unit comprise one or, two Sheffer stroke gates and one or more time-delay door; The series connection of a plurality of time-delay door; Time-delay Tdelay_cell=2 * Tnand+n * the Tbuf of each delay unit, wherein, Tnand and Tbuf are respectively the gate delay of Sheffer stroke gate and time-delay door, and n is the number of time-delay door.
7. time deviation treating apparatus according to claim 1 is characterized in that:
In the process of Measuring Time deviation, said timing control unit control command generation unit sends the order notification data and sends chip transmission characteristic;
In the process of eliminating time deviation, said timing control unit control command generation unit sends the order notification data and sends the data that the chip transmission needs transmission.
8. time deviation treating apparatus according to claim 1 is characterized in that:
In the process of Measuring Time deviation, whether said data comparing unit will be delayed time, and data are grasped in the back and characteristic compares, and grasp data after the record time-delay and compare correct with characteristic;
In the process of eliminating time deviation, said data comparing unit is uploaded to timing control unit with the delay value that each said adjustable delay line needs.
9. time deviation treating apparatus according to claim 1 is characterized in that:
In the process of Measuring Time deviation, said timing control unit control command generation unit, time-delay regulon, data placement unit and data comparing unit; Timing control unit control transfers to the data comparing unit with characteristic;
In the process of eliminating time deviation, said timing control unit control command generation unit, time-delay regulon and data placement unit.
10. the time deviation disposal route of a time deviation treating apparatus, said time deviation treating apparatus comprises:
Comprise data transmission chip, Data Receiving chip and N position datawire; Said Data Receiving chip comprises timing control unit, order generation unit, time-delay regulon, data placement unit and data comparing unit; Said order generation unit is used for sending order and notifies said data to send chip transmission data, by said timing control unit control; Said time-delay regulon comprises N adjustable delay line, and the delay value of each said adjustable delay line is controlled by said timing control unit; Said N position datawire is connected with N adjustable delay line is corresponding; Said data placement unit comprises N latch, is used to grasp the data after the time-delay, by said timing control unit and clock control; Said N adjustable delay line is connected with N latch is corresponding; Said data comparing unit comprises N comparer, by said timing control unit control; A said N latch is connected with N comparer is corresponding; Said timing control unit, control command generation unit, time-delay regulon, data placement unit and data comparing unit;
Each said adjustable delay line is a K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0;
Said time deviation disposal route comprises the measuring method of time deviation, it is characterized in that: comprise the steps:
The first step: said timing control unit, with sequence number (representing) assignment of effective gating signal of time-delay regulon, m=K-1 with m;
Second step: said timing control unit control time-delay regulon, make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: said timing control unit is controlled said order generation unit, sends order and notifies said data transmission chip to send characteristic and the characteristic correspondence is sent to N comparer;
The 4th step: N latch of said timing control unit control, data are grasped in the back of delaying time, and N time-delay back extracting data correspondence is sent to N comparer;
The 5th step: extracting data and characteristic compared after said each comparer of timing control unit control will be delayed time, and whether record time-delay back extracting data are compared correct with characteristic;
The 6th step: said timing control unit judges whether m is zero;
If m is not equal to zero: then m=m-1 jumped to for second step;
If m equals zero: then carried out for the 7th step: said timing control unit compares K record data of each K level adjustable delay line; Obtain the delay value of each K level adjustable delay line needs according to comparative result, confirm the progression of the delay unit that each K level adjustable delay line need insert and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need insert and be uploaded to timing control unit;
The 8th step: the measuring method of concluding time deviation.
11. time deviation disposal route according to claim 10 is characterized in that:
Said time deviation disposal route comprises the removing method of time deviation, and said removing method finishes the back operation in measuring method; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line needs of confirming according to the measuring method of time deviation insert, the progression of the delay unit that N K level adjustable delay line of said timing control unit control inserts;
Second step: said timing control unit is controlled said order generation unit, sends order and notifies said data to send the data that the chip transmission needs transmission;
The 3rd step: N K level adjustable delay line delayed time respectively to data according to the progression of the delay unit of each K level adjustable delay line access;
The 4th step: said timing control unit and clock control data placement unit grasp the data after the time-delay.
12. time deviation disposal route according to claim 11 is characterized in that:
The measuring method cycling service of said time deviation, after the removing method operation once of said time deviation, the removing method operation of time deviation.
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| CN102637059B (en) | 2014-12-10 |
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