CN102623324B - Electrochemical etching of semiconductors - Google Patents

Electrochemical etching of semiconductors Download PDF

Info

Publication number
CN102623324B
CN102623324B CN201110463350.8A CN201110463350A CN102623324B CN 102623324 B CN102623324 B CN 102623324B CN 201110463350 A CN201110463350 A CN 201110463350A CN 102623324 B CN102623324 B CN 102623324B
Authority
CN
China
Prior art keywords
metal
wafer
semiconductor wafer
acid
emission layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110463350.8A
Other languages
Chinese (zh)
Other versions
CN102623324A (en
Inventor
G·哈姆
J·A·里斯
G·R·奥拉德伊斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm and Haas Electronic Materials LLC
Original Assignee
Rohm and Haas Electronic Materials LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm and Haas Electronic Materials LLC filed Critical Rohm and Haas Electronic Materials LLC
Publication of CN102623324A publication Critical patent/CN102623324A/en
Application granted granted Critical
Publication of CN102623324B publication Critical patent/CN102623324B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/32—Anodisation of semiconducting materials
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/12—Etching of semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/12—Electroplating: Baths therefor from solutions of nickel or cobalt
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Semiconductors are electrochemically etched in solutions containing sources of bifluoride and nickel ions. The electrochemical etching may form pores in the surface of the semiconductor in the nanometer range. The etched semiconductor is then nickel plated.

Description

Semi-conductive chemical etching
Cross-reference to related applications
The application is based on U.S. 35U.S.C. § 119 (e) clause, and requiring the applying date is the U.S. Provisional Application No.61/422 on December 13rd, 2010,597 priority, and this application full content is hereby incorporated by.
Technical field
The present invention relates to a kind of semiconductor electrochemistry engraving method.More specifically, the present invention relates to a kind of in order to improve the semiconductor electrochemistry engraving method of metal and semiconductor tack.
Background technology
Semiconductor, for example photovoltaic device and solar cell, metal deposition relate at semi-conductive front and back and form conductive contact piece.Metal coating must be set up ohmic contact with semiconductor to guarantee that electric charge carrier breaks away from semiconductor and enter conductive contact piece and interference-free.In order to reduce as far as possible current loss, metallized contact grid must have enough current conductivity, i.e. high conductivity or sufficiently high conductor path cross section.
Exist multiplely meet above-mentioned condition, for the technique of washing rear surface of solar cell.For example, in order to improve the electric current conduction of rear surface of solar cell, directly strengthen p doping under overleaf.Conventionally use aluminium to realize this purpose.For example, by vapour deposition or printing, aluminium be applied on the back side and driven in the back side or form alloy in overleaf respectively.When washing front or light entrance face, target is to realize the minimum of active semi-conductor surface to block, to use surface as much as possible to catch photon.
Use thick film technology to form the conventional method that metal coating is metallization conductive path.The thickener using comprises metallic, therefore has electrical conductivity.By silk screen, mask, bat printing or thickener, write and apply this thickener.Normally used technique is silk-screen printing technique, and the finger-like washing line of wherein making has the minimum feature of 80 μ m to 100 μ m.Even if such grid width, still obviously and compare with simple metal structure, contact resistance is higher for conductivity loss.This has adverse effect on series resistance, fill factor and solar battery efficiency.This impact strengthens because of less printing conductive path width, and this is to cause the silver metal that applies from thickener still less because reduce live width.Non-conductive oxide between metallic and glass ingredient are the main causes that causes conductivity to decline.
The more complicated technology utilization of preparation front contact laser or photoetching technique to limit conductor path structure.Afterwards, this conductor path that metallizes.Thereby conventionally use various washing steps, to apply metal coating, attempt to realize enough adhesive strengths and the ideal thickness for conductivity.For example, when using wet chemistry metal plating technique, by palladium catalyst, on this current path, deposit the first fine metal coating.This is enhanced by electroless deposition nickel conventionally.In order to improve conductivity, can on nickel, by chemical plating or strike, carry out deposited copper.Afterwards, can use meticulous tin or silver layer to apply this copper to protect it not oxidized.
The tack that is deposited into the plated nickel of semiconductor silicon wafer is mainly subject to the impact of the configuration of surface of this substrate and the internal stress of this clad deposit thing.The tack of nickel and this wafer is also subject to the impact of the stress that the additional coating layer by deposition on this nickel top causes.The significant change along with the difference of manufacturer of the configuration of surface of this semiconductor wafer, and based semiconductor type, for example monocrystalline or polycrystalline and significant change.Under many circumstances, superficial makings can not provide enough sedimental fixing of metal lining, and there is no not receivable attachment loss.A kind of method that solves this attachment issue be after plated nickel immediately this semiconductor wafer of sintering to form nickle silicide.This nickle silicide provide subsequently with copper or silver carry out the required enough bond strengths of metal deposition, keep good tack simultaneously.Yet this need to utilize controlled atmosphere when sintering, and plating operation is divided into two steps, it makes this complicated process of preparation.In addition, due to shunting, there is larger damage diode or the possibility of performance loss.And, increased process time and cost.Therefore, need a kind of method of improving the tack of metal on semiconductor wafer.
Summary of the invention
A method, described method comprises: semiconductor wafer a) is provided, and described semiconductor wafer comprises front, the back side and the PN junction of the emission layer with oxidation; B) this semiconductor wafer is contacted with the composition that comprises one or more bifluoride sources, one or more fluoride salts or its mixture and one or more metal ion sources; C) generation current in said composition; D) apply the anode current of the scheduled time, close subsequently one scheduled time of this anode current, and repeat to form nano porous layer on the emission layer of this circulation with the described oxidation at this semiconductor wafer; And, e) apply cathode current and light with plated metal in this nano porous layer.
Described method also comprises: semiconductor wafer a) is provided, comprises front, the back side and the PN junction of the emission layer with oxidation; B) this semiconductor wafer is contacted with the composition that comprises one or more bifluoride sources, one or more fluoride salts or its mixture; C) generation current in said composition; D) apply the anode current of the scheduled time, close subsequently one scheduled time of this anode current, and repeat to form nano porous layer on the emission layer of this circulation with this oxidation at this semiconductor wafer; E) this semiconductor wafer is contacted with metal deposition solution; And f) generation current in this metal deposition solution, with plated metal in this nano porous layer.
The method forms basic nano porous layer uniformly on the emission layer of this oxidation of semiconductor wafer.This nano porous layer provides the tack of the improvement between this metal deposit and this semiconductor wafer.In addition, this anodic pulse technique that is used to form this nano porous layer can not penetrate the oxidation emission layer of this semiconductor wafer, so that this emitter damages to the degree that has endangered the ohmic contact between this metal level and this semiconductor wafer.Afterwards, metal level subsequently can deposit on this initial metal level and can not cause adhesion failure, has improved thus the reliability that comprises metallized semi-conductive device.In addition, the method can be eliminated the demand of the complex steps to forming metal silicide and relating in silicification technics.
Accompanying drawing explanation
Fig. 1 is the SEM of 170,000 times of silicon single crystal wafer front emission layers, and it uses anodic pulse method to utilize the acidic aqueous solution composition etching of sodium bifluoride take and forms the even porous layer that the degree of depth is 61.2nm.
Fig. 2 is the SEM of 100,000 times of single-crystal wafer front emission layers, and it uses anodic pulse method to utilize the acidic aqueous solution composition etching of sodium bifluoride take and forms the even porous layer that the degree of depth is 104nm.
Fig. 3 is the SEM of 75,000 times of single-crystal wafer front emission layers, and it uses anodic pulse method to utilize the acidic aqueous solution composition etching of sodium bifluoride take and forms the even porous layer that the degree of depth is 80.9nm.
Embodiment
As this specification, use in the whole text, term " deposition " is used interchangeably with " plating ".Term " current path " is used interchangeably with " electric current line ".Term " composition " is used interchangeably with " plating bath ".Prefix " one (kind) " and " be somebody's turn to do " for comprise odd number with plural both.Term " selectivity deposition " means that metal deposition occurs in specific desired zone on substrate.Term " lux=1x ", for illumination unit, equals a lumen/rice 2; And electromagnetism (EM) radiant power under 540 terahertz frequencies of a lux=1.46 milliwatt.Unless have other clearly to indicate in text, abbreviation below has following implication: ℃=degree Celsius; G=gram; ML=milliliter; L=liter; A=ampere; Dm=decimetre; Cm=centimetre; μ m=micron; Nm=nanometer; Min.=minute; Sec.=second: UV=ultraviolet ray; IR=infrared ray; SEM=scanning electron microscopy; And ASTM=Unite States Standard method of testing.Unless all referring to weight, all percentage and ratio have other indications.All scopes include end value can combined in any order, unless clearly the such number range sum of mandatory requirement is 100%.
Photovoltaic device and solar cell can consist of monocrystalline, polycrystalline or amorphous silicon semiconductor wafer.Although only relate to semiconductor silicon wafer in specification below, also can use other suitable semiconductor wafer, for example GaAs, germanium silicon and germanium.When using silicon wafer, it has p-type base (base) doping conventionally.
The shape of this semiconductor wafer can be circle, square or rectangular, or can also be other any suitable shape.Such wafer can have various sizes and surface resistivity.For example, circular wafer can have 150mm, 200mm, 300mm, 400mm or larger diameter.
The back side of wafer is metallized.Can use any traditional method.This whole back side can by washing, for example, be formed grid by the part at washing or the back side.Such back face metalization can provide by multiple technologies, and can before front wafer surface metallization, complete.In one embodiment, metal coating is applied to this back side with the form of conducting paste, for example argentiferous thickener, containing the thickener of aluminium thickener or argentiferous and aluminium; Yet, also can use and comprise for example other thickener of nickel, palladium, copper, zinc or tin of metal.This conducting paste generally includes conducting particles and the organic bond that embeds glass matrix.Conducting paste can be applied on wafer by multiple technologies, for example, by silk screen printing, apply.After applying thickener, it removes this organic bond through firing (fire).When using the conducting paste that contains aluminium, diffuse into the back side of this wafer aluminum portions, if or also comprise silver in the thickener using, may form alloy with silver.Use this thickener containing aluminium can improve contact resistance and " p+ " doped region is provided.By applying in advance aluminium or boron and phase counterdiffusion subsequently, prepare heavy doping " p+ " type district.In one embodiment, can, before applying back metal coating, to this back side, apply containing aluminium thickener and fire.Optionally, before applying back metal coating, remove from the residue containing aluminium thickener of firing.In another embodiment, can be at the backside deposition inculating crystal layer of wafer, and on this inculating crystal layer by chemical plating or metallide plated metal coating.
The front of this wafer optionally experiences crystalline orientation texture etching so that this surface has the light incident geometry of the improvement that has reduced reflection, for example, form pyramidal structure.In order to manufacture semiconductor junction, at this front wafer surface, carry out phosphorus diffusion or Implantation with preparation n doping (n+ or n++) district and the wafer with PN junction is provided.This n doped region is called emission layer.This emission layer can be homogeneous emission layer or selectivity emission layer.Homogeneous emission layer has uniform concentration of dopant or sheet resistance conventionally.Selectivity emission layer has kinds of surface resistance value.Conventionally, the district of current path is set, sheet resistance is lower or have higher doping, and antireflecting coating district has higher resistance or overlapping low doping.Because the higher-doped of current path and be conducive to the formation of nano-porous structure compared with low resistance tendency, therefore preferred selectivity emission layer.
On the front of this wafer or emission layer, set up anti-reflecting layer.In addition, this anti-reflecting layer can be used as passivation layer.Suitable anti-reflecting layer includes but not limited to, silicon oxide layer is SiO for example x, silicon-nitride layer Si for example 3n 4, the combination of Si oxide and silicon-nitride layer and silicon oxide layer, silicon-nitride layer and titanium oxide layer TiO for example xcombination.In aforementioned chemical formula, x is oxygen atomicity.Such anti-reflecting layer can deposit by multiple technologies, for example, by various CVD (Chemical Vapor Deposition) method, as chemical vapour deposition (CVD) and physical vapour deposition (PVD).
The front of wafer comprises metallization pattern.For example, the front of wafer can comprise current collection line and current bus bar.Current collection line is usually located at the horizontal direction of bus and conventionally with respect to current bus bar, has relatively meticulous structure (being size).
In one embodiment, front or the emission layer of this wafer are coated with anti-reflecting layer, for example silicon nitride.Afterwards, in this front, limit opening or pattern.This pattern runs through this anti-reflecting layer to expose the surface of the semiconductor body of this wafer.Alternatively, can in opening, form through this wafer surface and enter the dark groove of 1-100 μ m in the semiconductor body of this wafer.Also can adopt darker or more shallow gash depth.Can use kinds of processes to form this pattern, such as but not limited to, laser ablation, mechanical system and photoetching process, all these are known in the prior art.Such mechanical system comprises sawing (sawing) and scraping (scratching).The surface that normal light carving technology is included in wafer arranges can image forming material (imageable maerial), patterning this can image forming material to form opening in this anti-reflecting layer, by this design transfer to this wafer, in this opening depositing metal layers and remove this can image forming material.In one embodiment, in opening, removing this before depositing metal layers step can image forming material.In another embodiment, in opening, after depositing metal layers step, removing this can image forming material.When in this metal deposition step process, this can image forming material exists, such any dyestuff of can image forming material conventionally avoiding absorbing the radiation wavelength using in metal deposition step process, for example contrast dyestuff (contrast dyes).What in plating step process, exist can contain dyestuff by image forming material conventionally, and this dyestuff has the minimum optical transmission rate of 40-60%.
When this can image forming material be liquid, such material can be set to by any suitable technology the surface of this wafer, such as but not limited to spin coating, ink jet printing, curtain coating and roller, applies.When this can image forming material be dry film, such material can be set in this wafer surface by vacuum lamination.
By this can be exposed to actinic radiation and can carry out patterning by image forming material to this via a mask by image forming material.According to selected, specificly can choose actinic radiation by image forming material.Can use laser and other traditional actinic radiation sources can carry out patterning by image forming material to this.
This pattern in can image forming material is transferred in this semiconductor wafer substrate subsequently.Can use wet chemical etch technology or use dry etching technology to carry out this design transfer.Suitable dry etching technology includes but not limited to, plasma etching, for example reactive ion etching.This pattern forms by the lines of the relative narrower sectional dimension as current collection line with as the lines of the relatively thick sectional dimension of bus conventionally.This bus is positioned at the horizontal of this current collection line.
Can use any suitable polymer remover to remove this can image forming material, and this remover is for example to be sold by ROHM AND HAAS electronic material company (Ma Er Greensboro, Massachusetts (Marlborough, Massachusetts)).Such remover can be alkalescence, acidity or substantially neutral.
Form the expose portion of this semiconductor wafer of pattern oxidized with recover clean arbitrarily before or processed wafer process in any original oxide (native oxide) of being removed.Can use conventional oxidant to recover this original oxide.Oxidation is used the aqueous hydrogen peroxide solution of 1-3wt% to complete conventionally.Other oxidant comprises but is not limited to, the aqueous solution of hypochlorite, persulfate, peroxy acid and permanganate.When this semiconductor wafer is monocrystalline, this oxidizing solution normally pH is greater than 7 or the alkaline solution of 8-12 for example.When this semiconductor wafer is silicon, at part formation one deck SiO of this exposure x.Conventionally this semiconductor wafer is immersed in the flowing process chamber that comprises oxidizing solution or processes by this chamber.Can also its naturally-occurring be oxidized by this semiconductor wafer being exposed to ambiance.
Afterwards, the expose portion of this semiconductor wafer of etching or pattern to form nano porous layer on the emission layer of this oxidation, adopt subsequently electrochemical etching and metal deposition composition to carry out metal deposition, said composition comprises one or more bifluoride sources, one or more fluoride salts or its mixture and one or more metal ion sources.Therefore, said composition comprises etching component and metal deposition component simultaneously.In another embodiment, by composition independently, complete the etching of using one or more bifluoride sources, fluoride salt or its mixture to carry out, use subsequently the wafer after this etching of metal deposition composition metal deposition independently.Can use traditional metal deposition composition.
Bifluoride source compound includes but not limited to, alkali-metal bifluoride is sodium bifluoride and potassium bifluoride for example, the quaternary salt of ammonium fluoride, ammonium acid fluoride, borofluoride, fluoboric acid, fluorine stannane, fluorine antimony hydride, tetrafluoro boric acid tetrabutylammonium, six aluminum fluorides and aliphatic amine, aromatic amine and nitrogen-containing heterocycle compound.Fluoride salt includes but not limited to, alkali metal fluoride is the fluoride of sodium and potassium for example.Conventionally bifluoride source compound and the content of fluoride salt in composition are 5g/L to 100g/L or for example 10g/L to 70g/L or for example 20g/L to 50g/L.
The acid that can comprise in composition includes but not limited to, sulfamic acid, and alkane sulfonic acid is Loprazolam, ethane sulfonic acid and propane sulfonic acid for example; Alcohol sulfonic acid; Aryl sulfonic acid is toluene aryl sulfonic acid, benzene sulfonic acid and phenolsulfonic acid for example, contains for example sulfamic acid of amino sulfonic acid; Inorganic acid is sulfuric acid, nitric acid and hydrochloric acid for example; Amino acid, carboxylic acid comprise single, double and tricarboxylic acids, their ester, acid amides and any unreacted acid anhydride.In addition, said composition can comprise sour mixture.When said composition comprises two or more carboxylic acids, at least one comprises that acid proton is to form bifluoride kind.Conventionally can obtain such acid from multiple commercial source, for example aldrich chemical company (Aldrich Chemical Company).Conventionally, the acid that electrochemical composition comprises and anhydride content are 1g/L to 300g/L, or 10g/L to 200g/L for example, or 30g/L to 100g/L for example.
By combination, by one or more acid of chemical dose proportioning, prepare this electrochemical composition with one or more bifluoride source compounds or one or more fluoride salts or its mixture.Stir until bifluoride component or fluoride salt are dissolved in acid.Can further add water mixes to dissolve any undissolved component.
Selectively, once add one or more acid anhydrides in the aqueous solution at least one bifluoride source, to contact with water, just form at least one carboxylic acid.Suppose that the enough acid anhydrides that adopt by stoichiometric can obtain the water content of 1-5wt%, exist one or more carboxylic acids in the bifluoride source compound aqueous solution.Afterwards, mix said composition until acid anhydrides hydrolysis and bifluoride source compound dissolve.Can add extra water further mixes until all components all dissolves.
Conventionally electrochemical composition comprises one or more alkali metal fluosilicate hydride, ammonium fluoride and ammonium acid fluoride as bifluoride source compound.More commonly, bifluoride source compound is for example bifluoride of sodium and potassium of alkali metal fluosilicate hydride.When bifluoride source compound is alkali metal fluosilicate hydride, at electrochemical composition, comprise one or more inorganic acids, for example sulfamic acid.When bifluoride source compound is ammonium acid fluoride or ammonium fluoride, in this electrochemical composition, comprise one or more carboxylic acids.Generally include monocarboxylic acid, for example acetic acid.
Can use various metals plating inculating crystal layer on nanoporous emission layer; Yet conventional metal is nickel and alloy, palladium and closes gold, silver and alloy and cobalt and alloy thereof.More common metal is nickel or palladium.More typical metal is nickel.Conventionally use nickel salt that nickel ion is provided.Such nickel compound includes but not limited to, nickelous sulfate, nickel chloride, nickelous bromide, nickel sulfamic acid and nickel phosphate.Can use the mixture of nickel compound.By using palladium compound, be generally palladium salt and palladium ion is provided.Such palladium salt includes but not limited to, palladium bichloride, palladium nitrate, palladium bichloride sodium, palladium bichloride potassium, tetrachloro-palladium potassium chlorate and chlorination tetramino palladium (tatraamine palladium chloride).Can use the mixture of palladium compound.Use silver compound that silver ion is provided.Such silver compound includes but not limited to, silver nitrate, silver oxide, silver potassium cyanide, silver thiosulfate and methane silver sulfate.Use cobalt compound that cobalt ions is provided.Cobalt compound includes but not limited to, cobalt chloride, cobaltous bromide, cobaltous sulfate, cobalt potassium cyanide, ammonium cobaltous sulfate and cobalt acetate.Should comprise the metallic compound of enough content so that the concentration of metal ions amount providing is 0.1 to 150g/L, be generally 0.5 to 100g/L, and be more typically 1 to 70g/L.
Optionally, in electrochemical composition, can use diversified surfactant.It can use any anion, cationic, both sexes and non-ionic surfactant, as long as can not disturb the performance of etching or metal deposition.The surfactant that can comprise customary amount.
Optionally, this electrochemical composition comprises one or more annexing ingredients.Such annexing ingredient includes but not limited to, brightener, grain refiner and ductility reinforcing agent.Such annexing ingredient is known in the art, and dosage is used routinely.
This electrochemical composition optionally comprises buffer.Exemplary buffer includes but not limited to, borate buffer (for example borax), PB, citrate buffer agent, carbonate buffer agent and hydroxide buffer.The PH that the consumption of this cushion using is enough to keep this electrochemical composition at 1-6, be generally the desirable level of 1-2.
This semiconductor wafer immerses and is contained in the described electrochemical composition in chemically inert etching and electroplating pool.The working temperature of this electrochemical composition can be 10-100 ℃, or as 20-50 ℃.Apply back side electromotive force (rectifier) to this semiconductor wafer.One inertia is dipped in this etching electroplating pool equally to electrode.Conventionally this is platinum line or silk screen electrode to electrode.This etching electroplating pool, semiconductor wafer, electrochemical composition and rectifier are electrically connected each other.
In this electrochemical composition with on semiconductor wafer, produce anode potential and continue a scheduled time, one scheduled time of cut-off current repeat this enough number of times that circulates so that nano porous layer to be uniformly provided on the oxidation emission layer in this semiconductor wafer front substantially subsequently, and anode potential makes it can not damage this semi-conductive electrical property through the surface of this oxidation emission layer simultaneously.The method penetrates to form substantially uniformly nanoporous emission layer and can make metal deposition cause and semiconductor wafer has between good adhesion and the sheet resistance of ohmic contact and obtains balance at emission layer.In addition, the method obtains balance minimizing to corrode or damage the antireflecting coating on emission layer and form between nanoporous emission layer simultaneously.The oxidized portion of this emission layer is made for to nanoporous form until a certain degree of depth, so as metal well attached to this emission layer and simultaneously the resistivity of emission layer there is enough conductibility with metal lining.It is darker that this nano porous layer enters this emission layer, and the surface resistivity of this emission layer is larger.Conventionally, this substantially uniformly nano porous layer to enter this emission layer enough dark, to make this emission layer sheet resistance, with respect to the emission layer surface resistivity before applying this anode potential, increase 5% to 40%, or for example 20% to 30%.Conventionally, the surface resistivity of this even porous emission layer be 200 Europe/square or lower.For example the factor of emission layer thickness and dopant profiles is also the parameter that will consider when determining the emission layer nanoporous degree of depth and emission layer resistivity.Can carry out a small amount of test and determine this emission layer nanoporous degree of depth and emission layer resistivity, to realize the metal deposition of particular semiconductor die, adhere to good metal.
Conventionally, apply anode potential during current density can be at 0.01A/dm 2to 2A/dm 2in scope, or 0.05A/dm for example 2to 1A/dm 2.Yet, can carry out a small amount of test determining preferred current density setting for particular semiconductor die, apply time cycle of anode potential and shutoff.Such parameter depends on the ideal thickness of the thickness of this semiconductor wafer and the original depth of emission layer and nanoporous emission layer.If the nanoporous of this emission layer part is too dark, may damage this semiconductor so that its sheet resistance increases.Too high sheet resistance can be damaged the conductivity that is formed on the current path in this emission layer nanoporous part.In addition, the lip-deep non-homogeneous nano porous layer of this emission layer causes the poor adhesive force of the metal level of plating subsequently.Conventionally apply anode potential 0.5 second and longer, or for example 0.5 second to 2 seconds, or for example 3 seconds to 8 seconds.The time stopping at cyclic process Anodic electromotive force can be 1 second and larger scope, or for example 3 seconds to 10 seconds, or for example 10 seconds to 50 seconds.Amount of cycles can be in 5 to 80 scope, or 10 to 100 scope for example.
If the semiconductor wafer of this patterning is silicon solar cell, this light source for example can be, fluorescence or LED lamp, and its energy providing is in the wave-length coverage of described silicon solar cell photovoltaic sensitivity.Can use various other light sources, such as but not limited to, incandescent lamp is 75 watts and 250 watts of lamps, mercury lamp, Halogen lamp LED and 150 watts of infrared lamps for example.This luminous energy can be continuous or pulse.For example can realize pulsing light by using mechanical chopper to interrupt this light, or can, based on ideal period, use electronic device light source to be provided to the periodical energy of interruption.The light quantity that is applied to semiconductor wafer in normal light induction plating process can be 400lx to 10,000lx, or 500lx to 7500lx for example.
By using luminous energy to illuminate the front of this semiconductor wafer, in this front, there is plating.The luminous energy irradiating has produced electric current in this semiconductor wafer.Other parameter of knowing by adjusting this luminous intensity, electroplating bath temperature, initial wafer condition, doped level and those skilled in the art, can control this positive plating speed.For semiconductor wafer, 100nm and metal seed layer thicker or for example thickness of 100nm to 2 μ m are normally desirable, and this accurate thickness depends on many factors, for example application, semiconductor dimensions, pattern and geometry.
In another embodiment, being used to form the etching component of nanoporous emission layer and this metal deposition formula can be included in independently in solution.This wafer is put into etching solution, in this etching solution, process wafer to form substantially nanoporous emission layer uniformly, transferred to afterwards independently metal deposition solution and carry out metal deposition.If it is oxidized to recover original oxide that this wafer needs, before etching, be oxidized this wafer.In another replaces execution mode, can in a kind of composition, merge this etching component and this oxidation component, the while is this metal of plating in solution independently.After the positive oxidation of this semiconductor, to this semiconductor wafer, apply anode potential as previously mentioned, this electromotive force be from the pulse of anode to 0 with the oxidized portion of this semiconductor emission layer of etching optionally, thereby form uniform nano porous layer substantially.In this embodiment, use bifluoride compound source, fluoride salt and acid as hereinbefore, and consumption is also identical.In addition, use oxidant and consumption as hereinbefore identical.
Afterwards, by photoinduction metal, be deposited on this uniform plated metal inculating crystal layer optionally in nano porous layer substantially, be generally the metal seed layer of nickel, palladium, cobalt or silver.As previously mentioned, back side electromotive force (rectifier) is applied on this semiconductor wafer.Light can be for continuous or pulse.As previously mentioned, this semiconductor is dipped in metal deposition composition and by light and is applied on this semiconductor.
Can use conventional electrolytic metal composition.Typical current density is 0.01A/dm 2to 2A/dm 2, s or for example 0.05A/dm 2to 1A/dm 2.Specific electric current demand depends on the concrete size of this used wafer.The electroplating technology using is conventional.Suitable electrolytic metal electroplating bath can business obtains, can be also in document published those.The NIKAL that example Wei Cong Rohm And Haas Electronic Mater of the electrolytic nickel electroplating bath being purchased obtains tMand NICKEL GLEAM tMthe nickel electrowinning product of series.The example of the electrolytic nickel electroplating bath that other is suitable is US3, disclosed Watts type plating bath in 041,255.
After aforementioned embodiments metal lining inculating crystal layer, can be on this metal seed layer one or more additional metal layer of plating.Such additional metal layer can be copper or silver.Can use conventional metal electric plating bath.If additional metal is copper, can be on this copper deposit tin pre-plating layer (tin strike layer) in case oxidation.If additional metal is silver, can be on this silver depositing silver pre-plating layer (silver strike layer) and deposit subsequently an additional silver layer on this pre-plating layer.Such additional metal layer can be by being used chemical plating, immersion, electrolysis, the photoinduction metal deposition of conventional electroplating bath and technique to deposit.Conventionally, such metal level scope is at 1 μ m to 50 μ m, more specifically, and from 5 μ m to 25 μ m.Pre-plating layer scope is at 0.25 μ m to 2 μ m.If this additional metal layer of electrolytic deposition, current density is 0.1A/dm conventionally 2to 3A/dm 2, and conventionally from 1A/dm 2to 3A/dm 2.Total electric current demand depends on used particular wafer size.
Such source metal for additional metal layer can include but not limited to, metal halide, and metal nitrate, metal carboxylate is acetate, metal formate and metal gluconate for example, and metal-amino acid compound is metal cysteine compound for example; Metal alkyl sulfonate is metal methane sulfonates and metal ethane sulfonate for example; Metal hydramine sulfonate, metal toluene fulfonate and metal phenolate sulfonate; And metal cyanides.When this metal is silver, this slaine is not silver halide conventionally, and this is because the dissolubility of these chlorination silver salt is limited.The embodiment of copper compound includes but not limited to, cupric pyrophosphate, copper gluconate, copper sulphate and copper chloride.The embodiment of tin compound includes but not limited to, stannic chloride, STANNOUS SULPHATE CRYSTALLINE and tin methane sulfonate.Can use the mixture of metallic compound.Such mixture can be to have same metal but the metallic compound of different compounds, for example the mixture of silver nitrate and silver-colored cysteine compound.
Conventionally the metallic compound that adds q.s to electroplating bath to provide 0.1 to 150g/L concentration of metal ions in coating composition.When metal ion is silver ion, the common content of concentration of silver ions in electroplating bath is 2 to 40g/L.Such metallic compound can be purchased from multiple source conventionally, for example the aldrich chemical company of Milwaukee, the state of Wisconsin.The plating bath example being purchased is COPPER GLEAM tMsT 901 and 901A copper electroplating bath and ENLIGHT tMsilver Plate 620 silver medal electroplating baths, by the ROHM AND HAAS electronic material Co., Ltd acquisition of Massachusetts Ma Er Greensboro.The tin plating bath example being purchased is SOLDERON tMtin electroplating composition and byproduct, also can be obtained by ROHM AND HAAS electronic material.
In metal electroplating solution, can use diversified conventional surfactants.Can use anion, in cationic, both sexes and non-ionic surfactant any.The surfactant that can comprise conventional amount used.
This metal electric plating bath can comprise one or more additional conventional components.Such annexing ingredient includes but not limited to, electrolyte, buffer, brightener, grain refiner, huge legendary turtle and agent, complexant, reducing agent, levelling agent and ductility reinforcing agent.Such annexing ingredient is as known in the art and consumption use routinely.
The method forms substantially nano porous layer uniformly on the emission layer surface in semiconductor wafer front.This nano porous layer provides the tack of improvement between this metal deposit and this semiconductor wafer.In addition, the technique that is used for forming this nano porous layer can not penetrate the emission layer of this semiconductor wafer so that damage this emitter, causes damaging the ohmic contact between this nickel inculating crystal layer and this semiconductor wafer.Afterwards, can on metal seed layer, deposit metal level subsequently and needn't worry adhesion failure, therefore improve the reliability that comprises the semi-conductive device that metallizes.In addition, the method has been eliminated the complex steps relating in the needs of formation metal silicide and silicification technics.
Specifically with reference to the silicon wafer for solar cell, this electrochemical etching method has been described; Yet, by for example changing in the rational necessity aspect adopted energy of light source, the photovoltaic device that also can use other material outside silica removal to prepare.
The following examples that comprise are for various aspects of the present invention are described, but not intention limits the scope of the invention.
Embodiment
Embodiment 1
The doped single crystal silicon wafer in its front with pyramidal protuberance is provided.This wafer has n+ doped region on the front of this wafer that forms emission layer.This wafer also has the PN junction below this emission layer.The front surface coated of this wafer has by SiN xthe anti-reflecting layer forming.The front of this wafer has the pattern for current path, and this pattern, through this anti-reflecting layer, exposes the surface of this silicon wafer.Every current path is across the whole length of this wafer.Those current paths are in one end of this wafer and the center of this wafer and busbar combination.The back side of this wafer is p+ doping and comprises aluminium electrode.
This wafer immerses the hydrofluoric acid solution of 1wt% to clean this current path and bus.At room temperature carry out the cleaning of a minute.Water rinses this wafer.Except removing pollutant from wafer, this hydrofluoric acid solution has also removed original oxide from the surface of emission layer.
Afterwards, the silicon single crystal wafer of this doping is immersed in and comprises ENLIGHT tMin the electroplating pool of 1300 nickel sulfamic acid electroplate liquids.The aluminium electrode of this chip back surface is connected on rectifier, and solid nickel anode as plating with in to electrode.This wafer is anode as negative electrode and this nickel.This plating is with, wafer and electrode is all electrically connected to, and applies 1A/dm 2cathode current continue one minute.At whole plating, in the cycle, to this wafer, apply artificial light rays.This light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is from 30 ℃ to 50 ℃.On this current path and this bus, deposit the nickel inculating crystal layer of 300nm.
Afterwards, this wafer is put into and comprises COPPER GLEAM tMthe metallide pond of 125 cathode copper electroplating baths (can obtain from ROHM AND HAAS electronic material).The aluminium electrode of this chip back surface be connected to rectifier and phosphorus-copper anode as in plating bath to electrode.This wafer is as negative electrode.This plating bath, wafer and electrode is all electrically connected to, and apply 1.5A/dm 2cathode current continue 14 minutes to deposit the copper layer of 6-10 μ m on the nickel inculating crystal layer on each current path and bus.In whole plating, again to this wafer, apply artificial light rays.This light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is from 20 ℃ to 50 ℃.
From this electroplating pool, take out this wafer, and detect the tack of this metal level and this current path and bus.Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.Although the metal level on bus does not peel off, the whole metal levels on current path all peel off from wafer.Tack between nickel and silicon wafer interface is defective.
Embodiment 2
Except electrosilvering on nickel inculating crystal layer but not copper, repeat the method for describing above in embodiment 1.Use ENLIGHT tMsilver Plate 620 silver medal electroplating bath plate silver.Current density is 1.5A/dm 2and plating finishes for 10 minutes.In whole plating, also artificial light rays is applied on this wafer.Light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is 20 ℃ to 40 ℃.On this nickel, deposit the silver layer of 8-10 μ m.
Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.On whole current paths and bus, between this nickel and this silicon wafer, the tack at interface is defective.
Embodiment 3
Provide and the single-crystal wafer of embodiment 1 same type above.This wafer is placed on metal plating support, and this back aluminium electrode directly contacts with this metal plating support.Along this battery of circumferential sealing of this wafer and the interface between this support, to reduce as far as possible the solution infiltration between this cell backside and plating rack.In anode circulation, the electric current of rectifier flows through this support and enters this battery by this back side contact.
Afterwards, use the aqueous hydrogen peroxide solution of 5wt% to be oxidized this current path and bus, oxidized to guarantee this silicon face.Afterwards, by being contained in the waterborne compositions in the wafer immersion plating pond on support of recording in earlier paragraphs, said composition comprises the sulfamic acid from the nickel ion of the 10g/L of sulfamic acid nickel salt, the sodium bifluoride of 45g/L and 15g/L.Should be connected to rectifier with the support of wafer, and platinum line is used as to electrode.This waterborne compositions, wafer and platinum line are electrically connected to each other.On this wafer, applying current density is 0.2A/dm 2anode current reach 30 seconds.This waterborne compositions is room temperature.
In etching this current path and bus with after forming substantially uniformly nano porous layer, to this wafer, apply artificial light rays and the polarity of this rectifier that reverses, so that this battery is negative electrode and this platinum electrode is anode.This light source is the Halogen lamp LED of 250 watts.Current density remains on 0.1A/dm 2, and the nickel inculating crystal layer of plating 100nm-500nm on the current path after this etching and bus.Continue to complete for 30 seconds this photoinduction plating.
Afterwards, nickel plating wafer is placed into the metallide pond that comprises ENLIGHT 420 cathode copper electroplating baths (can obtain from ROHM AND HAAS electronic material).The aluminium electrode of this chip back surface is connected to rectifier, and copper anode as in plating bath to electrode.This wafer is anode as negative electrode and this platinum line.This plating bath, wafer and electrode is all electrically connected to, and apply 2A/dm 2cathode current reach 14 minutes to deposit the copper layer of 6-10 μ m on the nickel inculating crystal layer at each current path and bus.In plating process, again to this wafer, apply artificial light rays.This light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is 20 ℃ to 50 ℃.
From this electroplating pool, take out this wafer and detect this metal level and the tack of this current path and bus.Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.Even if at the interface of nickel and silicon, also without any metal, be positioned at tangible proof on adhesive tape or metal level separated any sign from this wafer.
Embodiment 4
Except plate silver on nickel inculating crystal layer but not copper, repeat the method for describing above in embodiment 3.Use has the ENLIGHT that concentration of silver ions is 1g/L tMsilver-colored preplating electroplate liquid plate silver on nickel of Silver Plate 620 electroplating baths, is used ENLIGHT subsequently tMsilver Plate 620 electroplating baths are plating silver layer on this silver preplating thing.In this pre-plating liquor, apply 2 to the 2.5V voltages of 30 seconds to 1 minute, afterwards immediately by this wafer transfer in another silver-colored plating bath, here with 2A/dm 2plating 10 minutes.Artificial light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is 20 ℃ to 40 ℃.On this nickel, deposit the silver layer of 8-10 μ m.
Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.All metal deposits on this current path and bus all keep perfect.Even if at the interface of nickel and silicon, also without any metal, be positioned at tangible proof on adhesive tape or metal level separated any sign from this wafer.
Embodiment 5
By with embodiment 1 in the single-crystal wafer of the same type described according to the description of embodiment 3, shelve.
Afterwards, by the waterborne compositions in this wafer immersion plating groove, the sodium bifluoride that it comprises 15g/L and the sulfamic acid of 30g/L.Should be connected to rectifier with the support of wafer, and platinum line is used as to electrode.This waterborne compositions, wafer and platinum line are all electrically connected to each other.Said composition is by agitation as appropriate and keep room temperature.At first, under 1.2V, to this wafer, apply 0.1A/dm 2anode current continue two seconds, turn-off afterwards this electric current 1 second.The current impulse that repeats this anode to 0 reaches 30 cycles.This current path of etching and bus, with after forming substantially uniformly nanoporous emission layer, take out this battery and use rinsed with deionized water from this waterborne compositions.
The silicon single crystal wafer of this doping is shelved, afterwards its immersion is comprised to ENLIGHT tMin the electroplating pool of 1300 electrolytic nickel electroplating chemical preparations.This support with wafer is connected to rectifier, solid nickel anode as in this plating bath to electrode.This wafer is as negative electrode.This plating bath, wafer and electrode is all electrically connected to, and apply 1A/dm 2cathode current continue 1 minute.In the whole plating cycle, to this wafer, apply artificial light rays.This light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is 30 ℃ to 50 ℃.Continue plating until deposit the nickel inculating crystal layer of 300nm on this current path and bus.
Afterwards, nickel plating wafer is placed in the metallide pond that comprises ENLIGHT 420 cathode copper electroplating baths.Support with wafer is connected to rectifier, and copper anode as in electrobath to electrode.This plating bath, wafer and electrode is all electrically connected to, and apply 2A/dm 2cathode current reach 14 minutes to deposit the copper layer of 6-10 μ m on the nickel inculating crystal layer on each current path and bus.In plating process, again to this wafer, apply artificial light rays.This light source is 250 watts of Halogen lamp LEDs.Plating temperature scope is 20 ℃ to 50 ℃.
From this electroplating pool, take out this wafer and detect this metal level and the tack of this current path and bus.Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.Although the metal level on bus is not peeled off, peel off from this wafer in some the scattered regions on this current path.The position that adhesion failure occurs is the interface between this nickel and this wafer silicon.
Embodiment 6
Except the number of times of porous rectification circulation is increased to 45 from 30, repeat the method for this embodiment 5.All other preparations are all identical with condition.
From this electroplating pool, take out this wafer and detect this metal level and the tack of this current path and bus.Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.All metal deposits on this current path and bus all keep perfect.Even if at the interface of nickel and silicon, also without any metal, be positioned at tangible proof on adhesive tape or metal level separated any sign from this wafer.
Embodiment 7
Except the number of times of porous rectification circulation is increased to 60 from 30, repeat the method for this embodiment 5.All other preparations are all identical with condition.
From this electroplating pool, take out this wafer and detect this metal level and the tack of this current path and bus.Use the tape test of ASTM D3359-97 standard rubber to detect the tack of this metal level.All metal deposits on this current path and bus all keep perfect.Even if at the interface of nickel and silicon, also without any metal, be positioned at tangible proof on adhesive tape or metal level separated any sign from this wafer.
Embodiment 8
Method in repetition embodiment 5 until form this porous silicon layer in etching solution.
Afterwards, use AMRAY 1910 secondary electron microscope to check this emission layer.On the surface of the pyramidal structure of this emission layer, formed substantially nano porous layer uniformly.Fig. 1 is 170,000 times of SEM figure of a pyramidal body structure surface.As shown in Figure 1 and illustrated in rectangle frame, on the surface of the pyramidal structure of this emission layer, having formed the degree of depth is the nano porous layer in 61.2nm (upper left corner of square frame is to the lower right corner).The height of the width of this square frame through being measured as 42.9nm (from left to right) and this square frame is through being measured as 43.7nm (from top to bottom).
Embodiment 9
Method in repetition embodiment 7 until form this porous silicon layer in etching solution.
In addition, before forming, use nano-pore the Model HM20 of Jiade Engineering Co., Ltd (Jandel Engineering Ltd.) to record the sheet resistance (ρ of this emission layer 0) be 17 ohm-sq.Except the current impulse of this anode current to 0 completes 60 circulations, by technique as hereinbefore, complete the formation of this nano-pore.After nano-pore forms, measure the sheet resistance (ρ of this emission layer 1) and determine that it is 23 ohm-sq.This emission layer sheet resistance has increased by 6 ohm-sq or 39%, and carry out the scope of metal deposition on nanoporous emission layer surface within, so that the metal level of plating has good tack on this emission layer.
Afterwards, use AMRAY 1910 secondary electron microscope to check this emission layer.On the surface of the pyramidal structure of this emission layer, formed substantially nano porous layer uniformly.Fig. 2 is 100,000 times of SEM figure of a pyramidal body structure surface.As shown in Figure 2, and illustrated in rectangle frame, on the surface of the pyramidal structure of this emission layer, having formed the degree of depth is the nano porous layer in 104nm (upper left corner of square frame is to the lower right corner).The height of the width of this square frame through being measured as 55.7nm (from left to right) and this square frame is through being measured as 88.3nm (from top to bottom).
Embodiment 10
Method in repetition embodiment 6 until form this porous silicon layer in etching solution.
Except the current impulse of this anode current to 0 completes 45 circulations, by technique as hereinbefore, complete the formation of this nano-pore.Afterwards, use AMRAY 1910 secondary electron microscope to check this emission layer.On the pyramidal body structure surface of this emission layer, formed uniform nano porous layer substantially.Fig. 3 is 75,000 times of SEM figure of a pyramidal body structure surface.As shown in Figure 3, and illustrated in rectangle frame, on the surface of the pyramidal structure of this emission layer, having formed the degree of depth is the nano porous layer in 80.9nm (upper left corner of square frame is to the lower right corner).The height of the width of this square frame through being measured as 43.2nm (from left to right) and this square frame is through being measured as 68.4nm (from top to bottom).

Claims (10)

1. improve a method for the tack of metal on semiconductor wafer, described method comprises:
A) provide semiconductor wafer, described semiconductor wafer comprises front, the back side and the PN junction of the emission layer that comprises oxidation;
B) this semiconductor wafer is contacted with composition, said composition comprises one or more bifluoride sources, one or more fluoride salts or its mixture and one or more metal ion sources;
C) generation current in said composition;
D) apply the anode current of the scheduled time, close subsequently one period of scheduled time of this anode current, and repeat to form nano porous layer on the emission layer of this circulation with the oxidation at this semiconductor wafer; And
E) apply cathode current and light with plated metal in this nano porous layer.
2. the method in claim 1, it is characterized in that, described bifluoride source is selected from the quaternary salt of alkali-metal bifluoride, ammonium fluoride, ammonium acid fluoride, borofluoride, fluoboric acid, fluorine stannane, fluorine antimony hydride, tetrafluoro boric acid tetrabutylammonium, six aluminum fluorides and aliphatic amine, aromatic amine and nitrogen-containing heterocycle compound.
3. the method in claim 1, further comprises the acid that is selected from sulfamic acid, sulfonic acid, inorganic acid, amino acid and carboxylic acid one or more.
4. the method in claim 1, is characterized in that, described metal ion is nickel ion, palladium ion, cobalt ions or silver ion.
5. the method for claim 1, is characterized in that, described metal is nickel, palladium, cobalt or silver.
6. improve a method for the tack of metal on semiconductor wafer, described method comprises:
A) provide semiconductor wafer, described semiconductor wafer comprises front, the back side and the PN junction of the emission layer that comprises oxidation;
B) this semiconductor wafer is contacted with composition, said composition comprises one or more bifluoride sources, one or more fluoride Yanyuans or their mixture;
C) generation current in said composition;
D) apply the anode current of the scheduled time, close subsequently one period of scheduled time of this anode current, and repeat to form nano porous layer on the emission layer of this circulation with the oxidation at this semiconductor wafer; And
E) this semiconductor wafer is contacted with metal deposition solution; And
F) in this metal deposition solution generation current with plated metal on this nanoporous emission layer.
7. the method for claim 6, is characterized in that, described metal is nickel.
8. the method for claim 7, is further included in deposited copper or silver on described nickel.
9. the method for claim 8, further comprises the tin preplating thing that deposits described copper.
10. the method for claim 8, is further included in depositing silver preplating thing on described silver.
CN201110463350.8A 2010-12-13 2011-12-13 Electrochemical etching of semiconductors Expired - Fee Related CN102623324B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42259710P 2010-12-13 2010-12-13
US61/422,597 2010-12-13

Publications (2)

Publication Number Publication Date
CN102623324A CN102623324A (en) 2012-08-01
CN102623324B true CN102623324B (en) 2014-12-10

Family

ID=45497721

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110463350.8A Expired - Fee Related CN102623324B (en) 2010-12-13 2011-12-13 Electrochemical etching of semiconductors

Country Status (7)

Country Link
US (2) US8603314B2 (en)
EP (1) EP2463410B1 (en)
JP (1) JP5868155B2 (en)
KR (1) KR20120065958A (en)
CN (1) CN102623324B (en)
SG (1) SG182081A1 (en)
TW (1) TWI493615B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8969122B2 (en) 2011-06-14 2015-03-03 International Business Machines Corporation Processes for uniform metal semiconductor alloy formation for front side contact metallization and photovoltaic device formed therefrom
CN105408241B (en) * 2013-03-15 2019-01-11 哈佛大学校长及研究员协会 Nano-pore is generated in atom level film by supershort electric pulse
JP6545585B2 (en) 2014-10-16 2019-07-17 株式会社荏原製作所 Substrate holder and plating apparatus
WO2017112880A1 (en) * 2015-12-22 2017-06-29 William Marsh Rice University Formation of porous silicon materials with copper-containing pores
JP6859150B2 (en) * 2017-03-22 2021-04-14 株式会社荏原製作所 How to determine the plating equipment and plating tank configuration
EP3438330B1 (en) * 2017-08-03 2024-04-17 Groz-Beckert KG Textile machine component and method for producing a textile tool
CN110148581B (en) * 2018-02-10 2022-05-17 姜富帅 Metallization process and method of metal-semiconductor
CN109770438B (en) * 2019-03-25 2023-07-25 云南中烟工业有限责任公司 Film-coated silicon-based electronic cigarette atomization chip and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1436879A (en) * 2003-02-27 2003-08-20 复旦大学 Prepn of porous liminescent material
WO2007058603A1 (en) * 2005-11-18 2007-05-24 Replisaurus Technologies Ab Method of forming a multilayer structure
CN101055900A (en) * 2006-04-10 2007-10-17 上海太阳能科技有限公司 Silicon solar battery
WO2009113874A2 (en) * 2008-03-14 2009-09-17 Norut Narvik As Method for texturing silicon surfaces and wafers thereof
CN101673785A (en) * 2009-09-25 2010-03-17 上海大学 Method for preparing reflection reduction film with surface embedded type porous silicon structure of silicon base solar battery

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3041255A (en) 1960-03-22 1962-06-26 Metal & Thermit Corp Electrodeposition of bright nickel
US3607480A (en) * 1968-12-30 1971-09-21 Texas Instruments Inc Process for etching composite layered structures including a layer of fluoride-etchable silicon nitride and a layer of silicon dioxide
US4369099A (en) * 1981-01-08 1983-01-18 Bell Telephone Laboratories, Incorporated Photoelectrochemical etching of semiconductors
JPS5884965A (en) * 1981-11-13 1983-05-21 モ−ビル・ソラ−・エナ−ジ−・コ−ポレ−ション Nickel plating method
GB8515532D0 (en) 1985-06-19 1985-07-24 Standard Telephones Cables Ltd Surface alloys treatment
JPH0613366A (en) * 1992-04-03 1994-01-21 Internatl Business Mach Corp <Ibm> Method and system for performing immersion scanning for forming porous silicon film and device
US5543333A (en) 1993-09-30 1996-08-06 Siemens Solar Gmbh Method for manufacturing a solar cell having combined metallization
US5599520A (en) 1994-11-03 1997-02-04 Garces; Juan M. Synthesis of crystalline porous solids in ammonia
US6277662B1 (en) * 1999-06-03 2001-08-21 Seiichi Nagata Silicon substrate and forming method thereof
EP1132952B1 (en) * 2000-03-10 2016-11-23 Imec Method for the formation and lift-off of porous silicon layers
JP3530149B2 (en) * 2001-05-21 2004-05-24 新光電気工業株式会社 Wiring board manufacturing method and semiconductor device
US6787450B2 (en) 2002-05-29 2004-09-07 Micron Technology, Inc. High aspect ratio fill method and resulting structure
US7400395B2 (en) 2002-06-12 2008-07-15 Intel Corporation Metal coated nanocrystalline silicon as an active surface enhanced raman spectroscopy (SERS) substrate
US7192860B2 (en) * 2002-06-20 2007-03-20 Honeywell International Inc. Highly selective silicon oxide etching compositions
TW200505975A (en) 2003-04-18 2005-02-16 Ekc Technology Inc Aqueous fluoride compositions for cleaning semiconductor devices
EP1644558B1 (en) * 2003-05-12 2019-04-03 Arkema Inc. High purity electrolytic sulfonic acid solutions
US7407689B2 (en) * 2003-06-26 2008-08-05 Atotech Deutschland Gmbh Aqueous acidic immersion plating solutions and methods for plating on aluminum and aluminum alloys
JP2005105409A (en) * 2003-09-08 2005-04-21 Rikogaku Shinkokai Method for manufacturing porous silicon structure and method for manufacturing metal-carrying porous silicon
US7368045B2 (en) * 2005-01-27 2008-05-06 International Business Machines Corporation Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow
US20070256937A1 (en) * 2006-05-04 2007-11-08 International Business Machines Corporation Apparatus and method for electrochemical processing of thin films on resistive substrates
US20090139868A1 (en) * 2007-12-03 2009-06-04 Palo Alto Research Center Incorporated Method of Forming Conductive Lines and Similar Features
US20090196999A1 (en) * 2007-12-12 2009-08-06 Rohm And Haas Electronic Materials Llc Adhesion promotion
TWI351771B (en) * 2007-12-31 2011-11-01 Sino American Silicon Prod Inc Solar cell
US20090188553A1 (en) * 2008-01-25 2009-07-30 Emat Technology, Llc Methods of fabricating solar-cell structures and resulting solar-cell structures
TW200952184A (en) * 2008-06-03 2009-12-16 Univ Nat Taiwan Structure of mixed type heterojunction thin film solar cells and its manufacturing method
TWI473312B (en) * 2008-06-06 2015-02-11 Dc Solar Corp A large area flexible dye-sensitized solar cell and the electrochemical fabricating method thereof
EP2141750B1 (en) * 2008-07-02 2013-10-16 Rohm and Haas Electronic Materials LLC Method of light induced plating on semiconductors
CN102105999A (en) * 2008-07-28 2011-06-22 达伊4能量有限公司 Crystalline silicon pv cell with selective emitter produced with low temperature precision etch back and passivation process
EP2157209B1 (en) * 2008-07-31 2014-10-22 Rohm and Haas Electronic Materials LLC Inhibiting Background Plating
US8003164B2 (en) * 2008-09-19 2011-08-23 Guardian Industries Corp. Method of making a scratch-and etch-resistant coated glass article
JP2012511100A (en) 2008-12-08 2012-05-17 ユニバーシティ オブ サウス オーストラリア Formation of nanoporous materials
US8906218B2 (en) * 2010-05-05 2014-12-09 Solexel, Inc. Apparatus and methods for uniformly forming porous semiconductor on a substrate
US8329046B2 (en) 2009-02-05 2012-12-11 Asia Union Electronic Chemical Corporation Methods for damage etch and texturing of silicon single crystal substrates
DE102009008152A1 (en) * 2009-02-09 2010-08-19 Nb Technologies Gmbh Silicon solar cell
BRPI1007989A2 (en) * 2009-02-25 2016-03-01 Avantor Performance Mat Inc multipurpose acid organic solvent based microelectronic cleaning composition
WO2011053736A1 (en) * 2009-10-30 2011-05-05 Rice University Structured silicon battery anodes
JP5734734B2 (en) * 2010-05-18 2015-06-17 ローム アンド ハース エレクトロニック マテリアルズ エルエルシーＲｏｈｍ ａｎｄ Ｈａａｓ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌｓ ＬＬＣ Method for forming current tracks on a semiconductor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1436879A (en) * 2003-02-27 2003-08-20 复旦大学 Prepn of porous liminescent material
WO2007058603A1 (en) * 2005-11-18 2007-05-24 Replisaurus Technologies Ab Method of forming a multilayer structure
CN101055900A (en) * 2006-04-10 2007-10-17 上海太阳能科技有限公司 Silicon solar battery
WO2009113874A2 (en) * 2008-03-14 2009-09-17 Norut Narvik As Method for texturing silicon surfaces and wafers thereof
CN101673785A (en) * 2009-09-25 2010-03-17 上海大学 Method for preparing reflection reduction film with surface embedded type porous silicon structure of silicon base solar battery

Also Published As

Publication number Publication date
EP2463410A3 (en) 2016-11-16
SG182081A1 (en) 2012-07-30
JP5868155B2 (en) 2016-02-24
US8603314B2 (en) 2013-12-10
TW201246352A (en) 2012-11-16
CN102623324A (en) 2012-08-01
KR20120065958A (en) 2012-06-21
TWI493615B (en) 2015-07-21
EP2463410B1 (en) 2018-07-04
US9076657B2 (en) 2015-07-07
US20130288476A1 (en) 2013-10-31
JP2012126999A (en) 2012-07-05
US20120184098A1 (en) 2012-07-19
EP2463410A2 (en) 2012-06-13

Similar Documents

Publication Publication Date Title
CN102623324B (en) Electrochemical etching of semiconductors
KR101578035B1 (en) Method of light induced plating on semiconductors
JP5996244B2 (en) Copper plating on semiconductors
CN101257059B (en) Method for electrochemical depositing solar cell metallic electrode
TWI481743B (en) Light induced plating of metals on silicon photovoltaic cells
TWI575118B (en) Metal plating for ph sensitve applications
US9783901B2 (en) Electroplating of metals on conductive oxide substrates
KR20130091290A (en) Activation process to improve metal adhesion
TWI490376B (en) High speed copper plating process
TW201019491A (en) Method for producing metal electrodes on solar cells through electroplating

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20141210

Termination date: 20201213