CN102607615A - Gain self-compensating method for linear array CCD (Charge-coupled Device) pixel level signal and compensating circuit - Google Patents
Gain self-compensating method for linear array CCD (Charge-coupled Device) pixel level signal and compensating circuit Download PDFInfo
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Abstract
The invention provides a gain self-compensating method for a linear array CCD (charge-coupled device) pixel level signal and a gain self-compensating compensating circuit, which are applied to planarization processing for an output signal in a space low-coherence-interference demodulating system. The hardware part of the demodulating system comprises a CPLD (complex programmable logic device) control circuit, a linear array CCD, a gain self-compensating circuit, an amplifying filter circuit and a data acquisition circuit, wherein the gain self-compensating circuit consists of a digital potentiometer, an operational amplifier, analog switches (S1 and S2) and resistors (R1 and R2) and is used for dynamically controlling the signal gain of a linear array CCD. In demodulation, the CPLD control circuit outputs a driving clock of the linear array CCD and outputs a synchronous clock signal to the gain self-compensating circuit at the same time, the CPLD control circuit controls the resistance regulation for the analog switches and the digital potentiometer synchronously in each pixel period, and the CPLD control circuit can change the gain of the operational amplifier according to a preset gain parameter form, so as to realize the independent fine regulation of the gain of each pixel signal. According to the method, the affection to the low-coherence-interference demodulating precision caused by non-uniform illumination can be effectively reduced.
Description
Technical field
The present invention relates to line array CCD output signal Processing field; Be specifically related to a kind of line array CCD pixel level signal gain method of self compensation and circuit and realized, made it be applicable to low coherence interference sensory field and spectrophotometric spectra analysis fields such as pressure, temperature, stress and displacement.
Background technology
Low coherence interference is the common method of high-acruracy survey absolute displacement, and the demodulating equipment that wherein adopts wedge to accomplish the optical path difference spacescan can obtain high precision and stable measurement, and it need receive the low coherence interference striped through the CCD device.Usually in the low coherence interference system; The light that light source sends is not even distribution, and the center is strong and a little less than the both sides, the illumination that therefore arrives on the line array CCD face is also inhomogeneous; The low coherence interference striped that contains displacement information on the even background signal of uneven illumination along with the conversion generation translation of measurand; Therefore the low coherence interference striped drops on the signal contrast difference that different illumination zone forms, and signal to noise ratio (S/N ratio) is different, thereby influences the demodulation accuracy of system.
The aanalogvoltage of line array CCD sensor output and incident light illumination, frame transfer frequency are relevant, and increase along with the increase of incident light illumination, reduce along with the increase of frame transfer frequency.Regulating the ccd output signal voltage method at present has two kinds, and a kind of is to shine illumination through regulating exterior light, and another kind is the timing up of adjustment CCD.The method of wherein regulating exterior light photograph illumination is through regulating light source power; Change the illumination illumination that CCD accepts; Thereby realize regulating the aanalogvoltage of ccd output signal, this method receives light source and the inhomogeneity restriction of light path system illumination patterns, can't carry out the meticulous adjustment of pixel level.The method of adjustment CCD timing up is the integral time through adjustment CCD; Make CCD photosensitive unit stored charge; Thereby change the aanalogvoltage of ccd output signal; But receive the restriction of CCD transfering clock frequency, driving circuit dominant frequency, can only put in order the adjustment of frame, can not accomplish meticulous adjustment by pixel to the ccd output signal gain.
Summary of the invention
The objective of the invention is to overcome the deficiency of said method, the method for self compensation of the line array CCD pixel level signal gain in a kind of spatial mode low coherence interference demodulating system is provided.Illumination according to each pixel of line array CCD is regulated its dynamic gain; Obtain stronger signal output, feasible pixel to different illumination zone can both utilize the dynamic range of CCD fully, strengthens the contrast of local signal; Observe the details of regional area, improve the precision of demodulating system.
Line array CCD pixel level signal gain method of self compensation provided by the invention is that hardware components is provided with the gain self-compensation circuit in demodulating system.
The demodulating system hardware components is as shown in Figure 2, comprises CPLD control circuit, line array CCD, amplification filtering circuit and data acquisition circuit, and the gain self-compensation circuit is connected between line array CCD and the amplification filtering circuit.Transfering clock, drive clock and the reset clock of CPLD control circuit output line array CCD; Export the synchronous reset clock signal simultaneously to the gain self-compensation circuit; Controlling the first analog switch S1, the second analog switch S2 and digital regulation resistance resistance in each pixel cycle synchronisation regulates; According to preset gain parameter form; Dynamically change the gain of operational amplification circuit in the gain self-compensation circuit, realize the meticulous adjustment of independence of each pixel signal gain.
Line array CCD pixel level signal gain self-compensation circuit is made up of operational amplifier, digital regulation resistance, the first analog switch S1, the second analog switch S2 and first resistance R 1 and second resistance R 2 in the spatial mode low coherence interference demodulating system provided by the invention.
The positive input end grounding of operational amplifier, inverting input is connected to the Linear Array CCD Signal output terminal through first resistance R 1; Be connected the negative-feedback circuit that is made up of two parallel branches between the inverting input of operational amplifier and the output terminal, wherein one the tunnel is the series arm of the first analog switch S1 and digital regulation resistance R; Another road is the series arm of the second analog switch S2 and second resistance R 2, forms the negative-feedback circuit of operational amplification circuit with this.
Line array CCD pixel level signal gain method of self compensation provided by the invention is:
1st, before demodulating system started, default conditions were made as the first analog switch S1 and break off, and the second analog switch S2 is closed.
2nd, system start-up; The output signal of line array CCD is received the input end of above-mentioned gain self-compensation circuit; Startup along with demodulator circuit; Transfering clock, drive clock and the reset clock of the CPLD control circuit output line array CCD of demodulating system, the synchronous reset of CPLD control circuit output simultaneously clock is given the first analog switch S1 and the second analog switch S2.
3rd, line array CCD begins to export the pixel signal under the effect of each road clock, and the pixel signal is divided into reset signal and two parts of useful signal by the time, and the reset signal voltage of the different pixel outputs of line array CCD is identical; Useful signal is different; When reset clock was high level, line array CCD resetted and exports reset signal, and the first analog switch S1 breaks off; The second analog switch S2 is closed, and second resistance R 2 is linked into operational amplification circuit.
4th, the CPLD resistance of regulating digital regulation resistance R according to predefined gain parameter form, the adjusting time is less than line array CCD reset time, guarantees that line array CCD exports before effective pixel signal, and digital regulation resistance reaches steady state (SS).When reset clock is low level, line array CCD output useful signal, the first analog switch S1 is closed; The second analog switch S2 breaks off, and digital regulation resistance is linked into operational amplification circuit, effectively pixel signal gain adjustment; The reset clock low level finishes, and begins the adjustment of next pixel signal.
Line array CCD pixel output signal and reset clock are synchronous; CPLD output synchronous reset clock signal is to the gain self-compensation circuit; Control the resistance of first analog switch (S1), second analog switch (S2) and digital regulation resistance (R) regulates in each pixel cycle synchronisation; Gain parameter form according to preset dynamically changes the gain of operational amplification circuit, realizes the meticulous adjustment of independence of each pixel signal gain.
Line array CCD pixel level signal gain self-compensation circuit separates adjustment to the reset signal and the useful signal of line array CCD output.The line array CCD reset signal adopts the amplification of unified gain, guarantees that each pixel useful signal base voltage is identical, and the line array CCD useful signal carries out by pixel gain adjustment, when reset clock is high level, and line array CCD output reset signal voltage V
I1, through gain self-compensation circuit output signal voltage V
O1,
In the formula: R
1Be the resistance of first resistance (R1), R
2It is the resistance of second resistance (R2);
When reset clock was low level, line array CCD was exported effective pixel signal voltage V
I2, through gain self-compensation circuit output signal voltage V
O2,
In the formula: R
1Be the resistance of first resistance (R1), R is the resistance according to the adjusted digital regulation resistance of gain parameter form.Thereby accomplish line array CCD pixel gain per stage compensation, make the pixel in different illumination zone can both utilize the dynamic range of CCD fully, strengthen the contrast of local signal, observe the details of regional area, improve the precision of demodulating system.
Advantage of the present invention and beneficial effect:
The line array CCD pixel level signal gain self-compensation circuit of spatial mode low coherence interference (FBG) demodulator is realized the meticulous adjustment of independence of each pixel signal gain, can effectively improve the even influence to the low coherence interference demodulation accuracy of uneven illumination.
Description of drawings
Fig. 1 is the demodulating equipment block diagram of the spatial mode low coherence interference system of Fabry-perot optical fiber sensing.
Fig. 2 is a spatial mode low coherence interference system demodulator circuit structural drawing.
Fig. 3 is the schematic diagram of line array CCD pixel gain per stage self-compensation circuit.
Fig. 4 is a spatial mode low coherence interference system background signal graph.
The signal graph that Fig. 5 does not collect through gain compensation for spatial mode low coherence interference system.
Fig. 6 passes through the signal graph of the line array CCD that collects after the gain compensation circuit for spatial mode low coherence interference system.
Among the figure, 1 wideband light source, 2 photo-couplers, 3 fibre-optical F-P sensors, 4 self-focusing collimation lenses, 5 wedges, 6 line array CCD devices.
Embodiment
Embodiment:
Accompanying drawing 1 is the low coherence interference demodulating system installation drawing that detects based on line array CCD that the inventive method relates to, and the measurement in conjunction with external atmospheric pressure describes this method.
The light that wideband light source 1 sends incides fibre-optical F-P sensor 3 through photo-coupler 2, and from the light generation approximate Double beam interference that two end faces of sensor 3 are launched, optical path difference is the long twice in F-P chamber, and the chamber personal attendant ambient atmosphere pressure and is linear change.The light signal of modulated mistake is derived from the outlet of photo-coupler 2, forms the light pencil outgoing of concentration of energy through self-focusing collimation lens 4.This light pencil sees through the scanning that wedge 5 is accomplished optical path difference, finally projects to line array CCD 6, and effective pixel number of line array CCD 6 is 3000.Wedge 5 forms optical path scannings, when the optical path difference that the optical path difference that causes when wedge 5 and sensor 3 cause is complementary, and the generation low coherence interference striped at line array CCD 6 corresponding local pixel places.
The demodulator circuit structure of low coherence interference demodulating system is shown in accompanying drawing 2; Demodulator circuit comprises CPLD control circuit, line array CCD, gain self-compensation circuit, amplification filtering circuit and digital collection circuit, and the gain self-compensation circuit is connected between line array CCD and the amplification filtering circuit.Wherein control circuit CPLD exports transfering clock (TCLK), drive clock (CRx) and reset clock (RS) to line array CCD, and the synchronous reset of CPLD output simultaneously clock is to the gain self-compensation circuit.Control the first analog switch S1 and the second analog switch S2 in each pixel cycle synchronisation, and, dynamically change the gain of gain self-compensation circuit, realize the gain adjustment of pixel level signal according to the resistance that predefined gain parameter form is regulated digital regulation resistance.
Accompanying drawing 3 is schematic diagrams of line array CCD gain self-compensation circuit.Comprising an operational amplifier, digital regulation resistance, the first analog switch S1, the second analog switch S2 and first resistance R 1 and second resistance R 2.
The positive input end grounding of operational amplifier, inverting input is connected to the Linear Array CCD Signal output terminal through first resistance R 1; Be connected the negative-feedback circuit that is made up of two parallel branches between the inverting input of operational amplifier and the output terminal, wherein one the tunnel is the series arm of the first analog switch S1 and digital regulation resistance R; Another road is the series arm of the second analog switch S2 and second resistance R 2, forms the negative-feedback circuit of operational amplification circuit with this.
Line array CCD pixel level signal gain method of self compensation provided by the invention is:
1st, before demodulating system started, default conditions were made as the first analog switch S1 and break off, and the second analog switch S2 is closed.
2nd, system start-up; The output signal of line array CCD is received the input end of above-mentioned gain self-compensation circuit; Startup along with demodulator circuit; Transfering clock, drive clock and the reset clock of the CPLD control circuit output line array CCD of demodulating system, the synchronous reset of CPLD control circuit output simultaneously clock is given the first analog switch S1 and the second analog switch S2.
3rd, line array CCD begins to export the pixel signal under the effect of each road clock, and the pixel signal is divided into reset signal and two parts of useful signal by the time, and the reset signal voltage of the different pixel outputs of line array CCD is identical; Useful signal is different; When reset clock was high level, line array CCD resetted and exports reset signal, and the first analog switch S1 breaks off; The second analog switch S2 is closed, and second resistance R 2 is linked into operational amplification circuit.
4th, the CPLD resistance of regulating digital regulation resistance R according to predefined gain parameter form, the adjusting time is less than line array CCD reset time, guarantees that line array CCD exports before effective pixel signal, and digital regulation resistance reaches steady state (SS).When reset clock is low level, line array CCD output useful signal, the first analog switch S1 is closed; The second analog switch S2 breaks off, and digital regulation resistance is linked into operational amplification circuit, effectively pixel signal gain adjustment; The reset clock low level finishes, and begins the adjustment of next pixel signal.
Line array CCD pixel output signal and reset clock are synchronous; CPLD output synchronous reset clock signal is to the gain self-compensation circuit; Control the resistance of first analog switch (S1), second analog switch (S2) and digital regulation resistance (R) regulates in each pixel cycle synchronisation; Gain parameter form according to preset dynamically changes the gain of operational amplification circuit, realizes the meticulous adjustment of independence of each pixel signal gain.
Line array CCD pixel level signal gain self-compensation circuit separates adjustment to the reset signal and the useful signal of line array CCD output.The line array CCD reset signal adopts the amplification of unified gain, guarantees that each pixel useful signal base voltage is identical, and the line array CCD useful signal carries out by pixel gain adjustment, when reset clock is high level, and line array CCD output reset signal voltage V
I1, through gain self-compensation circuit output signal voltage V
O1,
In the formula: R
1Be the resistance of first resistance (R1), R
2It is the resistance of second resistance (R2);
When reset clock was low level, line array CCD was exported effective pixel signal voltage V
I2, through gain self-compensation circuit output signal voltage V
O2,
In the formula: R
1Be the resistance of first resistance (R1), R is the resistance according to the adjusted digital regulation resistance of gain parameter form.Thereby accomplish line array CCD pixel gain per stage compensation, make the pixel in different illumination zone can both utilize the dynamic range of CCD fully, strengthen the contrast of local signal, observe the details of regional area, improve the precision of demodulating system.
The practical implementation step of line array CCD pixel level signal gain self-compensation circuit is following in the spatial mode low coherence interference demodulating system:
At first; Obtain and gain parameter form that preset CCD pixel is corresponding; Gain parameter is that the background signal according to spatial mode low coherence interference demodulating system provides, and before demodulating system starts, fibre-optical F-P sensor is replaced with the fiber reflector with identical reflectivity.After the start-up system, CCD receives the background signal that does not contain interference fringe, and this moment, the CPLD control circuit was not controlled the gain self-compensation circuit, and gain circuitry is not in default conditions, and analog switch S1 breaks off, and S2 is closed, and resistance R 2 is linked in the discharge circuit negative feedback.The background signal of CCD output is transferred to host computer through amplification filtering circuit, data acquisition circuit.Host computer carries out match to the background signal that receives, and the background curves y=f that obtains being similar to (x) is as shown in Figure 4, calculates the corresponding gain parameter k of different pixel x by 3=f (x) * k (x), thereby obtains the parameter form of adjustment that gains, and download among the CPLD.
Secondly, to exporting the planarization of signal in the spatial mode low coherence interference demodulating system.Insert the F-P sensor.After the start-up system, the transfering clock TCLK of CPLD output line array CCD, drive clock CRx, reset clock RS, export the synchronous reset clock simultaneously and give analog switch S1, S2.Line array CCD begins to export the pixel signal under the effect of each road clock, when reset clock RS high level, line array CCD resets and exports pixel reset signal voltage V
O1, being linked into the gain self-compensation circuit through R1, this moment, analog switch S1 broke off, and S2 is closed, and resistance R 2 is linked into operational amplification circuit, output signal voltage V
O1,
In the formula: R
1Be the resistance of first resistance (R1), R
2It is the resistance of second resistance (R2).CPLD regulates the resistance R of digital regulation resistance according to predefined gain parameter form.The adjusting time guarantees that less than CCD reset time CCD exports before effective pixel signal, and digital regulation resistance reaches steady state (SS).When reset clock RS low level, line array CCD is exported effective pixel signal voltage V
I2, analog switch S1 is closed, and S2 breaks off, and digital regulation resistance is linked into operational amplification circuit.Output signal voltage V
O2,
In the formula: R is the resistance of adjusted digital regulation resistance.Reset clock RS low level finishes, the gain adjustment of a pixel signal of beginning.
In the experiment, during the Gain Automatic compensation of not enabled, the low coherence interference signal that receives is as shown in Figure 4.Zone a little less than illumination, interference signal receive the influence of illumination, poor contrast, and signal to noise ratio (S/N ratio) is low.After launching the adjustment of gain self-compensation circuit, the low coherence interference signal that receives is as shown in Figure 5, and the low coherence interference signal is obviously strengthened, and has effectively improved the even influence to the low coherence interference demodulation accuracy of uneven illumination.
Claims (4)
1. line array CCD pixel level signal gain self-compensation circuit in the spatial mode low coherence interference demodulating system is characterized in that this circuit is made up of operational amplifier, digital regulation resistance, first analog switch (S1), second analog switch (S2) and first resistance (R1) and second resistance (R2);
The positive input end grounding of described operational amplifier, inverting input is connected to the Linear Array CCD Signal output terminal through first resistance (R1); Be connected the negative-feedback circuit that constitutes by two parallel branches between the inverting input of operational amplifier and the output terminal; Wherein one the tunnel is first analog switch (S1) and digital regulation resistance (R) series arm, and another road is the series arm of second analog switch (S2) and second resistance (R2).
2. line array CCD pixel level signal gain method of self compensation that uses the said self-compensation circuit of claim 1 is characterized in that this compensation method is:
1st, before demodulating system started, default conditions were made as first analog switch (S1) and break off second analog switch (S2) closure;
2nd, system start-up; The output signal of line array CCD is received the input end of the said gain self-compensation circuit of claim 1; Startup along with demodulator circuit; Transfering clock, drive clock and the reset clock of the CPLD control circuit output line array CCD of demodulating system, the synchronous reset of CPLD control circuit output simultaneously clock is given first analog switch (S1) and second analog switch (S2);
3rd, line array CCD begins to export the pixel signal under the effect of each road clock, and the pixel signal is divided into reset signal and two parts of useful signal by the time, and the reset signal voltage of the different pixel outputs of line array CCD is identical; Useful signal is different; When reset clock was high level, line array CCD resetted and exports reset signal, and first analog switch (S1) breaks off; Second analog switch (S2) closure, second resistance (R2) is linked into operational amplification circuit;
4th, the CPLD resistance of regulating digital regulation resistance (R) according to predefined gain parameter form, the adjusting time is less than line array CCD reset time, guarantees that line array CCD exports before effective pixel signal, and digital regulation resistance reaches steady state (SS);
When reset clock is low level; Line array CCD output useful signal, first analog switch (S1) closure, second analog switch (S2) breaks off; Digital regulation resistance (R) is linked into operational amplification circuit; Effectively pixel signal gain adjustment, the reset clock low level finishes, and begins the adjustment of next pixel signal.
3. according to claims 2 described methods; It is characterized in that: line array CCD pixel output signal and reset clock are synchronous; CPLD output synchronous reset clock signal is controlled the resistance of first analog switch (S1), second analog switch (S2) and digital regulation resistance (R) and is regulated, according to preset gain parameter form to the gain self-compensation circuit in each pixel cycle synchronisation; Dynamically change the gain of operational amplification circuit, realize the meticulous adjustment of independence of each pixel signal gain.
4. according to claims 2 or 3 described methods, it is characterized in that: in each pixel cycle, when reset clock was high level, line array CCD resetted and exports pixel reset signal voltage V
I1, through gain self-compensation circuit output signal voltage V
O1,
In the formula: R
1Be the resistance of first resistance (R1), R
2It is the resistance of second resistance (R2);
When reset clock was low level, line array CCD was exported effective pixel signal voltage V
I2, through gain self-compensation circuit output signal voltage V
O2,
In the formula: R is the resistance of adjusted digital regulation resistance;
Each pixel output signal of CCD is divided into reset signal and two parts of useful signal; The gain self-compensation circuit guarantees that to the unified gain adjustment of CCD reset signal each pixel useful signal base voltage is identical, and useful signal is carried out the different gains adjustment; Realize that the regional pixel of different illumination can both utilize the dynamic range of CCD fully; Strengthen the contrast of local signal, observe the details of regional area, improve the precision of demodulating system.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109660209A (en) * | 2019-01-10 | 2019-04-19 | 深圳市禾望电气股份有限公司 | A kind of signals of rotating transformer modulation circuit and motor driven systems |
| CN113310400A (en) * | 2021-05-26 | 2021-08-27 | 桂林电子科技大学 | Laser interferometry synchronous dynamic gain compensation method for closed-loop control |
| CN113937962A (en) * | 2021-11-15 | 2022-01-14 | 江苏科技大学 | Device and method for improving current sampling precision of permanent magnet synchronous motor at low speed |
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