CN102595067A

CN102595067A - Analog-and-digital mixed accumulating time-delay integrating type complementary metal-oxide semiconductor image sensor

Info

Publication number: CN102595067A
Application number: CN2012100622301A
Authority: CN
Inventors: 高静; 高岑; 姚素英; 徐江涛; 史再峰; 聂凯明; 李渊清
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2012-03-07
Filing date: 2012-03-07
Publication date: 2012-07-18

Abstract

The invention relates to a time-delay integrating type complementary metal-oxide semiconductor image sensor (TDI-CIS). To achieve the purpose of providing a reading method for a TDI-CIS and greatly reducing the area of a chip without excessively increasing the conversion rate of a column-level ADC (analog-to-digital converter), the invention adopts the following technical scheme: an analog-digital mixed accumulation TDI-CIS comprises a pixel array, m analog domain accumulators, an analog-to-digital converter and a digital value register, wherein m analog domain accumulators are used for accumulating the signals output by the pixel array in the analog domain at m times in form of voltage or current, and outputting the signals accumulated at m times to the analog-to-digital converter to qualify; the quantified digital value is stored into the register; and the processes mentioned above are repeated for n times so as to achieve the formula of L=m*n, and the data in the register are accumulated at last to achieve the accumulation of L-grade signals. The analog-and-digital mixed accumulating TDI-CIS provided by the invention is mainly applied to the design and manufacture of the TDI-CIS.

Description

Simulation, numeral are mixed the type TDI-CIS imageing sensor that adds up

Technical field

The present invention relates to integration (Time-Delay-Integration time of delay; TDI) the complementary oxide semiconductor imageing sensor of type metal (CMOS image sensor; CIS); Be particularly related to a kind of method for designing that is applicable to extensive accumulator stage TDI type cmos image sensor sense architecture, specifically relate to simulation, the digital reading method that mixes the type TDI-CIS that adds up.

Background technology

TDI type cmos image sensor mainly by pel array, add up and read array circuit and the ADC change-over circuit is formed.The TDI type cmos image sensor of L level carries out L exposure to same target; Whenever after carrying out single exposure; Summation circuit is read signal and is added up with the signal that read last time, treat finally to accomplish add up for L time after, signal is transferred to subsequent conditioning circuit handles; This kind processing mode can significantly improve the signal to noise ratio of signal, improves the sensitivity and the image quality of imageing sensor.The principle schematic that adds up for TDI type cmos image sensor signal shown in Figure 1 comprises pel array and accumulator array among the figure.After system's operate as normal, the signal that in a transit time, at first the first row pixel exposure is obtained is input in first accumulator; In the next transit time, the second row pixel is made public to the image of previous frame, and the signal that will read is input in first accumulator, adds up with the result of last time; Repeat above operation, after identical exposure result has been carried out adding up for L time, obtain final signal and output.

Traditional T DI type cmos image sensor can be divided into analog domain and add up and the numeric field dual mode that adds up.The accumulation method of analog domain is the signal with pel array output, adds up in accumulator with the form of the analog signal of voltage or electric current.Use electric capacity to realize for the sampling of analog signal and the needs that add up; TDI type cmos image sensor for the L level; Accomplish in the simulation accumulator if signal adds up all, accumulator is not accomplished the L level and can not be cleared before adding up, therefore corresponding every row pixel; Adding up of L level just must have L accumulator, and be as shown in Figure 2.When the progression of accumulator is very big, just need use a large amount of electric capacity, make that image sensor chip size of (a pel array row level direction) on single direction is very big.Add up progression more than 128 grades the time, and the length in row level direction of chip will reach 3cm, makes chip cost rise, and yields descends.

The accumulation method of numeric field is after the signal process of pel array output is amplified in advance, directly to transfer to ADC and carry out quantification treatment, and the digital signal with ADC output adds up again, to realize the function of TDI type imageing sensor.This method can overcome the analog domain excessive problem of chip area that adds up, but the TDI type cmos image sensor of having relatively high expectations for line frequency, and the switching rate of ADC will become the bottleneck of chip design.Line frequency with 30KHz is an example, needs the switching rate of ADC to reach 4MHz, and this row level ADC that adopts usually for TDI type cmos image sensor is difficult to realize.

Summary of the invention

The present invention is intended to solve the deficiency that overcomes prior art; Provide a kind of and can significantly reduce chip area; Can excessively not promote simultaneously the reading method of the TDI-CIS of the switching rate that is listed as level ADC, for achieving the above object, the technical scheme that the present invention takes is; Simulation, numeral are mixed the type TDI-CIS imageing sensor that adds up; Comprise: pel array, a m analog domain accumulator, analog to digital converter, digital quantity register, m analog domain accumulator are used for adding up m time at analog domain with the form of voltage or the electric current signal with pel array output, m time the signal of adding up is outputed to analog to digital converter quantize; Digital quantity after the quantification is put into register; Above-mentioned process repeats n time, satisfies L=m * n, and the data in the register add up mutually the most at last, realizes that the signal of L level adds up.

The signal of same object view adds up 4 times at analog domain, the result who adds up for 4 times is quantized the back add up 2 times at numeric field, finally utilizes 6 simulation accumulators to realize 8 grades adding up, i.e. L=8, m=4, n=2.

Technical characterstic of the present invention and effect:

Signal reduces at the number of times that analog domain is added up, and can under the prerequisite that does not influence Signal-to-Noise, suitably dwindle the size of sampling capacitance and integrating capacitor; Because the simulation accumulator is re-used, reduced the quantity of integrating instrument simultaneously; The direct yield of two above-mentioned beneficial effects is significantly to have reduced area of chip.

Description of drawings

Fig. 1 TDI type cmos image sensor signal accumulative total principle schematic.

Fig. 2 traditional analog territory TDI type cmos image sensor structure chart.

Fig. 3 simulates, digital hybrid domain adds up type TDI-CIS sense architecture schematic diagram.

8 grades of simulations adopting among Fig. 4 the present invention, numeral mixing add up and read sketch map.

8 grades of simulations adopting among Fig. 5 the present invention, numeral are mixed the integrating instrument gating sequential chart of accumulation structure.Among the figure:

The row of Sel represent pixel array selects signal; The reset signal of Rst represent pixel array; Effective read output signal of TX represent pixel array; K1-K6 represents the gating signal of accumulator array; Reset1-Reset6 represents the reset signal of accumulator array;

1 represent pixel array is along with 8 exposures of advancing same object view being carried out of time among the figure; On behalf of accumulator array, 2 same object view information is at first added up reads after 4 times; 3 represent accumulator array that same object view information is carried out follow-up add up for 4 times read.

Embodiment

The present invention is that a kind of simulation, numeral are mixed the TDI type cmos image sensor that adds up.TDI type cmos image sensor for the L level; The signal of pel array output is at first added up m time at analog domain with the form of voltage or electric current; M time the signal of adding up is outputed to ADC quantize, analog quantity is transformed for digital quantity, and the digital quantity after will quantizing is put into register; Above-mentioned process is repeated n time, satisfy L=m * n, the data in the register add up mutually the most at last, realize that the signal of L level adds up.Be different from traditional full analog domain and add up, the novel reading circuit framework that adds up is only accomplished the task that adds up of a part in analog domain, so accumulator can be released in advance; This just means that in the process that the L level adds up the simulation accumulator can be reached the purpose of reduction number of accumulators by the repeated use of limited number of time, and then the reduction chip area.

Sense architecture among the present invention is described below:

The progression that adds up of TDI type cmos image sensor is L (L=2t, t=1,2; 3...); Is m with the exposure information of same object view as analog signal accumulative frequency in the analog domain accumulator, with adding up signal after m time after ADC converts digital quantity into, is stored in the register; Next simulate accumulator and continue the exposure information of same object view is added up m time, quantize data last in back and the register through ADC and add up; Above-mentioned process is repeated n time, and satisfy L=m * n, the signal of finally accomplishing the L level adds up.Because in analog domain adds up, every completions of the accumulator back of adding up for m time just can be reset, and then in the adding up of total L level, each is simulated accumulator and can be re-used n time, and promptly the number of accumulator has been reduced 1/m.Fig. 3 is the add up schematic diagram of type TDI-CIS sense architecture of analog digital hybrid domain.

Realize 8 grades with single-row 8 row pel arrays and be accumulated as example, Fig. 4 reads the sketch map that adds up for its signal.Structure shown in the figure, L=8, m=4, n=2, promptly the signal of same object view adds up 4 times at analog domain, the result who adds up for 4 times is quantized the back add up 2 times at numeric field, finally utilizes 6 simulation accumulators to realize 8 grades adding up.T1 is to arrange according to time sequencing to t10 among the figure, and t1 representes that constantly system just starts working; The box indicating pixel of the left side 8 row grey is represented by P1-P8 among the figure; The 6 row box indicating accumulators on the right are represented by K1-K6; Alphabetical A-I in the pixel representes different object view points, numeral in the accumulator and pixel combine represent alphabetical representative the object view point by the how many times that added up; The corresponding information of each object view whenever adds up to accomplish in analog domain and promptly reads for 4 times, and corresponding accumulator is reset, and prepares to read in next data, and the signal of reading is accomplished remaining adding up at numeric field after transferring to the ADC quantification; Fig. 5 is that the gating sequential of simulation accumulator and the row of pixel select sequential; Pel array is gone choosing according to the order of P8-P1, guarantees that the maximum object view information of accumulative frequency is preferentially read; The gating sequential of accumulator K1-K8 and reset timing are according to shown in the figure.

Claims

1. a simulation, numeral are mixed the type TDI-CIS imageing sensor that adds up; It is characterized in that; Comprise: pel array, a m analog domain accumulator, analog to digital converter, digital quantity register; M analog domain accumulator is used for adding up m time at analog domain with the form of voltage or the electric current signal with pel array output, m time the signal of adding up outputed to analog to digital converter quantize;

Digital quantity after the quantification is put into register; Above-mentioned process repeats n time, satisfies L=m * n, and the data in the register add up mutually the most at last, realizes that the signal of L level adds up.

2. transducer as claimed in claim 1 is characterized in that, the signal of same object view adds up 4 times at analog domain, the result who adds up for 4 times is quantized the back add up 2 times at numeric field, finally utilizes 6 simulation accumulators to realize 8 grades adding up, i.e. L=8, m=4, n=2.