201117611 六、發明說明： 【發明所屬之技術領域】 本發明係關於電子影像技術’尤指一種用於一金屬氧化物半導 體影像感測器的系統架構及訊號處理方法。 【先前技術】 電子影像裝置透過光電轉換，轉換一輸入光影像為一輸出電子 輸出訊號。一般來說，訊雜比（signal t0 noiseratio ’ SNR)為度量 轉換後之電子輸出訊號之品質的指標。訊雜比越高代表訊號品質越 佳0 為提升電子影像裝置的靈敏度，先前之技術是採用時間延遲積 •分式（timedelay integration，TDI)電荷耦合器（Chargecoupled device ’ CCD) ’來提升訊雜比’及提升靈敏度。一般來說，一 n個 分階時間延遲積分式感測器包含N個光電感測單元，用來根據一時 間延遲累積時序機制，產生一最終之影像訊號輸出。N個分階時間 延遲積分式感測器之影像訊號輸出為個別光電感測單元輸出訊號之 總合（N倍）。另外，當最終影像訊號輸出增加為^^倍時，其雜訊 成分僅增加#倍，換言之，時間延遲積分式電雜合器可提升訊雜 比i倍。 [S1 5 201117611 如欲將時間延遲累積機制應用至一金屬氧化物半導 裝置時，其基礎組成單做大幅度調^也就是說，—= 物半=體光電感測單元（例如光電二極體、光電電晶體）之結構與 -電·合器基礎單元大不_。為了實現時間延遲積分式麵氧 化物半導體’對應㈣贿構及訊號處理方式亦須同步調整，也就 是本發明的主要目的。 【發明内容】 ， 本發明提供一種時間延遲積分式金屬氧化物半導體光電像素感 測電路，包含有： ' " (a) —多兀件光電像素感測器，包含有複數個子光電感測單元 (SPSEi、SPSE2、…、SPS马、…、SPSEM，M> 1)。該複數 個子光電感測單元之位置相鄰，但彼此間被隔絕，分別用來累 積一像素光線於空間中之光影像訊號，以轉換為對應之子像素 光電訊號（SPPESi、SPPES2、…、SPPESj、…、SPPESM，Μ > i) ’其中該像素光線照射於該多元件光電像素感測器。 (b) 複數個中繼光電訊號累加器（PESAi、pESA2、 、pESAk、、 pesam)。該每一中繼光電訊號累加器PESAk可透過該金屬氧 化物半導體切換電晶體，耦接於該任一子光電感測單元 SPSEj ’用來接收對應之該子像素光電訊號sppESj，及產生一 累加中繼光電訊號ACPESk。更具體的說，該金屬氧化物半導 201117611 體切換電晶體可為-互補金屬氧化物半導體（c〇mplementary201117611 VI. Description of the Invention: [Technical Field] The present invention relates to electronic imaging technology, and more particularly to a system architecture and signal processing method for a metal oxide semiconductor image sensor. [Prior Art] An electronic imaging device converts an input optical image into an output electronic output signal by photoelectric conversion. In general, the signal t0 noise ratio (SNR) is an indicator of the quality of the converted electronic output signal. The higher the signal-to-noise ratio, the better the signal quality. To improve the sensitivity of the electronic imaging device, the previous technique used a time delay integration (TDI) charge coupled device (CCD) to enhance the signal. Than 'and improve sensitivity. In general, an n-order time-delay integral sensor includes N photo-sensing units for generating a final image signal output according to a time delay accumulation timing mechanism. The output signal of the N-order time delay integral sensor is the sum of the output signals of the individual photo-sensing unit (N times). In addition, when the final image signal output is increased to ^^ times, the noise component is only increased by # times. In other words, the time delay integral type electric hybrid device can increase the signal-to-noise ratio by i times. [S1 5 201117611 If you want to apply the time delay accumulation mechanism to a metal oxide semiconductor device, the basic composition of the unit is greatly adjusted. That is, -= half of the body = body photoinductance unit (such as photodiode) The structure of the body, the photoelectric transistor, and the basic unit of the electric and the combined device are not large. In order to realize the time delay integral type oxide semiconductor semiconductor, the corresponding (four) bribe and signal processing methods must also be adjusted simultaneously, which is the main purpose of the present invention. SUMMARY OF THE INVENTION The present invention provides a time delay integrated metal oxide semiconductor photo pixel sensing circuit, comprising: ' " (a) - a multi-component photo pixel sensor comprising a plurality of sub-optical sensing units (SPSEi, SPSE2, ..., SPS Ma, ..., SPSEM, M> 1). The plurality of sub-optical sensing units are adjacent to each other but are isolated from each other for accumulating optical image signals of a pixel of light in space to be converted into corresponding sub-pixel photoelectric signals (SPPESi, SPPES2, ..., SPPESj, ..., SPPESM, Μ > i) 'where the pixel light is illuminated by the multi-element photoelectric pixel sensor. (b) Multiple relay optoelectronic signal accumulators (PESAi, pESA2, pESAk, pesam). Each of the relay photo-electrical signal accumulators PESAk can be coupled to the MOS transistor switching transistor SPSEj' for receiving the corresponding sub-pixel photoelectric signal sppESj, and generating a cumulative Relay photoelectric signal ACPESk. More specifically, the metal oxide semiconducting 201117611 bulk switching transistor can be a -complementary metal oxide semiconductor (c〇mplementary
Metal-Oxide-Semiconductor，CMOS)電晶體。 (c ) 一讀取電路。透過切換操作耦接於該任一中繼光電訊號累加器 PESAk ’用來移除及讀取對應之該累加中繼光電訊號ACpESk。 ⑷-時間延遲累積相式控彻。雛於該複數個子光電感測單 元SPSE〗、…、SPSEM、該複數個中繼光電訊號累加器 PESA!、…、PESAM及該讀取電路，用來影響一預設之循環時 間序列。如此一來，該時間延遲積分式金屬氧化物半導體光電 像素感測電路可透過該讀取電路，產生最終乏複數個時序訊 號，進而增加訊雜比，該每一時序訊號係等於該子像素光電訊 號SPPES!、…、SPPESM之時間延遲之總合。 在一實施例中，該複數個子光電感測單元SPSE!、...、SPSEm 及該複數個中繼光電訊號累加器PESAl、…、PESAm間之耦合之該 循環時間序列之一次循環係： (SPSEr PESAb SPSE2- PESA2,.., SPSEM- PESAM)； (SPSEr PESA2, SPSE2- PESA3,. .，SPSEM- PESA!); ;以及 (SPSEi- PESAM，SPSE2- PESA丨，..，SPSEM- PESAm])。 在一實施例中，該複數個中繼光電訊號累加器pesa,、...、 pesam及該讀取電路間之耦合之該循環時間序列之一次循環係： (PESArROC)；Metal-Oxide-Semiconductor, CMOS) transistor. (c) A read circuit. The relay photo-electrical accumulator PESAk ’ is coupled to the corresponding relay photo-electric signal ACpESk through a switching operation. (4) - Time delay cumulative phase control. The plurality of sub-optical sensing units SPSE, ..., SPSEM, the plurality of relay photoelectric signal accumulators PESA!, ..., PESAM and the reading circuit are used to influence a predetermined cyclic time sequence. In this way, the time-delay integrated metal oxide semiconductor photo-pixel sensing circuit can generate a final plurality of timing signals through the read circuit, thereby increasing the signal-to-noise ratio, and each timing signal is equal to the sub-pixel photoelectric The sum of the time delays of the signals SPPES!,..., SPPESM. In one embodiment, the cycle of the plurality of sub-optical sensing units SPSE!, . . . , SPSEm and the plurality of relay photo-signal accumulators PESAl, . . . , PESAm is cyclically cycled: SPSEr PESAb SPSE2-PESA2,.., SPSEM-PESAM); (SPSEr PESA2, SPSE2-PESA3, . . , SPSEM-PESA!); and (SPSEi-PESAM, SPSE2-PESA丨,..,SPSEM-PESAm] ). In one embodiment, the looping sequence of the cyclic time series of the plurality of relayed photoelectric signal accumulators pesa, ..., pesam and the reading circuit is: (PESArROC);
[SI 7 201117611 (PESA2-ROC); ....，以及 (PESAM-ROC )。 在一實施例中，該每一子光電感測單元SPSEj係一光電二極體 或一光電電晶體。 在一實施例中’該每一中繼光電訊號累加器PESAk包含有一玎 重δ又之電谷性轉阻放大器及一充電電容，用來透過時間累積，可_重 設地轉換該子像素光電訊號SPPESj為該累加中繼光電訊號 ACPESk，其中該充電電容之容量於該複數個子像素光電訊號 SPPESi、…、SPPESM之時間延遲之總合所造成之一延長時間，須 足以減輕通過該電容性轉阻放大器之一充電訊號於像素間因漏電流 不同所造成之影像衰減效應。除此之外，該每一中繼光電訊號累加 器PESAk另包含有一單位增益放大器，用來緩衝該電容性轉阻放大 器對該子像素感測器單元SPSEj之影響，以轉換該子像素光電訊號 SPPESj為一對應之光電電壓，進而避免影像衰減效應。 在一較詳細實施例中，該每一讀取電路另包含有串連之一像素 關聯雙取樣電路及一類比數位轉換器，用來取得所需之該累加中繼 光電訊號ACPESk ’及將該累加中繼光電訊號ACPESk數位化為—视 訊輪出資料。 201117611 【實施方式】 請參考第1圖，第1圖為本發明實施例，四個分階之時間延遲 積分式（time delay integration，TDI)金屬氧化物半導體 (Metal-Oxide-Semiconductor，MOS)光電像素感測電路1之示意 圖。按光電訊號產生及進行的順序，光電像素感測電路1包含有一 子像素感測單元區3、一光電訊號累加區5及一讀取電路區7。子像 素感測單元區3包含有多元件光電像素感測器MEPSi、MEPS2、 ® MEPS3。多元件光電像素感測器MEPS!包含有子光電感測單元 SPSE„、SPSEn、SPSEls、SPSEM。子光電感測單元 SPSE„、SPSE12、 SPSEU、SPSEH之位置相鄰，但彼此間被隔絕。相似地，多元件光 電像素感測器MEPS2包含有相鄰又彼此獨立的子光電感測單元 SPSE”、SPSE22、SPSE23、SPSE24。在本實施例中，每一子光電感 測早元為一光電一極體’但不限於此’例如亦可為一光電電晶體。 子光電感測單元SPSE„、SPSEu、SPSEls、SPSEH分別累積一像素 # 光線hv於空間中之光影像訊號，以轉換為對應之子像素光電訊號 SPPES,、SPPES2、sppes3、SPPES4，其中像素光線hv照射於多元 件光電像素感測器MEPSi。 光電訊號累加區5中之中繼光電訊號累加器pESAu、pESAi2、 PESAu、PESAM可提供多元件光電像素感測器]y[EpSi處理光電訊 號時’所需之訊號。在此實施例中，每一中繼光電訊號累加器包含 一可重設之電容性轉阻放大器及一充電電容，用來透過時間累積， 2〇1117611 可重設地轉換對應之一子像素光電訊號SPPESj為一累加中繼光電 訊號ACPES。在第1圖中，任一中繼光電訊號累加器可透過切換一 開關矩陣’連接並接收一對應之子像素光電訊號，進而產生累加中 繼光電訊號ACPES。舉例來說，中繼光電訊號累加器PESA22可透 過切換操作’連接至子像素光電訊號SPPES24，以產生一累加中繼 光電訊號ACPES22。較佳地，組成開關矩陣之開關可為金屬氧化物 半導體開關電晶體’更具體的說，為互補金屬氧化物半導體 (Complementary Metal-Oxide-Semiconductor，CMOS )電晶體。 讀取電路區7包含一讀取電路9，可透過切換開關矩陣，耦接 至任一中繼光電訊號累加器PESAk，用來移除及讀取一對應之累加 中繼光電訊號ACPESk。舉例來說，可在讀取後，透過重新設定電 谷性轉阻放大器，移除累加中繼光電訊號ACPESk。針對多元件光 電像素感測器MEPSi、MEPS2、MEPS3，讀取電路9可分別產生對 應之時序光電時間訊號SQTSi、SQTS2、S(JTS3。 在第1圖中’光電像素感測電路！包含有一時間延遲累積序列 控制器1卜透過開關矩陣，叙接於子光電感測單元SPSE、中繼光 電訊號累㈣PESA及電路9，用來影響—職之循環時間序 Ά此-來，透過讀取電路9 ’賴像素感測電路丨可產生多元 件光電像素感測器蕭S1所需之時序光電時間訊號SQTS1，讀等 ^子像素找峨 S聰u、SPPESi2、SPPESi3、sppESi4 目似地，光電像素感測電路i可分別針對多元件光電像素感測器 201117611 MEPS2、MEPS3，分別產生時序光電時間訊號SQTS2、SQTS3，其 中光電時間訊號sqts2之值等於子像素光電訊號SPPES21、 SPPES22、SPPESu、SPPES24的總合，而光電時間訊號SQTS3之值 等於子像素光電訊號sppes31、SPPES32、SPPES33、SPPES34的總合。 請繼續參考第2A圖至第2H圖，第2A圖至第2H圖分別為時 間延遲累積序列控制器11之耦合狀態之一循環時間序列之第一幀 至第八幀之示意圖。在第2A圖至第2H圖中，為方便說明：子光電 感測單元SPSEu之子像素光電訊號sppESu標示為「#1」；子光電 感測單元SPSE1Z之子像素光電訊號sppeSu標示為「#2」；子光電 感測單元SPSEn之子像素光電訊號sppeSu標示為「#3」；子光電 感測單元SPSEM之子像素光電訊號sppesm標示為「#4」。子光電 感測單元SPSE與中繼光電訊號累加器PESA間之訊號耦合由指向 下方的箭頭表示。 舉例來說，在第2A圖之第一幀中，子光電感測單元spSEi4耦 合至中繼光電訊號累加iiPESA14;在第2C圖之第三巾貞中，子光電 感測單το SPSE^耦合至中繼光電訊號累加器pESAi4。另外，讀取 電路9與中繼找訊號累加器PESA間之訊號耗合亦由向下指的箭 頭表示。舉例來說，在第2Β圖之第二巾貞中，中繼光電訊號累加器 PESAu耦合至讀取電路9，並由讀取電路9讀取；在第犯圖之第 七情中’巾繼光電訊號累加器PESAi3輕合至讀取電路9，並由讀取 電路9讀取。追縱時間延遲累積序列控制器u從第―賴至第八=之 i S 1 11 201117611 操作’時序光電時間訊號SQTSk時序可表示為： 幀數 SQTSi 第一幀 #1 第二幀 #1+#2 第二幀 #1+#2 + #3 第四幀 #ι+#2 + #3 + #4 第五幀 #1+#2 + #3 + #4 第六幀 #1 + #2 + #3 + #4 第七幀 #1+#2 + #3 + #4 · 第八幀 #1+#2 + #3 + #4 由上可知，除了初始狀態外，時序光電時間訊號SQTSi之時序 呈現一穩定狀態，等於子像素光電訊、SppESi2、 SPPESU、SPPESM之時間延遲總合。.相似地，時序光電時間訊號 SQTS2之時序達到穩態後，等於子像素光電訊號SppES^、sppESu、 SPPES23、SPPES24之時間延遲總合。 以此類推，本發明可應用在N個分階之時間延遲積分式金屬氧 化物半導體光電像素感測電路中，其尹N為任何大於】的整數。另 外，多元件光電像素感測器MEPS的數量可為任意正整數，並在空 間安排上，可較佳地以線性的二維矩陣實現，但不限於此。 請繼續參考第3圖，第3圖為四個分階之光電像素感測電路工 12 201117611 中，子光電感測單元SPSE與讀取電路9間之訊號路徑之示意圖。 如第3圖所示，每一中繼光電訊號累加器PESA包含一重設之電容 性轉阻放大器及一充電電容cf。舉例來說，子光電感測單元SpSEn 及一電容性轉阻放大器CTL·^間透過一轉傳控制開關TR1及一轉傳 選擇開關TR一SEL1串接；電容性轉阻放大器CTIAi及讀取電路9 間透過一讀取選擇開關RD一SEL1串接。如欲重設電容性轉阻放大 器CTIA丨，可關閉-重設關reSET卜以重置一累加中繼光電訊 _號ACPESn。讀取電路9包含串接之像素關聯雙取樣電路及一類比 數位轉換器（未繪於第3圖中），用絲得所需之累加中繼光電訊號 ACPES，並數位化為一視訊輸出資料。相關之細節可參考美國專利 申明案US12/171，351之第1圖及第4圖。須注意的是，子像素光電 訊號SPPESn、SPPESu、SPPESn、SPPESM之時間延遲之總合所造 成之-延長時間。因此’儘管大電容之以會浪費電路面積及降低累 加中繼光電§fl號ACPES之準位，在設計電路時，^^乃須選擇夠大的 充電電容Cf’以在延長咖，減輕通過電雜轉阻放大$⑶八之 隹一充電訊號因漏電流所造成之影像衰減效應。 如欲避免使用大面積之充電電容Cf，每一中繼光電訊號累加器 PESA另可包含-可重設之單位增益放大器U(JA，如第4圖所示。 單位增益放大器UGA用來緩衝電容性轉阻放大器對子像素感測器 單tgSPSE之影響，以轉換子像素光電訊號31>1>£8為一對應之光電 電壓，進而避免影像衰減效應。舉例來說，在第*圖中一單位增 盈放大器UGA^衝電容性轉阻放大器CTIAi對子像素感測器單元[SI 7 201117611 (PESA2-ROC); ...., and (PESAM-ROC). In one embodiment, each of the sub-photonic sensing units SPSEj is a photodiode or an optoelectronic transistor. In an embodiment, each of the relay photo-signal accumulators PESAk includes a δ δ electric valley transimpedance amplifier and a charging capacitor for accumulating time, and the sub-pixel photoelectric can be _reset-converted The signal SPPESj is the accumulated relay photoelectric signal ACPESk, wherein the capacity of the charging capacitor is caused by the sum of the time delays of the plurality of sub-pixel photoelectric signals SPPESi, . . . , SPPESM, which is sufficient to reduce the capacitive transfer. The image attenuation effect caused by the difference in leakage current between the pixels of one of the resistance amplifiers. In addition, each of the relay photo signal accumulators PESAk further includes a unity gain amplifier for buffering the influence of the capacitive transimpedance amplifier on the sub-pixel sensor unit SPSEj to convert the sub-pixel photoelectric signals. SPPESj is a corresponding photoelectric voltage to avoid image attenuation effects. In a more detailed embodiment, each of the read circuits further includes a series of pixel-associated double sampling circuits and an analog-to-digital converter for obtaining the required accumulated relay optical signal ACPESk 'and The accumulated relay photoelectric signal ACPESk is digitized into a video round-off data. 201117611 [Embodiment] Please refer to FIG. 1. FIG. 1 is a diagram showing four time-delayed time delay integration (TDI) metal-oxide-semiconductor (MOS) photovoltaics according to an embodiment of the present invention. A schematic diagram of the pixel sensing circuit 1. In the order in which the photoelectric signals are generated and performed, the photoelectric pixel sensing circuit 1 includes a sub-pixel sensing unit region 3, an optical signal accumulating region 5, and a read circuit region 7. The subpixel sensing unit area 3 includes multi-element photoelectric pixel sensors MEPSi, MEPS2, ® MEPS3. The multi-element photoelectric pixel sensor MEPS! includes sub-photoelectric sensing units SPSE„, SPSEn, SPSEls, SPSEM. The sub-optical sensing units SPSE„, SPSE12, SPSEU, SPSEH are located adjacent to each other but are isolated from each other. Similarly, the multi-element photoelectric pixel sensor MEPS2 includes adjacent and independent sub-photonic sensing units SPSE", SPSE22, SPSE23, SPSE24. In this embodiment, each sub-photon sensor is an optical element. The one-pole body 'but not limited to this' may be, for example, a photovoltaic transistor. The sub-optical sensing units SPSE „, SPSEu, SPSEls, and SPSEH respectively accumulate a light image signal of a pixel # ray hv in space to be converted into a corresponding The sub-pixel photoelectric signals SPPES, SPPES2, sppes3, SPPES4, wherein the pixel light hv is irradiated to the multi-element photoelectric pixel sensor MEPSi. The relay photoelectric signal accumulators pESAu, pESAi2, PESAu, and PESAM in the photoelectric signal accumulation area 5 can provide signals required for the multi-element photoelectric pixel sensor y [EpSi when processing the photoelectric signal]. In this embodiment, each of the relay photo-signal accumulators includes a resettable capacitive transimpedance amplifier and a charging capacitor for accumulating time, and 2〇1117611 reconfigurably converts one of the sub-pixels. The signal SPPESj is an accumulated relay photoelectric signal ACPES. In Fig. 1, any of the relay photo-signal accumulators can connect and receive a corresponding sub-pixel photo-electric signal by switching a switch matrix' to generate an accumulated relay photo-electric signal ACPES. For example, the relay opto-electronic accumulator PESA 22 can be coupled to the sub-pixel optoelectronic SPPES 24 via a switching operation to generate an accumulated relay opto-electronic signal ACPES 22. Preferably, the switch constituting the switch matrix may be a metal oxide semiconductor switching transistor ‘specifically, a Complementary Metal-Oxide-Semiconductor (CMOS) transistor. The read circuit area 7 includes a read circuit 9 coupled to any of the relay photo signal accumulators PESAk through the switch matrix to remove and read a corresponding accumulated relay optical signal ACPESk. For example, after the reading, the accumulated relay photoelectric signal ACPESk can be removed by resetting the valley transimpedance amplifier. For the multi-element photoelectric pixel sensors MEPSi, MEPS2, MEPS3, the read circuit 9 can respectively generate corresponding timing photoelectric time signals SQTSi, SQTS2, S (JTS3. In Fig. 1 'photopixel sensing circuit! contains a time The delay accumulation sequence controller 1 is transmitted through the switch matrix, and is connected to the sub-photo-sensing unit SPSE, the relay photo-signal-tired (four) PESA, and the circuit 9 for affecting the cycle time sequence of the job, and the read circuit 9 'Lai pixel sensing circuit 丨 can produce multi-element photoelectric pixel sensor Xiao S1 required timing photoelectric time signal SQTS1, read ^ sub-pixel find 峨 S Cong u, SPPESi2, SPPESi3, sppESi4 Vision, photoelectric pixel sense The measuring circuit i can respectively generate the timing photoelectric time signals SQTS2 and SQTS3 for the multi-element photoelectric pixel sensors 201117611 MEPS2 and MEPS3, wherein the value of the photoelectric time signal sqts2 is equal to the sum of the sub-pixel photoelectric signals SPPES21, SPPES22, SPPESu and SPPES24. The value of the photoelectric time signal SQTS3 is equal to the sum of the sub-pixel photoelectric signals sppes31, SPPES32, SPPES33, SPPES34. Please continue to refer to the 2A to 2H 2A to 2H are schematic diagrams showing the first frame to the eighth frame of one cycle time series of the coupling state of the time delay accumulation sequence controller 11, respectively. In the 2A to 2H diagrams, for convenience of explanation: The sub-pixel photoelectric signal sppESu of the sub-optical sensing unit SPSEu is marked as "#1"; the sub-pixel photoelectric signal sppeSu of the sub-optical sensing unit SPSE1Z is marked as "#2"; the sub-pixel photoelectric signal sppeSu of the sub-optical sensing unit SPSEn is marked as " #3"; The sub-pixel photoelectric signal sppesm of the sub-photoelectric sensing unit SPSEM is marked as "#4". The signal coupling between the sub-optical sensing unit SPSE and the relay photo-signal accumulator PESA is indicated by an arrow pointing downwards. In the first frame of FIG. 2A, the sub-photonic inductance measuring unit spSEi4 is coupled to the relay photoelectric signal accumulating iiPESA14; in the third frame of the second drawing, the sub-photonic inductance measuring unit το SPSE^ is coupled to the relay photoelectric The signal accumulator pESAi4. In addition, the signal consumption between the read circuit 9 and the relay lookup accumulator PESA is also indicated by the downward pointing arrow. For example, in the second frame of the second figure, the relay Light The signal accumulator PESAu is coupled to the read circuit 9 and is read by the read circuit 9; in the seventh case of the first map, the wiper photoelectric signal accumulator PESAi3 is lightly coupled to the read circuit 9, and is read by the circuit. 9 read. The tracking time delay accumulation sequence controller u from the first to the eighth = i S 1 11 201117611 operation 'timing photoelectric time signal SQTSk timing can be expressed as: frame number SQTSi first frame #1 second frame #1+#2 Second frame #1+#2 + #3 Fourth frame #ι+#2 + #3 + #4 Fifth frame #1+#2 + #3 + #4 Sixth frame #1 + #2 + #3 + #4 7th frame #1+#2 + #3 + #4 · 8th frame #1+#2 + #3 + #4 It can be seen from the above that in addition to the initial state, the timing photoelectric time signal The timing of SQTSi presents a steady state, which is equal to the time delay sum of sub-pixel optoelectronics, SppESi2, SPPESU, and SPPESM. Similarly, after the timing of the timing photoelectric time signal SQTS2 reaches a steady state, it is equal to the time delay sum of the sub-pixel photoelectric signals SppES^, sppESu, SPPES23, and SPPES24. By analogy, the invention can be applied to N stepped time delay integrated metal oxide semiconductor photopixel sensing circuits, with Yin N being any integer greater than 。. In addition, the number of multi-element photo pixel sensors MEPS may be any positive integer and may be preferably arranged in a linear two-dimensional matrix, but is not limited thereto. Please refer to FIG. 3 again. FIG. 3 is a schematic diagram of the signal path between the sub-photonic sensing unit SPSE and the reading circuit 9 in the four-step photoelectric pixel sensing circuit 12 12176176. As shown in Fig. 3, each relay photoelectric signal accumulator PESA includes a reset capacitive transimpedance amplifier and a charging capacitor cf. For example, the sub-optical sensing unit SpSEn and a capacitive transimpedance amplifier CTL·^ are connected in series through a transfer control switch TR1 and a transfer selection switch TR-SEL1; the capacitive transimpedance amplifier CTIAi and the read circuit 9 is connected in series through a read selection switch RD-SEL1. To reset the capacitive transimpedance amplifier CTIA, you can turn off-reset the reSET to reset an accumulative relay __ACPESn. The read circuit 9 includes a series-connected pixel-associated double-sampling circuit and an analog-to-digital converter (not shown in FIG. 3), which is used to obtain the required accumulated relay optical signal ACPES and digitized into a video output data. . For details, refer to Figures 1 and 4 of U.S. Patent Application Serial No. US 12/171,351. It should be noted that the sum of the time delays of the sub-pixel photoelectric signals SPPESn, SPPESu, SPPESn, SPPESM - extended time. Therefore, although the large capacitance will waste circuit area and reduce the level of accumulating relay photoelectric §fl number ACPES, when designing the circuit, ^^ must select a large enough charging capacitor Cf' to extend the coffee and reduce the electricity. The hybrid resistance is amplified by the image attenuation effect caused by the leakage current of the charging signal of (3) eight. To avoid the use of large-area charging capacitors Cf, each relay photo-signal accumulator PESA can also include a resettable unity-gain amplifier U (JA, as shown in Figure 4. Unity gain amplifier UGA is used to buffer capacitors The effect of the transimpedance amplifier on the sub-pixel sensor single tgSPSE is to convert the sub-pixel photoelectric signal 31 > 1 > £8 to a corresponding photoelectric voltage, thereby avoiding the image attenuation effect. For example, in the figure Unit gain amplifier UGA ^ punch capacitive transimpedance amplifier CTIAi to sub-pixel sensor unit
[SI 13 201117611 SPSEU之影響。另外，串接之一讀取開關肋丨及一關聯雙取樣電路 CDS1設置於單位增益放大n UGAi及電容性轉阻放大器CTJAi 間，用來移除每當重置時’單位增益放大㈣叫所產生之一重置 kTC雜訊失真。相關細節可參考美國專利申請案usll/869,732 (公 開號2009-0091648)之第9圖及第η圖。 比較第1圖及美國專利申請案usll/869,732之第2圖，本發明 可透過重新安排元件，提升效能。具體來說，若子光電感測單元 SPSE"、SPSEu、SPSEn、SPSEH線性地沿-子像素感測器線設置，肇 可將： (a)編號為奇數的中繼光電訊號累加器、pESAu及對應之 部分讀取電路9設置於子像素感測器線之一第一側； ⑻編號為偶數的中繼光電訊號累加器pESAi2、pESAi4及對應之 部分讀取電路9設置於子像素感測器線之一第二側。 如此來^子光電感測早元之線性空間解析度受限於相關之訊號 累加及讀取電路時，由於相關訊號累加及讀取電路之線性集成密度鲁 降低，線性空間解析度可獲得提升。 綜上所述，本發明提供一種時間延遲積分式金屬氧化物半導體 光電像素感測電路，可以高訊雜比來實現光電影像感測。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 201117611 【圖式簡單說明】 物半2^本發0_例’四彳_之時岐遲積分式金屬氧化 +導體光電像素感測電路之示意圖。[SI 13 201117611 SPSEU impact. In addition, one of the serial read switch ribs and an associated double sampling circuit CDS1 are disposed between the unity gain amplifier n UGAi and the capacitive transimpedance amplifier CTJAi to remove the unity gain amplifier (four) whenever reset. One of the generated kTC noise distortions is generated. For details, refer to Figure 9 and Figure η of US Patent Application No. ll. 869,732 (publication number 2009-0091648). Comparing Figure 1 with Figure 2 of U.S. Patent Application Serial No. ll. 869,732, the present invention can improve performance by rearranging components. Specifically, if the sub-photonic sensing units SPSE", SPSEu, SPSEn, and SPSEH are linearly arranged along the sub-pixel sensor line, 肇 can: (a) the odd-numbered relay photo-signal accumulator, pESAu, and corresponding The partial read circuit 9 is disposed on one side of the sub-pixel sensor line; (8) the even-numbered relay photo-signal accumulators pESAi2, pESAi4 and the corresponding partial read circuit 9 are disposed on the sub-pixel sensor line One of the second sides. In this way, the linear spatial resolution of the optical sensor is limited by the associated signal. When the circuit is accumulated and read, the linear spatial resolution can be improved because the linear integration density of the associated signal accumulation and read circuit is reduced. In summary, the present invention provides a time delay integrated metal oxide semiconductor photo pixel sensing circuit capable of realizing photoelectric image sensing with high signal to noise ratio. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. 201117611 [Simple description of the diagram] Schematic diagram of the semiconductor photoelectric oxidation + conductor photo-pixel sensing circuit when the object half 2^ is 0_example 'four 彳 _.
第2A圖至第2H圖為第1圖之光電像素感測電路之主要元件間 搞合狀態之—棘時間序狀示意圖。 B 訊 第3圖為第1圖之光電像素感測電路之一較詳細實施例之一 號路徑之示意圖。 第4圖為第1圖之光電像素感測電路之另一較詳細實施例之一 訊號路徑之示意圖。 【主要元件符號說明】Fig. 2A to Fig. 2H are schematic diagrams showing the state of the engagement between the main components of the photoelectric pixel sensing circuit of Fig. 1 . B. Figure 3 is a schematic diagram of one of the more detailed embodiments of the photo-pixel sensing circuit of Figure 1. Figure 4 is a schematic illustration of one of the more detailed embodiments of the photodiode sensing circuit of Figure 1 . [Main component symbol description]
7 9 光電像素感測電路 子像素感測單元區 光電訊號累加區 讀取電路區 讀取電路 11 時間延遲累積序列控制器 #1、#2、#3、#4 子像素光電訊號 MEPSi、MEPS2、MEPS3 多元件光電像素感測器 SPSE„、SPSE12、SPSE13、SPSE14、SPSE21、spse22、spse24、spse31、7 9 Photoelectric pixel sensing circuit Sub-pixel sensing unit area Photoelectric signal accumulating area Reading circuit area reading circuit 11 Time delay accumulation sequence controller #1, #2, #3, #4 Sub-pixel photoelectric signal MEPSi, MEPS2 MEPS3 multi-element photoelectric pixel sensor SPSE„, SPSE12, SPSE13, SPSE14, SPSE21, spse22, spse24, spse31,
[SI 15 201117611 SPSE32 ' SPSE34 子光電感測單元 sppesu、sppes12、sppes14 、SPPES21、SPPES22、SPPES24、SPPES SPPES32' SPPES34 子像素光電訊號 PESA„、PESA12、PESA13、 pesa14、pesa21、pesa22、pesa24 PESA31 ' PESA32 ' PESA34 中繼光電訊號累加器 ACPESn ' ACPES12 ' ACPES14 ' ACPES21 ' ACPES22 ' ACPES24 ACPES31、ACPES32、ACPES34累加中繼光電訊號 Vr、Vb 參考電壓 SQTSi > SQTS2 ' SQTS3 時序光電時間訊號 TR1 ' TR2 轉傳控制開關 TR_SEL1 ' TR_SEL2 轉傳選擇開關 RD_SEL1 ' RD_SEL2 讀取選擇開關 CTIA! ' CTIA2 電容性轉阻放大器 UGAi ' UGA2 單位增益放大器 RSTj ' RST2 開關 CDS 卜 CDS2 關聯雙取樣電路 RESET1 ' RESET2 重設開關 Cf 充電電容 hv 像素光線[SI 15 201117611 SPSE32 ' SPSE34 sub-optical sensing unit sppesu, sppes12, sppes14, SPPES21, SPPES22, SPPES24, SPPES SPPES32' SPPES34 sub-pixel photoelectric signal PESA„, PESA12, PESA13, pesa14, pesa21, pesa22, pesa24 PESA31 'PESA32 ' PESA34 relay photoelectric signal accumulator ACPESn ' ACPES12 ' ACPES14 ' ACPES21 ' ACPES22 ' ACPES24 ACPES31 , ACPES32 , ACPES34 cumulative relay photoelectric signal Vr , Vb reference voltage SQTSi > SQTS2 ' SQTS3 timing photoelectric time signal TR1 ' TR2 transfer control switch TR_SEL1 ' TR_SEL2 Transposition selection switch RD_SEL1 ' RD_SEL2 Read selection switch CTIA! ' CTIA2 Capacitive transimpedance amplifier UGAi ' UGA2 Unity gain amplifier RSTj ' RST2 Switch CDS Bu CDS2 Associated double sampling circuit RESET1 ' RESET2 Reset switch Cf Charging capacitor hv Pixel light
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