CN102594745A - Synchronization method for single carrier frequency domain equalization system and realization circuit thereof - Google Patents

Abstract

The invention discloses a synchronization method for a single carrier frequency domain equalization system, which comprises a multiplex technique and a bit synchronization method based on training characters. According to the method, three training characters are added at a frame head and used for completing various types of synchronization and signaling estimation algorithm, so that the load of the frame head is lowered, and effective transmission rate of data is improved. The invention discloses bit synchronization algorithm, and the algorithm is divided into an initial synchronism and accurate synchronization, after the range of the initial synchronism is confirmed, an accurate synchronization position is found out in the range by adopting accurate synchronization method, compared with a conventional bit synchronization method, other peak value of the algorithm can not exist out the range of the initial synchronization, and the algorithm has more accurate bit synchronization position judegement ability and has more high working efficiency.

Description

Method for synchronous in the single-carrier frequency domain equalization system and realization circuit thereof

Technical field

The present invention relates to wireless communication field; Like wireless sensor network, system of broadband wireless communication etc.; Relate in particular to a kind of based on single carrier frequency domain equalization (Single Carrier System with Frequency Domain Equalization, SC-FDE) method for synchronous of technology.

Background technology

Radio communication is experiencing from the analog communication to the digital communication, from the very fast development of FDMA to CDMA, is that technology innovation is the fastest, the maximum industry of market capacity.Radio communication develops into today, and more and more service content have proposed increasingly high requirement to message transmission rate, and the frequency spectrum resource wretched insufficiency has become the bottleneck of restriction radio communication career development day by day.Though second generation mobile communication can still can't satisfy the requirement of following multimedia communication than fast thousands of times of existing transmission rate.Therefore, how fully to develop limited frequency spectrum resources, improve the availability of frequency spectrum, become one of focus of current wireless communication technology research.When improving the utilance of diving frequently, guarantee that the reliability of transmission also is an important problem.Following wireless communications application has higher requirement to using environment, and this just needs new wireless communication technology can adapt to more abominable channel, can overcome various adverse effects.

Wireless communication technology is applied in the multiple different system, like wireless sensor network, system of broadband wireless communication etc.Wireless sensor network (WSN) is that a kind of brand-new information is obtained platform; Can monitor in real time with the collection network distributed areas in the information of various detected objects; And these information are sent to gateway node; To realize that complicated specified scope internal object detects and follows the tracks of, have characteristics such as rapid deployment, survivability are strong, wide application prospect is arranged.Along with the development of radio sensing network, the transfer of data of higher rate becomes and is necessary very much, and the especially transmission of burst packet need to adapt to that the sensing net is disposed flexibly, the application demand of low-cost, small size.In addition, Wideband Wireless Digital Communication also is current wireless development of Communication Technique forward position, is having broad application prospects aspect the integrated services such as voice, video, data and multimedia in future.

In the research that has the meaning represented aspect the bit synchronization of single carrier frequency domain equalization is David Falconer, the Sirikiat Lek Ariyavisitakul of research institutions such as Ka Ledun (Carleton) university in 2002; " Frequency Domain Equalization for Single-Carrier Broadband Wireless Systems " paper that scholars such as Anader Benyamin-Seeyar deliver at IEEE Communications Magazine; Single carrier frequency domain equalization (SC-FDE) technology has been proposed in the literary composition; This technology can obtain utilization flexibly in systems such as wireless sensor network, broadband wireless communications; It has the sensitiveness of lower peak-to-average force ratio and phase noise, has reduced the power consumption and the cost of analogue devices such as power amplifier; And under the propagation conditions that has the time delay diffusion, the SC-FDE system can obtain the performance approximate with ofdm system; SC-FDE system transmitting terminal is simple in structure simultaneously, has reduced the power consumption of transmitting terminal.Therefore, the SC-FDE system can be widely used in the wireless communication system.Thereafter occurring some documents has in succession launched in depth to discuss to each item key technology in the SC-FDE system.

In the SC-FDE system, be a very crucial step synchronously.The SC-FDE system is very responsive to synchronous error (especially bit synchronization error).For the phase deviation of sampling clock, after FFT transforms to frequency domain, be equivalent to the phase place rotation of each code element, be the interference of the property taken advantage of, can correct through frequency domain equalization and come; The frequency departure of sampling clock transforms to and is equivalent to introduce inter-carrier interference on the frequency domain, can't be through the frequency domain equalization compensation, and also the same presence bit synchronous error of signal after the time domain is returned in the IFFT conversion, has very big interference for judgement.In addition, the frequency shift (FS) of sampling clock (frequency deviation) also can cause the timing wander of signal, influences synchronization performance.Therefore, the synchronization module of SC-FDE system, bit synchronization module especially wherein is one of whole system key for design technology.

Summary of the invention

In order to solve the problems referred to above that exist in the prior art, the present invention proposes a kind of new bit synchronization method based on single-carrier wave frequency domain equalization technology, and concrete technical scheme is following:

Adopt a kind of multiplex technique based on train word, with three groups of training sequences realized in single carrier frequency domain equalization (SC-FDE) system synchronously, specifically, be to be divided into 3 training sequence TS1, TS2 and TS3 to the frame structure in the SC-FDE system leading;

In the algorithm of synchronous and channel estimating; Have based on non-data-aided algorithm and based on modes such as data-aided algorithms; Slower based on the general convergence rate of non-data-aided algorithm, and the algorithm realization is comparatively complicated, so this paper adopts based on data-aided algorithm; Its convergence rate is very fast, is applicable to the transfer of data of higher rate.In based on data-aided algorithm, generally carry out through the mode of inserting training sequence in the frame head position.Each training sequence is made up of different train words, is that transmitting terminal and receiving terminal are total to the sequence of knowing.Each train word is by unique word (Unique Word; UW) constitute, require to present randomness, and smooth amplitude response is arranged at frequency domain in time domain; (Constant Amplitude and Zero AutoCorrelation, CAZAC) sequence realizes UW by permanent envelope zero auto-correlation.It is less that the training sequence of forming is thus influenced by noise and frequency deviation, for synchronously and channel estimation method very suitable.

First training sequence TS1 is practised handwriting by the short training of a series of repetitions and forms, and is used for frame and arrives detection, thick sample-synchronous, thick frequency offset estimating.

Second removable 4 part that are divided into of training sequence TS2, every partial-length is 1/4 of data block length N.This part is used for bit synchronization.

The 3rd training sequence TS3 is made up of two identical train words, is used for thin frequency offset estimating, channel estimating.

In the synchronous process of receiving terminal, at first utilize said TS1 to carry out thick sample-synchronous, tentatively confirm sampled point, the sampling clock adjustment is carried out on the slotting ring road in then utilizing, and so far, has corrected sampling deviation; Carry out frame through algorithm then and arrive detection based on window energy; After detecting the valid data arrival; Utilize TS2 to carry out bit synchronization; Utilize TS3 to carry out Nonlinear Transformation in Frequency Offset Estimation (" frequency deviation " of this place " carrier wave " and aforementioned and back preferably is unified into " carrier wave frequency deviation " or other from the term angle).

Utilizing TS2 to carry out in the bit synchronous process; Employing is [A-A-A A] based on the train word structure that the bit-synchronization algorithm of training sequence: TS2 adopts; Whether can the algorithm with Schmidl & Cox (also adopt other algorithm earlier?); Half train word of preceding half train word and back is made related operation, and the sliding window size of this moment is N/2, draws a metrology platform M ₀

Because the existence of Cyclic Prefix has caused M ₀One section smooth platform is arranged, on this platform, judge M ₀Whether, work as M greater than certain fixed value ₀＞M _{Fixed value}The time, continue to adopt following algorithm to find the bit synchronization peak value.The fixed value of recommending can be set at 0.5, and is comparatively convenient when its value is used for the hardware realization.

Use improved Minn algorithm then, 4 train words of N/4 length carried out computing cross-correlation draw metrology platform:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}$

Among the present invention, such frame structure concise and succinct is fit to be applied to single-carrier frequency domain equalization system; And each train word can be realized different functions, and in addition, same train word can reuse in the different algorithms; Multiplexing technology can alleviate the burden of frame head, improves data transmission rate.

Bit-synchronization algorithm has a specific kurtosis, and other places beyond peak value, can not have other peaks again.Therefore help carrying out bit synchronous accurate judgement.In addition, in bit synchronous process, adopt synchronously preliminary and accurate synchronous two steps, can effectively quicken bit synchronous carrying out.

Description of drawings

Fig. 1 is single carrier frequency domain equalization (SC-FDE) system block diagram.

Fig. 2 is the frame structure of the single-carrier frequency domain equalization system of the embodiment of the invention.

Fig. 3 is the structure of first training sequence in the frame structure of the embodiment of the invention.

Fig. 4 is the structure of second training sequence in the frame structure of the embodiment of the invention.

Fig. 5 is the structure of the 3rd training sequence in the frame structure of the embodiment of the invention.

Fig. 6 is that the synchro system block diagram and the bit synchronization modular circuit thereof of the embodiment of the invention realizes block diagram.

Fig. 7 is the bit synchronous analogous diagram of the embodiment of the invention.

Fig. 8 is the structural representation of data buffering module.

Specific embodiments

Method for synchronous in single carrier frequency domain equalization (SC-FDE) system is divided into 3 training sequence TS1, TS2 and TS3 to the frame structure in the single-carrier frequency domain equalization system leading;

Each training sequence is made up of different train words, is that transmitting terminal and receiving terminal are total to the sequence of knowing, it is less that it receives noise and frequency shift (FS) to be that frequency deviation influences, and is applicable to synchronously and channel estimation method;

First training sequence TS1 is made up of the short training of a series of repetitions UW that practises handwriting, be used for frame arrive detect, thick sample-synchronous and thick Nonlinear Transformation in Frequency Offset Estimation; Second training sequence TS2 is used for bit synchronization; The 3rd training sequence TS3 is made up of two identical train words, is used for thin Nonlinear Transformation in Frequency Offset Estimation;

In the synchronous process of the receiving terminal of SC-FDE system, adopt three steps to realize: 1) at first to utilize TS1 to carry out thick sample-synchronous, tentatively confirm sampled point; The sampling clock adjustment is carried out on the slotting ring road in then utilizing; Carry out frame subsequently and arrive detection; 2) after detecting the valid data arrival, utilize TS2 to carry out bit synchronization; 3) utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation then, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation.

In the step 1); TS1 carries out thick sample-synchronous: the their cross correlation that the short training of utilization repetition is practised handwriting produces several peak values; And relatively the size of each peak value is found out the largest peaks position, and peak-peak place autocorrelation performance is the strongest, is the preliminary sample-synchronous point of confirming; TS1 carries out frame and arrives detection: adopt the algorithm based on window energy.

Step 2) in, said second training preface TS2 row are split as 4 parts, and 1/4 of the data block length N that every part train word length is the frame structure in the SC-FDE system splits the train word structure that obtains TS2 and is [A-A-A A].

Step 2) in, utilize TS2 to carry out bit synchronous process and adopt the bit-synchronization algorithm based on training sequence, step is following:

A) with the algorithm of Sehmidl & Cox, TS2 is divided into front and back two parts, is respectively [A-A] and [A A]; If the length of training sequence is N, then the length of each part is N/2 in the two parts of front and back; The train word of two parts is made related operation;

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r(d+m)*r(d+m+L),$ Wherein, L=N/2;

The energy of TS2 second portion train word [A A] is:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2;$

The sliding window size of this moment is N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2};$

B) with the metrology platform M of step a) gained ₀Drawing needs the further scope of search:

Because the existence of Cyclic Prefix has caused M ₀One section smooth platform is arranged, on this platform, judge M ₀Whether greater than certain fixed value M _{Fixed value}, work as M ₀＞M _{Fixed value}The time, continue to adopt following step 2.3) find the bit synchronization peak value;

C) with improved Minn algorithm, to 4 train word A of N/4 length ,-A ,-A and A carry out computing cross-correlation, and considers that the filtering edge still has the influence of peak value, the cross correlation algorithm of employing is following:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

At last, draw metrology platform:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}.$

For hardware is realized for simplicity said fixed value M _{Fixed value}Be 0.5.

In the step 3), TS3 is made up of two identical long train words, and total length is made as N, and then each long train word length is N/2, is used for carrying out thin Nonlinear Transformation in Frequency Offset Estimation; In the whole process of Nonlinear Transformation in Frequency Offset Estimation, practise handwriting as thick Nonlinear Transformation in Frequency Offset Estimation with last 2 short trainings of TS1, with the TS3 training sequence Nonlinear Transformation in Frequency Offset Estimation of running business into particular one.

Specific in this example, the present invention is further specified below in conjunction with accompanying drawing.

Fig. 1 is single carrier frequency domain equalization (SC-FDE) system block diagram.The single carrier transmission pattern of SC-FDE is different from other traditional single carrier transmission, and what it sent is the two-forty single-carrier signal after the modulation, and receiving terminal is realized frequency domain equalization through FFT and IFFT conversion, is actually frequency-domain analysis to received signal.This technology is based on the inspiration of OFDM, and the mode of employing frequency domain equalization greatly reduces the complexity of time domain equalization, has improved systematic function.Technical scheme of the present invention is exactly the sync section that is used for this system.

This routine single-carrier frequency domain equalization system frame structure is as shown in Figure 2, and it comprises leading and data block.Leadingly be divided into 3 training sequences:

First training sequence TS1 is made up of the short training of a series of repetitions UW that practises handwriting, and is as shown in Figure 3.

Second removable 4 part that are divided into of training sequence TS2, every partial-length is 1/4 of data block length N.This part is used for bit synchronization, and is as shown in Figure 4.

The 3rd training sequence TS3 is made up of two identical train words, and be as shown in Figure 5.

All training sequence TS1, TS2 and TS3 adopt aforementioned CAZAC sequence, and this sequence has amplitude response stably, and only in the auto-correlation at zero point, therefore have good autocorrelation performance, are very suitable for synchronously and channel estimating.

Comprise a kind of multiplex technique and a kind of bit-synchronization algorithm among the present invention, set forth respectively below based on train word.

1. the present invention proposes a kind of multiplex technique, realized that with three train words particular content is following synchronously based on train word:

In the synchronous process of receiving terminal, at first utilize first training sequence (TS1) to carry out thick sample-synchronous, tentatively confirm the sample-synchronous point, the sampling clock adjustment is carried out on the slotting ring road in then utilizing, and so far, sampling deviation has been corrected.Carry out frame through algorithm then and arrive detection based on window energy; After detecting the valid data arrival; Utilize second training sequence (TS2) to carry out bit synchronization; Utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation then, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation, the circuit structure diagram of synchronization module is as shown in Figure 6.

In this process, TS1 at first is used for thick sample-synchronous.Because the sampling clock adjusting module needs certain stabilization time, in order to shorten this time-delay, we tentatively confirm the position of sampling earlier with thick sample-synchronous module.In the process of thick sampling clock adjustment, the correlation properties of utilization targeting sequencing produce several peak values, and relatively the size of each peak value is found out the largest peaks position, are the preliminary sample-synchronous point of confirming.In the whole sample-synchronous algorithm, adopt thick sample-synchronous to confirm basic scope earlier, use the loop accurate tracking again, such method can be corrected sampling deviation more rapidly.

Then, TS1 is used for frame again and arrives detection, and the algorithm based on window energy that content is well known can well draw the frame due in.

At last, last 2 short trainings of TS1 are practised handwriting as thick frequency offset estimating.In the process of frequency offset estimating, for scope and the precision that guarantees frequency deviation, use short train word to do thick frequency offset estimating respectively, with the frequency deviation region that guarantees to detect, and with the frequency offset estimating of running business into particular one than long training sequence, to guarantee its precision.Because it is shorter that short training is practised handwriting, frequency offset estimation range is bigger, just is suitable for the detection of thick frequency deviation.

TS2 is as bit synchronization.In the bit-synchronization algorithm that the present invention proposes, used Schmidl & Cox algorithm and improved Minn algorithm, these two kinds of algorithms are different for the structural requirement of train word.And in the present invention,, adopted same train word structure in order to practice thrift the additional information of frame head, reach the requirement of algorithm with multiplexing mode.The implementation of specific algorithm is seen the 2nd summary of the invention.

TS3 is used for thin frequency offset estimating.This training sequence is a long training sequence, and purpose is exactly the realization of thin frequency offset estimating.In the process of channel estimating of back, also use this training sequence and estimate in addition, thereby reduced the burden of frame head, the effective transmission rate of the data of raising.

2. the present invention proposes a kind of bit-synchronization algorithm based on training sequence, particular content is following:

The train word structure that this sequence adopts is train word structure [A-A-A A], and is as shown in Figure 4.

Step 1: with the algorithm of Schmidl & Cox, train word TS2 is divided into front and back two parts, two parts are respectively [A-A] and [A A].If the length of training sequence is N, then the length of each part is N/2.The train word of two parts is made related operation.

Observe former and later two parts, find that the train word of second portion is equivalent to the negative value of first, that is to say two parts being done in the process of cross-correlation, still sharp-pointed correlation can be arranged, its difference only is P ₀(d) value is a negative value.And this asks metrology platform M in the back ₀The time less than the influence.

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r(d+m)*r(d+m+L)$

Wherein, L=N/2

The energy of second portion train word is:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2$

The sliding window size of this moment is N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2}$

Step 2: the metrology platform with the step 1 gained draws the scope that needs further search.

Because the existence of Cyclic Prefix has caused M ₀One section smooth platform is arranged, on this platform, judge M ₀Whether, work as M greater than certain fixed value ₀＞M _{Fixed value}The time, continue to adopt step 3 to find the bit synchronization peak value.

The metrology platform scope confirm that with signal to noise ratio be relevant, so this fixed value choose also relevant with signal to noise ratio.The fixed value of recommending can be set at 0.5, and is comparatively convenient when its value is used for the hardware realization.

Step 3: with improved Minn algorithm, 4 train words of N/4 length are carried out computing cross-correlation, and consider that the filtering edge still has the influence of peak value, the cross correlation algorithm of employing is following:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

At last, draw metrology platform:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}$

Fig. 6 is that the circuit of bit-synchronization algorithm is realized block diagram, and Fig. 7 is the analogous diagram of bit-synchronization algorithm.Can see that by figure benefit of the present invention is that bit-synchronization algorithm has a specific kurtosis, and other places beyond peak value, can there be other peaks again.Therefore help carrying out bit synchronous accurate judgement.In addition, in bit synchronous process, adopt synchronously preliminary and accurate synchronous two steps, can effectively quicken bit synchronous carrying out.

Schmidl & Cox algorithm and improvement Minn algorithm can adopt existing techniques in realizing among the present invention.

A kind of circuit of realizing said method comprises that thick sample-synchronous module, frame arrive detection module, bit synchronization module and carrier synchronization module; External data arrives the data after detection module, bit synchronization module and carrier synchronization module obtain synchronously through said thick sample-synchronous module, frame successively;

Said bit synchronization module comprises data buffering module, initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module;

The input data that arrive detection module from frame handle obtaining data A, B, r0, r1, r2 and r3 through the data buffering module; Wherein, A is former data, and B is that A is through the data after the N/2 time-delay; R0 is former data, and r1 is the data after r0 delays time through N/4, and r2 is the data after r0 delays time through N/2, and r3 is the data after the r0 process 3N/4 time-delay;

A, B import initial synchronization module into, handle to obtain M0;

R0, r1, r2 and r3 import accurate synchronization module into, handle to obtain M;

M0 and M import the bit synchronization determination module into, handle and obtain the sync bit arriving signal, and this signal imports control module into, handle obtaining the dateout enable signal;

Dateout enable signal control data buffer module is given the carrier synchronization module by data buffering module dateout.

Said data buffering module is made up of trigger, and initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module are mapped to general digital control circuit realization by the corresponding algorithm of the inventive method.

For the data buffering module:

This module need produce through data message A, B, r0, r1, r2, r3 after the different time delay, uses for subsequent module.Wherein, A is former data, and B is that A is through the data after the N/2 time-delay; R0 is former data, and r1 is the data after r0 delays time through N/4, and r2 is the data after r0 delays time through N/2, and r3 is the data after the r0 process 3N/4 time-delay.

Because A and r0 are same data (former data), r2 and B also are same data (data after the N/2 time-delay), so the circuit structure diagram of data buffering module can be a circuit as shown in Figure 8.Among the figure, d type flip flop is used as delay cell in this circuit; BitEnable is an enable signal.

Claims (7)

1. the method for synchronous in single carrier frequency domain equalization (SC-FDE) system is characterized in that being divided into 3 training sequence TS1, TS2 and TS3 to the frame structure in the single-carrier frequency domain equalization system leading;

Each training sequence is made up of different train words, is that transmitting terminal and receiving terminal are total to the sequence of knowing, it is less that it receives noise and frequency shift (FS) to be that frequency deviation influences, and is applicable to synchronously and channel estimation method;

First training sequence TS1 is made up of the short training of a series of repetitions UW that practises handwriting, be used for frame arrive detect, thick sample-synchronous and thick Nonlinear Transformation in Frequency Offset Estimation; Second training sequence TS2 is used for bit synchronization; The 3rd training sequence TS3 is made up of two identical train words, is used for thin Nonlinear Transformation in Frequency Offset Estimation;

In the synchronous process of the receiving terminal of SC-FDE system, adopt three steps to realize: 1) at first to utilize TS1 to carry out thick sample-synchronous, tentatively confirm sampled point; The sampling clock adjustment is carried out on the slotting ring road in then utilizing; Carry out frame subsequently and arrive detection; 2) after detecting the valid data arrival, utilize TS2 to carry out bit synchronization; 3) utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation then, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation.

2. based on the method for synchronous in the described single-carrier frequency domain equalization system of claim 1; It is characterized in that in the said step 1); TS1 carries out thick sample-synchronous: the cross correlation that the short training of utilization repetition is practised handwriting produces several peak values; And relatively the size of each peak value is found out the largest peaks position; Peak-peak place autocorrelation performance is the strongest, is the preliminary sample-synchronous point of confirming;

TS1 carries out frame and arrives detection: adopt the algorithm based on window energy.

3. the method for synchronous in the single-carrier frequency domain equalization system according to claim 1; It is characterized in that said step 2) in; Said second training preface TS2 row are split as 4 parts; 1/4 of the data block length N that every part train word length is the frame structure in the SC-FDE system splits the train word structure that obtains TS2 and is [A-A-A A].

4. the method for synchronous in the single-carrier frequency domain equalization system according to claim 3 is characterized in that said step 2) in, to utilize TS2 to carry out bit synchronous process and adopt bit-synchronization algorithm based on training sequence, step is following:

A) with the algorithm of Sehmidl&Cox, TS2 is divided into front and back two parts, is respectively [A-A] and [A A]; If the length of training sequence is N, then the length of each part is N/2 in the two parts of front and back; The train word of two parts is made related operation;

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r(d+m)*r(d+m+L),$ Wherein, L=N/2;

The energy of TS2 second portion train word [A A] is:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2;$

The sliding window size of this moment is N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2};$

B) with the metrology platform M of step a) gained ₀Drawing needs the further scope of search:

Because the existence of Cyclic Prefix has caused M ₀One section smooth platform is arranged, on this platform, judge M ₀Whether greater than certain fixed value M _{Fixed value}, work as M ₀＞M _{Fixed value}The time, continue to adopt following step 2.3) find the bit synchronization peak value;

C) with improved Minn algorithm, to 4 train word A of N/4 length ,-A ,-A and A carry out computing cross-correlation, and considers that the filtering edge still has the influence of peak value, the cross correlation algorithm of employing is following:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

At last, draw metrology platform:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}.$

5. the method for synchronous in the single-carrier frequency domain equalization system according to claim 4 is characterized in that realizing for simplicity said fixed value M for hardware _{Fixed value}Be 0.5.

6. based on the method for synchronous in the described single-carrier frequency domain equalization system of claim 1; It is characterized in that in the said step 3) that TS3 is made up of two identical long train words, total length is made as N; Then each long train word length is N/2, is used for carrying out thin Nonlinear Transformation in Frequency Offset Estimation;

In the whole process of Nonlinear Transformation in Frequency Offset Estimation, practise handwriting as thick Nonlinear Transformation in Frequency Offset Estimation with last 2 short trainings of TS1, make thin Nonlinear Transformation in Frequency Offset Estimation with the TS3 training sequence.

7. a circuit of realizing the arbitrary said method of claim 1～6 is characterized in that comprising that thick sample-synchronous module, frame arrive detection module, bit synchronization module and carrier synchronization module; External data arrives the data after detection module, bit synchronization module and carrier synchronization module obtain synchronously through said thick sample-synchronous module, frame successively;

Said bit synchronization module comprises data buffering module, initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module;

The input data that arrive detection module from frame handle obtaining data A, B, r0, r1, r2 and r3 through the data buffering module; Wherein, A is former data, and B is that A is through the data after the N/2 time-delay; R0 is former data, and r1 is the data after r0 delays time through N/4, and r2 is the data after r0 delays time through N/2, and r3 is the data after the r0 process 3N/4 time-delay;

A, B import initial synchronization module into, handle to obtain M0;

R0, r1, r2 and r3 import accurate synchronization module into, handle to obtain M;

M0 and M import the bit synchronization determination module into, handle and obtain the sync bit arriving signal, and this signal imports control module into, handle obtaining the dateout enable signal;

Dateout enable signal control data buffer module is given the carrier synchronization module by data buffering module dateout.

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