CN102594745B - Synchronization method for single carrier frequency domain equalization system and realization circuit thereof - Google Patents

Abstract

The invention discloses a synchronization method for a single carrier frequency domain equalization system, which comprises a multiplex technique and a bit synchronization method based on training characters. According to the method, three training characters are added at a frame head and used for completing various types of synchronization and signaling estimation algorithm, so that the load of the frame head is lowered, and effective transmission rate of data is improved. The invention discloses bit synchronization algorithm, and the algorithm is divided into an initial synchronism and accurate synchronization, after the range of the initial synchronism is confirmed, an accurate synchronization position is found out in the range by adopting accurate synchronization method, compared with a conventional bit synchronization method, other peak value of the algorithm can not exist out the range of the initial synchronization, and the algorithm has more accurate bit synchronization position judegement ability and has more high working efficiency.

Description

Synchronous method in single-carrier frequency domain equalization system and realizing circuit thereof

Technical field

The present invention relates to wireless communication field, as wireless sensor network, system of broadband wireless communication etc., particularly relate to a kind of synchronous method based on single carrier frequency domain equalization (Single Carrier System with Frequency Domain Equalization, SC-FDE) technology.

Background technology

Radio communication experienced by the very fast development from analog communication to digital communication, from FDMA to CDMA, is the industry that technology innovation is the fastest, market capacity is maximum.Development of Wireless Communications is to today, and more and more service content proposes more and more higher requirement to message transmission rate, and frequency spectrum resource wretched insufficiency has become the bottleneck of restriction radio communication career development day by day.Although Generation Mobile Telecommunication System than existing transmission rate thousands of times soon, still can cannot meet the requirement of Future Multimedia communication.Therefore, how fully to develop limited frequency spectrum resource, improve the availability of frequency spectrum, become one of focus of current wireless communication technology research.While utilance is dived in raising frequently, the reliability that guarantee is transmitted also is an important problem.Following wireless communications application has higher requirement to applied environment, and this just needs new wireless communication technology can adapt to more severe channel, can overcome various adverse effect.

Wireless communication technology is employed in multiple different system, as wireless sensor network, system of broadband wireless communication etc.Wireless sensor network (WSN) is a kind of brand-new information acquisition platform, can the information of various detected objects in Real-Time Monitoring and collection network distributed areas, and these information are sent to gateway node, to realize complicated specified scope internal object detection and tracking, there is the features such as rapid deployment, survivability be strong, have broad application prospects.Along with the development of radio sensing network, the transfer of data of higher rate becomes and is necessary very much, especially the transmission of burst packet, needs the application demand adapting to Sensor Network flexible deployment, low cost, small size.In addition, Wideband Wireless Digital Communication is also the frontier development of Current wireless communication technology, has broad application prospects in the voice in future, video, the integrated service such as data and multimedia.

There is the David Falconer that the research representing meaning is the research institutions such as Ka Ledun (Carleton) universities in 2002 in the bit synchronization of single carrier frequency domain equalization, Sirikiat Lek Ariyavisitakul, " Frequency Domain Equalization for Single-Carrier Broadband Wireless Systems " paper that the scholars such as Anader Benyamin-Seeyar deliver at IEEE Communications Magazine, single carrier frequency domain equalization (SC-FDE) technology is proposed in literary composition, this technology can at wireless sensor network, obtain in the systems such as broadband wireless communications and use flexibly, it has lower peak-to-average force ratio and the sensitiveness of phase noise, reduce power consumption and the cost of the analogue devices such as power amplifier, and under the propagation conditions that there is time delay spread, SC-FDE system can obtain the performance approximate with ofdm system, SC-FDE systems radiate end structure is simple simultaneously, reduces the power consumption of transmitting terminal.Therefore, SC-FDE system can be widely used in wireless communication system.Thereafter in succession occur that some documents expand the every key technology in SC-FDE system in depth to discuss.

In SC-FDE system, it is synchronously a very crucial step.SC-FDE system is very responsive to synchronous error (especially bit synchronization error).For the phase deviation of sampling clock, transforming to after frequency domain through FFT, be equivalent to the phase rotating of each code element, is the interference of multiplicative, can be corrected come by frequency domain equalization; The frequency departure of sampling clock, is transformed on frequency domain and is equivalent to introduce inter-carrier interference, cannot be compensated by frequency domain equalization, and IFFT switches back to the same presence bit synchronous error of the signal after time domain, there is very large interference for judgement.In addition, the frequency shift (FS) (frequency deviation) of sampling clock also can cause the timing wander of signal, affects synchronous performance.Therefore, the synchronization module of SC-FDE system, bit synchronization module especially is wherein one of key technology of whole system design.

Summary of the invention

In order to solve the above-mentioned problems in the prior art, the present invention proposes a kind of bit synchronization method based on single-carrier wave frequency domain equalization technology newly, and concrete technical scheme is as follows:

Adopt a kind of multiplex technique based on train word, achieve in single carrier frequency domain equalization (SC-FDE) system with three groups of training sequences synchronous, specifically, be that the leading of the frame structure in SC-FDE system is divided into 3 training sequences TS1, TS2 and TS3;

In the algorithm of synchronous and channel estimating, have based on the algorithm of unbound nucleus and based on modes such as data-aided algorithms, the general convergence rate of algorithm based on unbound nucleus is slower, and algorithm realization is comparatively complicated, therefore adopt herein based on data-aided algorithm, its convergence rate is very fast, is applicable to the transfer of data of higher rate.Based in data-aided algorithm, generally by carrying out in the mode of frame header position insertion training sequence.Each training sequence is made up of different train words, is transmitting terminal and receiving terminal sequence in common knowledge.Each train word is by unique word (Unique Word, UW) form, require to present randomness in time domain, and have smooth amplitude response at frequency domain, UW is realized by permanent envelope zero auto-correlation (Constant Amplitude and Zero AutoCorrelation, CAZAC) sequence.The training sequence formed thus affects less by noise and frequency deviation, for synchronous and channel estimation method is very applicable.

First training sequence TS1 is practised handwriting by the short training of a series of repetition and forms, and arrives detection, thick sample-synchronous, coarse frequency offset for frame.

Second training sequence TS2 is removable is divided into 4 parts, and every partial-length is 1/4 of data block length N.This part is used for bit synchronization.

3rd training sequence TS3 is made up of two identical train words, estimates, channel estimating for thin frequency deviation.

In the process that receiving terminal is synchronous, first utilize described TS1 to carry out thick sample-synchronous, tentatively determine sampled point, then utilize interpolation loop to carry out sampling clock adjustment, so far, correct for sampling deviation; Then detection is arrived by carrying out frame based on the algorithm of window energy, after detecting that valid data arrive, TS2 is utilized to carry out bit synchronization, utilize TS3 carry out Nonlinear Transformation in Frequency Offset Estimation (this place " carrier wave " and aforementioned and " frequency deviation " below, preferably from term angle carry out being unified into " carrier wave frequency deviation " or other).

Carry out in bit synchronous process utilizing TS2, adopt the bit-synchronization algorithm based on training sequence: the train word structure that TS2 adopts is [A-A-A A], first use the algorithm of Schmidl & Cox (whether also can adopt other algorithm?), front half train word and rear half train word are made related operation, sliding window size is now N/2, draws a metrology platform M ₀.

Because the existence of Cyclic Prefix, result in M ₀there is the platform that a section smooth, this platform judges M ₀whether be greater than certain fixed value, work as M ₀> M _{fixed value}time, continue to adopt following algorithm to find bit synchronization peak value.Recommend fixed value can be set as 0.5, its value be used for hardware implementing time more for convenience.

Then with the Minn algorithm improved, computing cross-correlation is carried out to 4 train words of N/4 length and draws metrology platform:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}$

In the present invention, such frame structure concise and succinct, is applicable to being applied to single-carrier frequency domain equalization system, and each train word can realize different functions, in addition, same train word can reuse in different algorithms, multiplexing technology can alleviate the burden of frame head, improves data transmission rate.

Bit-synchronization algorithm has specific one kurtosis, and other places beyond peak value, other peaks can not be there is again.Therefore be conducive to carrying out bit synchronous accurate judgement.In addition, in bit synchronous process, adopt preliminary synchronisation and accurate synchronization two steps, effectively can accelerate bit synchronous carrying out.

Accompanying drawing explanation

Fig. 1 is single carrier frequency domain equalization (SC-FDE) system block diagram.

Fig. 2 is the frame structure of the single-carrier frequency domain equalization system of the embodiment of the present invention.

Fig. 3 is the structure of first training sequence in the frame structure of the embodiment of the present invention.

Fig. 4 is the structure of second training sequence in the frame structure of the embodiment of the present invention.

Fig. 5 is the structure of the 3rd training sequence in the frame structure of the embodiment of the present invention.

Fig. 6 is that the synchro system block diagram of the embodiment of the present invention and bit synchronization modular circuit thereof realize block diagram.

Fig. 7 is the bit synchronous analogous diagram of the embodiment of the present invention.

Fig. 8 is the structural representation of data buffering module.

Specific embodiments

Synchronous method in single carrier frequency domain equalization (SC-FDE) system, is divided into 3 training sequences TS1, TS2 and TS3 the leading of the frame structure in single-carrier frequency domain equalization system;

Each training sequence is made up of different train words, is transmitting terminal and receiving terminal sequence in common knowledge, and it affects less by noise and frequency shift (FS) and frequency deviation, is applicable to synchronous and channel estimation method;

First training sequence TS1 is made up of the short training of a series of repetition UW that practises handwriting, arrive for frame detect, thick sample-synchronous and thick Nonlinear Transformation in Frequency Offset Estimation; Second training sequence TS2 is used for bit synchronization; 3rd training sequence TS3 is made up of, for thin Nonlinear Transformation in Frequency Offset Estimation two identical train words;

In the process that the receiving terminal of SC-FDE system is synchronous, three steps are adopted to realize: 1) first to utilize TS1 to carry out thick sample-synchronous, tentatively determine sampled point; Then interpolation loop is utilized to carry out sampling clock adjustment; Carry out frame subsequently and arrive detection; 2) after detecting that valid data arrive, TS2 is utilized to carry out bit synchronization; 3) then utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation.

Step 1) in, TS1 carries out thick sample-synchronous: the their cross correlation using the short training repeated to practise handwriting produces several peak value, and the size of more each peak value finds out maximum peak value position, peak-peak place autocorrelation performance is the strongest, is the sample-synchronous point tentatively determined; TS1 carries out frame and arrives detection: adopt the algorithm based on window energy.

Step 2) in, described second training sequence TS2 row are split as 4 parts, and every part train word length is 1/4 of the data block length N of frame structure in SC-FDE system, and splitting the train word structure obtaining TS2 is [A-A-A A].

Step 2) in, utilize TS2 to carry out the bit-synchronization algorithm of bit synchronous process employing based on training sequence, step is as follows:

A) with the algorithm of Sehmidl & Cox, TS2 is divided into front and back two parts, is respectively [A-A] and [-A A]; If the length of training sequence is N, then before and after, in two parts, the length of each part is N/2; The train word of two parts is made related operation;

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r(d+m)*r(d+m+L),$ Wherein, L=N/2;

The energy of TS2 Part II train word [-A A] is:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2;$

Sliding window size is now N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2};$

B) the metrology platform M of step a) gained is used ₀draw the scope needing search further:

Because the existence of Cyclic Prefix, result in M ₀there is the platform that a section smooth, this platform judges M ₀whether be greater than certain fixed value M _{fixed value}, work as M ₀> M _{fixed value}time, continue to adopt following step 2.3) find bit synchronization peak value;

C) with the Minn algorithm improved, carry out computing cross-correlation to 4 train word A ,-A ,-A and A of N/4 length, and consider that filtering edge still has the impact of peak value, the cross correlation algorithm of employing is as follows:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

Finally, metrology platform is drawn:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}.$

For the purpose of hardware implementing is simple, described fixed value M _{fixed value}be 0.5.

Step 3) in, TS3 is made up of two identical long train words, and total length is set to N, then each long train word length is N/2, is used for carrying out thin Nonlinear Transformation in Frequency Offset Estimation; In the whole process of Nonlinear Transformation in Frequency Offset Estimation, practise handwriting as thick Nonlinear Transformation in Frequency Offset Estimation with last 2 short trainings of TS1, to run business into particular one Nonlinear Transformation in Frequency Offset Estimation with TS3 training sequence.

Specific in this example, below in conjunction with accompanying drawing, the present invention will be further described.

Fig. 1 is single carrier frequency domain equalization (SC-FDE) system block diagram.The single carrier transmission mode of SC-FDE is different from other traditional single carrier transmission, its send be modulation after two-forty single-carrier signal, receiving terminal by FFT and IFFT conversion realize frequency domain equalization, be actually frequency-domain analysis to received signal.This technology is the inspiration based on OFDM, adopts the mode of frequency domain equalization to greatly reduce the complexity of time domain equalization, improves systematic function.Technical solution of the present invention is exactly the sync section for this system.

As shown in Figure 2, it comprises leading and data block to the single-carrier frequency domain equalization system frame structure of this example.Leadingly be divided into 3 training sequences:

First training sequence TS1 is made up of the short training of a series of repetition UW that practises handwriting, as shown in Figure 3.

Second training sequence TS2 is removable is divided into 4 parts, and every partial-length is 1/4 of data block length N.This part is used for bit synchronization, as shown in Figure 4.

3rd training sequence TS3 is made up of two identical train words, as shown in Figure 5.

All training sequence TS1, TS2 and TS3 adopt aforementioned CAZAC sequence, and this sequence has stable amplitude response, and only in auto-correlation at zero point, therefore have good autocorrelation performance, are very suitable for synchronous and channel estimating.

The present invention comprises a kind of multiplex technique based on train word and a kind of bit-synchronization algorithm, sets forth respectively below.

1. the present invention proposes a kind of multiplex technique based on train word, achieve synchronously with three train words, particular content is as follows:

In the process that receiving terminal is synchronous, first utilize first training sequence (TS1) to carry out thick sample-synchronous, tentatively determine sample-synchronous point, then utilize interpolation loop to carry out sampling clock adjustment, so far, sampling deviation correct for.Then detection is arrived by carrying out frame based on the algorithm of window energy, after detecting that valid data arrive, second training sequence (TS2) is utilized to carry out bit synchronization, then utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation, the circuit structure diagram of synchronization module as shown in Figure 6.

In the process, TS1 is first for thick sample-synchronous.Because sampling clock adjusting module needs certain stabilization time, in order to shorten this time delay, we first tentatively determine the position of sampling by thick sample-synchronous module.In the process that thick sampling clock adjusts, use the correlation properties of targeting sequencing to produce several peak value, and the size of more each peak value find out maximum peak value position, is the sample-synchronous point tentatively determined.In whole sample-synchronous algorithm, adopt thick sample-synchronous first to determine basic scope, then use loop accurate tracking, such method can correct sampling deviation more rapidly.

Then, TS1 arrives for frame again and detects, and the algorithm based on window energy that content is well known, can well draw frame due in.

Finally, last 2 short trainings of TS1 are practised handwriting as coarse frequency offset.In the process that frequency deviation is estimated, in order to ensure scope and the precision of frequency deviation, doing coarse frequency offset with shorter train word respectively, to ensure the frequency deviation region detected, and to run business into particular one frequency deviation estimation with longer training sequence, to ensure its precision.Because short training is practised handwriting shorter, frequency offset estimation range is comparatively large, is just suitable for the detection of thick frequency deviation.

TS2 is used as bit synchronization.In the bit-synchronization algorithm that the present invention proposes, used the Minn algorithm of Schmidl & Cox algorithm and improvement, these two kinds of algorithms are different for the structural requirement of train word.And in the present invention, in order to save the additional information of frame head, have employed same train word structure, the requirement of algorithm is reached by multiplexing mode.The implementation of specific algorithm is shown in the 2nd summary of the invention.

TS3 is used for thin frequency deviation and estimates.This training sequence is long training sequence, and object is exactly the realization that thin frequency deviation is estimated.In addition in the process of channel estimating below, also use this training sequence to estimate, thus reduce the burden of frame head, the effective transmission rate of the data of raising.

2. the present invention proposes a kind of bit-synchronization algorithm based on training sequence, particular content is as follows:

The train word structure that this sequence adopts is train word structure [A-A-A A], as shown in Figure 4.

Step one: with the algorithm of Schmidl & Cox, train word TS2 is divided into front and back two parts, and two parts are respectively [A-A] and [-A A].If the length of training sequence is N, then the length of each part is N/2.The train word of two parts is made related operation.

Observe former and later two parts, find that the train word of Part II is equivalent to the negative value of Part I, that is, doing in the process of cross-correlation to two parts, still can have sharp-pointed correlation, its difference is only P ₀d the value of () is negative value.And this asks metrology platform M later ₀time be do not have influential.

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r(d+m)*r(d+m+L)$

Wherein, L=N/2

The energy of Part II train word is:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2$

Sliding window size is now N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2}$

Step 2: draw the scope needing search further by the metrology platform of step one gained.

Because the existence of Cyclic Prefix, result in M ₀there is the platform that a section smooth, this platform judges M ₀whether be greater than certain fixed value, work as M ₀> M _{fixed value}time, continue to adopt step 3 to find bit synchronization peak value.

Determination and the signal to noise ratio of metrology platform scope are relevant, therefore this fixed value choose also relevant to signal to noise ratio.Recommend fixed value can be set as 0.5, its value be used for hardware implementing time more for convenience.

Step 3: with the Minn algorithm improved, carry out computing cross-correlation to 4 train words of N/4 length, and consider that filtering edge still has the impact of peak value, the cross correlation algorithm of employing is as follows:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}r*(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

Finally, metrology platform is drawn:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}$

Fig. 6 is the circuit realiration block diagram of bit-synchronization algorithm, and Fig. 7 is the analogous diagram of bit-synchronization algorithm.Can be seen by figure, benefit of the present invention is, bit-synchronization algorithm has specific one kurtosis, and other places beyond peak value, other peaks can not be there is again.Therefore be conducive to carrying out bit synchronous accurate judgement.In addition, in bit synchronous process, adopt preliminary synchronisation and accurate synchronization two steps, effectively can accelerate bit synchronous carrying out.

In the present invention, Schmidl & Cox algorithm and improvement Minn algorithm can adopt existing techniques in realizing.

Realize a circuit for said method, comprise thick sample-synchronous module, frame arrives detection module, bit synchronization module and carrier synchronization module; External data arrives detection module, bit synchronization module and carrier synchronization module obtain the data synchronously through described thick sample-synchronous module, frame successively;

Described bit synchronization module comprises data buffering module, initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module;

Arrive the input data of detection module through data buffering module from frame, process obtains data A, B, r0, r1, r2 and r3; Wherein, A is former data, and B is the data of A after N/2 time delay; R0 is former data, and r1 is the data of r0 after N/4 time delay, and r2 is the data of r0 after N/2 time delay, and r3 is the data of r0 after 3N/4 time delay;

A, B import initial synchronization module into, and process obtains M0;

R0, r1, r2 and r3 import accurate synchronization module into, and process obtains M;

M0 and M imports bit synchronization determination module into, and process obtains sync bit arriving signal, and this signal imports control module into, and process obtains exporting data enable signal;

Export data enable signal control data buffer module, export data to carrier synchronization module by data buffering module.

Described data buffering module is made up of trigger, and initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module become general digital control circuit to realize by the Algorithm mapping of the correspondence of the inventive method.

For data buffering module:

This module needs to produce data message A, B, r0, r1, r2, the r3 after different time delays, uses for subsequent module.Wherein, A is former data, and B is the data of A after N/2 time delay; R0 is former data, and r1 is the data of r0 after N/4 time delay, and r2 is the data of r0 after N/2 time delay, and r3 is the data of r0 after 3N/4 time delay.

Because A and r0 is same data (former data), r2 and B is also same data (data after N/2 time delay), therefore the circuit structure diagram of data buffering module can be circuit as shown in Figure 8.In figure, d type flip flop is used as delay cell in this circuit; BitEnable is an enable signal.

Claims (5)

1. the synchronous method in single carrier frequency domain equalization (SC-FDE) system, is characterized in that the leading of the frame structure in single-carrier frequency domain equalization system to be divided into 3 training sequences TS1, TS2 and TS3;

Each training sequence is made up of different train words, is transmitting terminal and receiving terminal sequence in common knowledge, and it affects less by noise and frequency shift (FS) and frequency deviation, is applicable to synchronous and channel estimation method;

First training sequence TS1 is made up of the short training of a series of repetition UW that practises handwriting, arrive for frame detect, thick sample-synchronous and thick Nonlinear Transformation in Frequency Offset Estimation; Second training sequence TS2 is used for bit synchronization; 3rd training sequence TS3 is made up of, for thin Nonlinear Transformation in Frequency Offset Estimation two identical train words;

In the process that the receiving terminal of SC-FDE system is synchronous, three steps are adopted to realize: 1) first to utilize TS1 to carry out thick sample-synchronous, tentatively determine sampled point; Then interpolation loop is utilized to carry out sampling clock adjustment; Carry out frame subsequently and arrive detection; 2) after detecting that valid data arrive, TS2 is utilized to carry out bit synchronization; 3) then utilize TS1 to carry out thick Nonlinear Transformation in Frequency Offset Estimation, utilize TS3 to carry out thin Nonlinear Transformation in Frequency Offset Estimation;

Described step 2) in, described second training sequence TS2 row are split as 4 parts, and every part train word length is 1/4 of the data block length N of frame structure in SC-FDE system, and splitting the train word structure obtaining TS2 is [A – A – A A];

Described step 2) in, utilize TS2 to carry out the bit-synchronization algorithm of bit synchronous process employing based on training sequence, step is as follows:

A) with the algorithm of Schmidl & Cox, TS2 is divided into front and back two parts, is respectively [A – A] and [– A A]; If the length of training sequence is N, then before and after, in two parts, the length of each part is N/2; The train word of two parts is made related operation;

Two-part correlation is:

$P_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}r{(d+m)}^{*}r(d+m+L),$ Wherein, L=N/2;

TS2 Part II train word [– A A] energy be:

$R_0\left(d\right)=\underset{m=0}{\overset{L-1}{\mathrm{\Σ}}}{\left|r(d+m+L)\right|}^2;$

Sliding window size is now N/2, draws a metrology platform M ₀:

$M_0\left(d\right)=\frac{{\left|P_0\left(d\right)\right|}^2}{{\left(R_0\left(d\right)\right)}^2};$

B) the metrology platform M of step a) gained is used ₀draw the scope needing search further:

Because the existence of Cyclic Prefix, result in M ₀there is the platform that a section smooth, this platform judges M ₀whether be greater than certain fixed value M _{fixed value}, work as M ₀>M _{fixed value}time, continue to adopt following step c) find bit synchronization peak value;

C) with the Minn algorithm improved, carry out computing cross-correlation to 4 train word A, – A, – A and A of N/4 length, and consider that filtering edge still has the impact of peak value, the cross correlation algorithm of employing is as follows:

$P_1\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}{r}^{*}(d+m)\·r(d+m+\frac{3}{4}N)$

$P_2\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}{r}^{*}(d+m+\frac{1}{4}N)\·r(d+m+\frac{1}{2}N)$

$P_3\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}{r}^{*}(d+m)\·r(d+m+\frac{1}{2}N)$

$P_4\left(d\right)=\underset{m=0}{\overset{N/4-1}{\mathrm{\Σ}}}{r}^{*}(d+m+\frac{1}{4}N)\·r(d+m+\frac{3}{4}N)$

Draw thus:

P(d)＝P ₁(d)+P ₂(d)-P ₃(d)-P ₄(d)

$R\left(d\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{\left|r(d+m)\right|}^2$

Finally, metrology platform is drawn:

$M\left(d\right)=\frac{{\left|P\left(d\right)\right|}^2}{{\left(R\left(d\right)\right)}^2}.$

2. the synchronous method in single-carrier frequency domain equalization system according to claim 1, it is characterized in that described step 1) in, TS1 carries out thick sample-synchronous: the their cross correlation using the short training repeated to practise handwriting produces several peak value, and the size of more each peak value finds out maximum peak value position, peak-peak place autocorrelation performance is the strongest, is the sample-synchronous point tentatively determined;

TS1 carries out frame and arrives detection: adopt the algorithm based on window energy.

3. the synchronous method in single-carrier frequency domain equalization system according to claim 1, is characterized in that for the purpose of hardware implementing is simple, described fixed value M _{fixed value}be 0.5.

4. the synchronous method in single-carrier frequency domain equalization system according to claim 1, it is characterized in that described step 3) in, TS3 is made up of two identical long train words, and total length is set to N, then each long train word length is N/2, is used for carrying out thin Nonlinear Transformation in Frequency Offset Estimation;

In the whole process of Nonlinear Transformation in Frequency Offset Estimation, practise handwriting as thick Nonlinear Transformation in Frequency Offset Estimation with last 2 short trainings of TS1, make thin Nonlinear Transformation in Frequency Offset Estimation with TS3 training sequence.

5. realize a circuit for the arbitrary described method of Claims 1 to 4, it is characterized in that comprising thick sample-synchronous module, frame arrives detection module, bit synchronization module and carrier synchronization module; External data arrives detection module, bit synchronization module and carrier synchronization module obtain the data synchronously through described thick sample-synchronous module, frame successively;

Described bit synchronization module comprises data buffering module, initial bit synchronization module, accurate synchronization module, bit synchronization determination module and control module;

Arrive the input data of detection module through data buffering module from frame, process obtains data A, B, r0, r1, r2 and r3; Wherein, A is former data, and B is the data of A after N/2 time delay; R0 is former data, and r1 is the data of r0 after N/4 time delay, and r2 is the data of r0 after N/2 time delay, and r3 is the data of r0 after 3N/4 time delay;

A, B import initial synchronization module into, and process obtains M0;

R0, r1, r2 and r3 import accurate synchronization module into, and process obtains M;

M0 and M imports bit synchronization determination module into, and process obtains sync bit arriving signal, and this signal imports control module into, and process obtains exporting data enable signal;

Export data enable signal control data buffer module, export data to carrier synchronization module by data buffering module.