CN106888065A - A kind of clock synchronizing method and terminal - Google Patents
A kind of clock synchronizing method and terminal Download PDFInfo
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- CN106888065A CN106888065A CN201710135239.3A CN201710135239A CN106888065A CN 106888065 A CN106888065 A CN 106888065A CN 201710135239 A CN201710135239 A CN 201710135239A CN 106888065 A CN106888065 A CN 106888065A
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- sampled point
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
Abstract
The embodiment of the present invention provides a kind of clock synchronizing method and terminal, and clock synchronizing method includes：The first transmission frame that the second terminal that reception is connected with the first terminal sends, first transmission frame includes pilot frequency sequence and user data；Wherein, at least a portion data of pilot frequency sequence can be used as the Cyclic Prefix in the first transmission frame, the multi-path jamming for eliminating transmission channel between the first terminal and the second terminal；Based on the first transmission frame, obtain time difference information, the phase difference that time difference information is used between the first clock signal for indicating the second terminal produced when the first transmission frame is sent and the first terminal second clock signal produced when the first transmission frame is received；Based on time difference information, it is determined that the first sampled point sampled to user data in the first transmission frame, and to the second sampled point that pilot frequency sequence in the first transmission frame is sampled；Based on the first sampled point and the second sampled point, realize that the clock between the first terminal and the second terminal is synchronous.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of clock synchronizing method and terminal.
Background technology
The communication technology has particularly obtained significant progress in nearest decades since nineteen nineties, right
People's daily life, the development of national economy produce far-reaching influence.And in future communication technologies just towards the side of bandwidth high speed
During to development, many broadband digital transmission technologies are of great interest, such as OFDM (Orthogonal
Frequency Division Multiplexing, OFDM), frequency domain equalization single carrier (Single Carrier With
Frequency Domain Equalization, SC-FDE) etc..
At present, the clock of SC-FDE systems is synchronously generally used based on data-aided clock synchronizing method, that is, send out
Sending end first sends fixed sequence program known to a section before data frame is sent, and receiving terminal is locally transported with identical fixed sequence program
Calculate, go out after the fixed sequence program sent by transmitting terminal that receiving terminal the is received fixed sequence program local with receiving terminal is completely overlapped
Existing maximum correlation peak, now can determine that the first sampling point of data frame, and then data frame is adopted since first sampling point
Sample, realizes clock synchronization.Fig. 5 is may refer to, SC-FDE systems are based on data-aided clock synchronizing method, the transmission of its system
Frame structure generally realizes that one can be used for clock synchronization, and one can be used for offset estimation, and its using two preamble words
Frame structure is used to do anti-multipath after being mapped by symbol, it is necessary to insert extra protection interval according to the frame format of regulation
Disturb, and the part of two preamble words and protection interval cannot be used for transmitting effective communication data, so that data are opened
Pin is larger, and communication efficiency is relatively low.
In sum, there is accessing cost for data greatly in clock synchronizing method of the prior art, so as to cause communication efficiency relatively low
Technical problem.
The content of the invention
The embodiment of the present invention provides a kind of clock synchronizing method and terminal, is used to solve clock synchronization side of the prior art
There is accessing cost for data greatly in method, so as to the technical problem for causing communication efficiency relatively low.
On the one hand, the embodiment of the present invention provides a kind of clock synchronizing method, including：
The first transmission frame that the second terminal that reception is connected with first terminal sends, first transmission frame includes leading
Frequency sequence and user data；Wherein, at least a portion data of the pilot frequency sequence can be used as in first transmission frame
Cyclic Prefix, the multipath that the Cyclic Prefix is used to eliminate transmission channel between first terminal and second terminal is done
Disturb；Based on first transmission frame, time difference information is obtained, the time difference information is used to indicate second terminal to exist
The first produced clock signal is receiving first transmission frame with first terminal when sending first transmission frame
When produced second clock signal between phase difference；Based on the time difference information, it is determined that to first transmission frame
Described in user data the first sampled point for being sampled, and pilot frequency sequence described in first transmission frame is sampled
Second sampled point；Based on first sampled point and second sampled point, realize first terminal with second terminal
Between clock synchronization.
Optionally, first transmission frame also includes taking a Fast Fourier Transform (FFT) FFT of first transmission frame
The synchronizing sequence of symbol, the synchronizing sequence at least can be used to indicate that the pilot frequency sequence rising in first transmission frame
Beginning position.
Optionally, based on first transmission frame, time difference information is obtained, including：Based on first transmission frame, really
The data message of fixed first transmission frame, the data message includes amplitude information and phase information；Passed based on described first
The data message of defeated frame, calculates the phase difference between first clock signal and the second clock signal；Based on the phase
Potential difference, obtains time difference information.
Optionally, based on the time difference information, it is determined that being adopted to user data described in first transmission frame
First sampled point of sample, including：Based on the time difference information, determined to institute in first transmission frame by curve matching
State the first sampled point that user data is sampled.
Optionally, based on the time difference information, it is determined that being adopted to pilot frequency sequence described in first transmission frame
Second sampled point of sample, including：Based on the synchronizing sequence, determine that the pilot frequency sequence is residing in first transmission frame
Position；Based on the time difference information, it is determined that the rising edge of the second clock signal corresponding with the phase difference；It is based on
The pilot frequency sequence location and rising edge in first transmission frame, it is determined that to institute in first transmission frame
State the second sampled point that pilot frequency sequence is sampled.
Optionally, based on first sampled point and second sampled point, first terminal and described second is realized
Clock synchronization between terminal, including：Based on first sampled point, second terminal is synchronized with first terminal
The user data is sampled；And based on second sampled point, second end is synchronized with first terminal
Machine is sampled to the pilot frequency sequence.
On the other hand, the embodiment of the present invention provides a kind of first terminal, can apply above-mentioned clock synchronizing method, including：
First receiver module, for receiving the first transmission frame that the second terminal being connected with first terminal sends, institute
Stating the first transmission frame includes pilot frequency sequence and user data；Wherein, at least a portion data of the pilot frequency sequence being capable of conduct
Cyclic Prefix in first transmission frame, the Cyclic Prefix is used to eliminate between first terminal and second terminal
The multi-path jamming of transmission channel；First acquisition module, it is described for based on first transmission frame, obtaining time difference information
Time difference information be used to indicating second terminal when first transmission frame is sent produced the first clock signal with
Phase difference between first terminal second clock signal produced when first transmission frame is received；First determines
Module, for based on the time difference information, it is determined that sampled to user data described in first transmission frame
One sampled point, and to the second sampled point that pilot frequency sequence described in first transmission frame is sampled；First realizes module, uses
In based on first sampled point and second sampled point, the clock between first terminal and second terminal is realized
It is synchronous.
Optionally, first transmission frame also includes taking a Fast Fourier Transform (FFT) FFT of first transmission frame
The synchronizing sequence of symbol, the synchronizing sequence at least can be used to indicate that the pilot frequency sequence rising in first transmission frame
Beginning position.
Optionally, based on first transmission frame, time difference information is obtained, first terminal also includes：Second is true
Cover half block, for based on first transmission frame, determining the data message of first transmission frame, the data message includes width
Degree information and phase information；First computing module, for the data message based on first transmission frame, when calculating described first
Phase difference between clock signal and the second clock signal；Second acquisition module, for based on the phase difference, obtaining the time
Control information.
Optionally, based on the time difference information, it is determined that being adopted to user data described in first transmission frame
First sampled point of sample, first terminal also includes：3rd determining module, for based on the time difference information, passing through
Curve matching determines the first sampled point sampled to user data described in first transmission frame.
Optionally, based on the time difference information, it is determined that being adopted to pilot frequency sequence described in first transmission frame
Second sampled point of sample, first terminal also includes：4th determining module, for based on the synchronizing sequence, it is determined that described
Pilot frequency sequence location in first transmission frame；5th determining module, for based on the time difference information, really
The rising edge of the fixed second clock signal corresponding with the phase difference；6th determining module, for based on the pilot tone sequence
Location and the rising edge in first transmission frame are listed in, it is determined that to pilot frequency sequence described in first transmission frame
The second sampled point sampled.
Optionally, based on first sampled point and second sampled point, first terminal and described second is realized
Clock synchronization between terminal, first terminal also includes：First synchronization module, for based on first sampled point,
It is synchronized with second terminal in first terminal to sample the user data；And second synchronization module, for base
In second sampled point, second terminal is synchronized with first terminal pilot frequency sequence is sampled.
One or more technical schemes in above-mentioned technical proposal, have the following technical effect that or advantage：
First, the embodiment of the present invention provides a kind of clock synchronizing method, and the second terminal that reception is connected with the first terminal sends
The first transmission frame, first transmission frame include pilot frequency sequence and user data, wherein, at least a portion data of pilot frequency sequence
Can be used as the Cyclic Prefix in the first transmission frame, the Cyclic Prefix is used to eliminate to be transmitted between the first terminal and the second terminal to be believed
The multi-path jamming in road；Then, according to first transmission frame, obtain for indicating the second terminal to be produced when the first transmission frame is sent
Phase between raw the first clock signal and the first terminal second clock signal produced when the first transmission frame is received
Poor time difference information, based on time difference information, determines sampled to user data in the first transmission frame respectively
One sampled point, and the second sampled point sampled to pilot frequency sequence；Finally according to the first sampled point and the second sampled point, realize
Clock synchronization between first terminal and the second terminal.I.e. in technical solution of the present invention, at least a portion number of pilot frequency sequence
According to can be as the Cyclic Prefix in the first transmission frame making protection interval, it is to avoid produced multipath is done during Multipath Transmission
Disturb, without the need for extra protection interval is inserted in the first transmission frame, so as to solve clock synchronization of the prior art
The accessing cost for data that method is present is big, causes the technical problem that communication efficiency is relatively low, realizes and reduces accessing cost for data, improves communication
The technique effect of efficiency.
2nd, in due to the embodiment of the present invention, the synchronizing sequence in the first transmission frame is compared to occupancy two in the prior art
The preamble word of FFT symbols, only takes up a FFT symbol, and another FFT symbol can be used for transmitting effective communication data,
So as to further increase communication efficiency.
3rd, due in embodiments of the present invention, based on time difference information, different modes are respectively adopted and determine to first
The first sampled point that user data is sampled in transmission frame, and second sampled to pilot frequency sequence in the first data frame is adopted
Sampling point, to realize the clock synchronization of transmitting-receiving two-end, clock synchronization can either be realized so as to reach, and turn avoid destruction pilot tone sequence
The technique effect of the frequency domain equalization characteristic of row.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 is the schematic flow sheet of clock synchronizing method in the embodiment of the present invention；
Fig. 2 is the frame structure schematic diagram of the first transmission frame in the embodiment of the present invention；
Fig. 3 is the waveform diagram of clock signal in the embodiment of the present invention；
Fig. 4 is the schematic diagram of the sampled point of determination pilot frequency sequence in the embodiment of the present invention；
Fig. 5 is a kind of schematic diagram of frame structure of the prior art；
Fig. 6 is the module diagram of the first terminal in the embodiment of the present invention.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Clock synchronizing method in the embodiment of the present invention, can apply to the first terminal, wherein the first terminal and follow-up
Second terminal may belong to SC-FDE systems, and SC-FDE systems are a kind of single-carrier systems, intrinsic in the absence of ofdm system
Peak power average power ratio (Peak to Average Power Ration, PAPR) problem, and it is to transmission power amplification
The range of linearity requirement of device is low, and the cost of equipment is relatively low.
In actual applications, the first terminal can be the receiver in SC-FDE systems, and the second terminal can be SC-FDE
Transmitter in system etc..Clock synchronizing method in the embodiment of the present invention can apply to but be not limited only to SC-FDE systems,
The method is equally applicable to other systems.And printed words such as " first, second, third " in the embodiment of the present invention are only easy for
Distinguish, be not used to any restriction.
The preferred embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.
As shown in figure 1, the embodiment of the present invention provides a kind of clock synchronizing method, the clock synchronizing method can apply to the
In one terminal, the process of the method can be described as follows：
S100：The first transmission frame that the second terminal that reception is connected with the first terminal sends, the first transmission frame includes pilot tone
Sequence and user data；Wherein, at least a portion data of pilot frequency sequence can be followed as the Cyclic Prefix in the first transmission frame
Ring prefix is used to eliminate the multi-path jamming of transmission channel between the first terminal and the second terminal.
Wherein, the first transmission frame can be the data frame or signal frame of SC-FDE systems, and the data frame or signal
The frame structure of frame can be set according to transmission means, and wherein transmission means includes burst transmission mode and continuous transmission mode
Deng, or frame structure can also be set according to the block number of pilot frequency sequence of insertion, and there is difference for different block numbers
Setting means, the block number of the pilot frequency sequence of insertion generally includes monolithic pilot tone word, polylith pilot tone word etc..
In the embodiment of the present invention, pilot frequency sequence can be Zadoff-Chu sequence (being hereinafter referred to as Chu sequences),
Chu sequences are a kind of time-domain training sequences with good orthogonal property, and it has good time domain autocorrelation, meanwhile, Chu
Sequence has excellent amplitude versus frequency characte, i.e., the amplitude such as be similar on frequency domain, its also amplitude such as approximate in time domain, can be used for
Realize channel estimation and frequency domain equalization.In actual applications, the selection of the frame length of Chu sequences, can take into account system time frequency synchronization
Demand and system actual overhead, strive for that more accurate Time and Frequency Synchronization can be realized with expense as small as possible.And use
User data can be the valid data of periodically insertion, and the valid data can be the communication data that user transmits in systems,
Such as speech data, view data.
Wherein, at least a portion data of pilot frequency sequence can be as the Cyclic Prefix (Cyclic in the first transmission frame
Prefix, CP), the Cyclic Prefix can be used for eliminating the multi-path jamming of transmission channel between the first terminal and the second terminal, i.e.,
Can be used for the multi-path jamming of multipath channel between countermeasure system receiving terminal and transmitting terminal.
As shown in Fig. 2 in actual applications, unique word can be used as by replicating the one piece of data of pilot frequency sequence end
(Unique Word, UW) constitutes the Cyclic Prefix of pilot frequency sequence, and this one piece of data can also be multiplexed with the circulation of user data
Prefix, extra protection interval is inserted without the frame structure to system, reduces accessing cost for data.
Optionally, the first transmission frame can also include taking a Fast Fourier Transform (FFT) (Fast of the first transmission frame
Fourier Transform, FFT) symbol synchronizing sequence, the synchronizing sequence at least can serve to indicate that pilot frequency sequence first
Original position in transmission frame.
Still referring to Fig. 2, in actual applications, synchronizing sequence can be similar to compared to two preamble words of the prior art
Only take up a FFT symbol, another FFT symbol that two preamble words are similar in two shared FFT symbols can be used for
Subsequent transmission valid data, so as to improve communication efficiency.Wherein, synchronizing sequence can mainly include following three part：
1), training sequence, it can be data known to a section, and by alternate " 0,1 " Sequence composition, length can be by certainly
The duration of Generation Control (Automatic Generation Control, AGC) locking is moved to determine.Training sequence is mainly used in
Receiving terminal AGC locking, i.e. receiving terminal AGC locking need a period of time, and need this period send training sequence and can not
Effective information is enough transmitted, such as effective user data, the major function of its locking is that the Larger Dynamic for realizing receiving terminal is received.
2), five sections of pseudo noise sequences for repeating (Pseudo-noise, PN), are hereinafter PN sequences, and it has
Orthogonality, is mainly used in realizing offset estimation and locally associated.
3), frame synchronization head, it can be one section of PN sequence, can be used for realizing the frame synchronization in system, be also called thick same
Step.In actual applications, the original position of the pilot frequency sequence in the first transmission frame can be determined according to frame synchronization head, i.e., to passing
The arrival of defeated frame signal detected and symbol original position estimated, captured partially during realizing, by when be locked in one partially
In individual less scope so that system can normally be operated.
The frame structure of the first transmission frame in the embodiment of the present invention can be with as shown in Fig. 2 wherein, L represents a FFT symbol
Frame length, UW is Cyclic Prefix, and it can form the multi-path jamming that protection interval is used to resist multipath channel.
S200：Based on the first transmission frame, time difference information is obtained, the time difference information is used to indicate the second terminal to exist
The first clock signal produced during the first transmission frame and the first terminal are sent when the first transmission frame is received produced the
Phase difference between two clock signals.
Fig. 3 is the waveform diagram of clock signal, can be produced by parts such as the counter in system, timers, its
In, data can be sampled when clock signal is in rising edge.Such as, the emitter of SC-FDE systems is sent out to receiver
When sending the first transmission frame, the counter in system can accordingly produce the first clock signal, and carry this in the first transmission frame
First clock signal, when receiver is when the first transmission frame is received, the timer of receiving terminal can be when local recovery goes out second
Clock signal, and the reason such as interference due to multipath channel, occur phase difference between the first clock signal and second clock signal,
Phase error i.e. between the two.In actual applications, the phase error can be calculated by the correlation formula of quadratic method and obtained,
Can certainly be obtained by other algorithms, which kind of algorithm specifically to obtain time difference information, the embodiment of the present invention using
Do not make any limitation to this, and calculated according to quadratic method obtain the calculating process of phase difference with it is consistent in the prior art, herein
Do not repeat.
Optionally, based on the first transmission frame, time difference information is obtained, can be included：Based on the first transmission frame, is determined
The data message of one transmission frame, the data message can include amplitude information and phase information；Data based on the first transmission frame
Information, calculates the phase difference between the first clock signal and second clock signal；Based on phase difference, time difference information is obtained.
In actual applications, from Mathematical Modeling, the first transmission frame substantially can be one piece of data, and the data
In, according to these data messages, can be calculated by the correlation computations formula of quadratic method including the information such as amplitude, phase
To phase difference, time difference information is obtained further according to the phase difference, wherein, time difference information can be second clock signal
The information such as advanced, delayed occurred relative to the first clock signal.
Such as, receiving terminal is when entrained first during the second clock signal that local recovery goes out is compared to the first transmission frame
For clock signal, the first transmission frame is sampled in advance in Lead conditions, i.e. receiving terminal；Or, receiving terminal is local
The second clock signal for recovering compared to entrained the first clock run signal in the first transmission, in hysteretic state, i.e.,
Receiving terminal time delay is sampled to the first transmission frame.In the case of this two kinds over time, when transmitting-receiving two-end cannot be realized
Clock synchronization, the data that receiving terminal may be caused to recover are imperfect or data dislocation occur.
S300：Based on time difference information, it is determined that the first sampled point sampled to user data in the first transmission frame,
And to the second sampled point that pilot frequency sequence in the first transmission frame is sampled.
Wherein, the first sampled point can be adopting of being sampled to user data when the first transmission frame is received of receiving terminal
Sample starting point, the sampled point can be calculated according to quadratic method and obtained；Accordingly, the second sampled point can be that receiving terminal is being received
The first sampling point sampled to pilot frequency sequence during the first transmission frame, the determination of sampled point can subsequently be introduced, herein not
Repeat.
That is, in embodiments of the present invention, after time difference information is obtained, can be distinguished by different modes
Determine the sampled point of user data and pilot frequency sequence in the first transmission frame.
Firstth, the sampled point of user data in the first transmission frame can in the following manner be determined.
Optionally, based on time difference information, it is determined that the first sampling sampled to user data in the first transmission frame
Point, the process can be：Based on the time difference information, determined to being used described in first transmission frame by curve matching
The first sampled point that user data is sampled.
Wherein it is possible to be defined as follows to curve matching, to seek a curve so that data point is from the upper of this curve
Nearby, required curve is referred to as matched curve for side or lower section, and the matched curve can both reflect the overall distribution of data, and
It is unlikely to local larger fluctuation occur, can more reflects the characteristic of approximated function, makes the approximating function tried to achieve and known letter
Its deviation reaches minimum by some way measurement for counting on the whole.
In actual applications, can according to the time difference information calculated using quadratic method, by filtering interpolation method,
Go out a most accurate sampling point value by calculating integer interpolation and decimal interpolation fitting, you can to determine to user data
The first sampling point sampled.Wherein, the calculating process of filtering interpolation method with it is consistent in the prior art, so not going to live in the household of one's in-laws on getting married herein
State.
Secondth, the sampled point of pilot frequency sequence in the first transmission frame can in the following manner be determined.
Optionally, based on time difference information, it is determined that the second sampling sampled to pilot frequency sequence in the first transmission frame
Point, the process can be：Based on synchronizing sequence, pilot frequency sequence location in the first transmission frame is determined；Missed based on the time
Difference information, it is determined that the rising edge of second clock signal corresponding with phase difference；It is residing in the first transmission frame based on pilot frequency sequence
Position and rising edge, it is determined that the second sampled point sampled to pilot frequency sequence described in the first transmission frame.
In the embodiment of the present invention, because the pilot frequency sequence in the first transmission frame mainly uses Chu sequences, it is one
All it is the special sequence of the amplitude such as approximate in frequency domain and time domain, frequency band is wider, it is easy to accomplish the frequency domain characteristic of full frequency band is estimated.And
Above-mentioned filtering interpolation method, can insert new data during calculating, and the generation of the new data is unsatisfactory for Chu sequences
Production, can destroy the frequency domain characteristic of Chu sequences so that the frequency domain equalization that later use Chu sequences are made can fail, it is impossible to enough right
The characteristic of channel makes correct compensation, consequently, it is possible to causing the final demodulation to the first data frame to fail.
So, it is determined that after time difference information, it is necessary first to determine that pilot frequency sequence is residing in the first transmission frame
Position Approximate so that follow-up when using filtering interpolation method come processing data, pilot frequency sequence can be avoided, prevent from destroying pilot tone
The frequency domain equalization characteristic of sequence.
In actual applications, due to frame synchronization head can be included in synchronizing sequence, can be determined according to frame synchronization head
Go out original position of the pilot frequency sequence in the first transmission frame, the frame length according to the original position and each symbol can be determined
The residing Position Approximate in the first transmission frame of pilot frequency sequence.
Secondly, phase difference can be determined according to time difference information corresponding to second clock signal rising edge.
Such as, Fig. 4 is referred to, wherein, it can be the window for obtaining sampled point to calculate window, and receiving signal can represent first
Pilot frequency sequence in transmission frame, T can be expressed as the cycle.Assuming that the scope of different phase errors corresponds to receiving terminal receiving
To the different rising edge of the clock signal gone out in local recovery during the first transmission frame, if falling phase error for [- 0.125,
0.125) when, rising edge corresponds to (a) in Fig. 4；If falling phase error for [0.125,0.375) when, rising edge corresponds to
(b) in Fig. 4；If falling phase error for [- 0.375, -0.125), rising edge correspond to Fig. 4 in (c)；Phase error model
Enclose during for other situations, rising edge can correspond to (d) in Fig. 4.
Therefore, it is calculated after phase error by quadratic method scheduling algorithm, phase error is entered according to 2 π radians
Row normalized, fallen in above-mentioned falling phase error according to the phase error obtained after normalized determine with
The rising edge of the second clock signal corresponding to phase error.If the phase error after normalization is 0.121, then its institute
Corresponding rising edge is (a) in Fig. 4, if the phase error after normalization is -0.315, the rising edge corresponding to it is
(c) in Fig. 4 etc..
Finally, the rising determined further according to pilot frequency sequence the location of in the first transmission frame and by the above method
Edge, it is determined that the second sampled point sampled to pilot frequency sequence in the first transmission frame, i.e., in the rising of the clock signal determined
Pilot frequency sequence is sampled along place.
Such as, if a symbol of pilot frequency sequence is 20MHZ, the position of pilot frequency sequence is being determined according to the above method
And after corresponding rising edge, it may be determined that go out the second sampled point that pilot frequency sequence in the first transmission frame is sampled, follow-up root
It is 1/ (20MHZ), i.e. 50ns according to the cycle according to the sampled point, pilot frequency sequence is sampled.Wherein, megahertz MHZ is frequency
Unit, nanosecond ns is chronomere.
S400：Based on the first sampled point and the second sampled point, realize that the clock between the first terminal and the second terminal is synchronous.
Optionally, based on the first sampled point and the second sampled point, realize that the clock between the first terminal and the second terminal is same
Step, including：Based on the first sampled point, the second terminal is synchronized with the first terminal user data is sampled；And based on
Two sampled points, the second terminal are synchronized with the first terminal pilot frequency sequence are sampled.
In actual applications, in a cycle, receiving terminal if it is determined that the first sampled point sampled to user data,
The second sampled point sampled to pilot frequency sequence, then receiving terminal can be synchronized with transmitting terminal to the first data frame carry out sampling it is extensive
It is multiple, so as to realize the clock synchronization between the first terminal and the second terminal.
In the embodiment of the present invention, receiving terminal, can be according to the first transmission when the first transmission frame is received in SC-FDE systems
The frame synchronization head of the training sequence in frame determines the original position of pilot frequency sequence, to determine pilot tone sequence in the first transmission frame
The Position Approximate of row, that is, realize the thick synchronization of transmitting-receiving two-end.After thick synchronization is realized, continuation carries out thin synchronization to system, i.e.,
Clock synchronization.And clock synchronization is directed to, mainly realized from two parts.
The phase that the correlation formula of quadratic method can be utilized to calculate between the first clock signal and second clock signal first
Error, then for other data in addition to pilot frequency sequence, such as user data, can be by the way of curve matching, such as interpolation
Filter method obtains the first sampling point of user data to calculate, you can to calculate phase error using quadratic method, and utilizes and inserts
Value filtering method corrects the error, so that it is determined that go out the first sampling point of user data.
And for the synchronization of pilot frequency sequence part, according to the phase error calculated above by quadratic method, see this
Phase error falls in the scope of which phase error, wherein, the clock letter that each falling phase error correspondence local recovery goes out
A rising edge in number, determines the rising edge of the clock signal corresponding to phase error in-scope, at the rising edge
It can be the first sampling point sampled to pilot frequency sequence.
After the first sampling point and the first sampling point of pilot frequency sequence for determining user data respectively, subsequently adopted according to this
Sample starting point, it is possible to realize the clock synchronization of transmitting-receiving two-end, further reduce partially when will be relative, further assure that system
Performance.
In embodiments of the present invention, at least a portion data of pilot frequency sequence just can be used as the circulation in the first transmission frame
Prefix is used to resist produced multi-path jamming during Multipath Transmission to make protection interval, without extra to
One transmission frame inserts protection interval, is used for the data auxiliary clock synchronous method of SC-FDE systems in the prior art so as to solve
The accessing cost for data of presence is big, causes the technical problem that communication efficiency is relatively low, realizes and reduces accessing cost for data, improves communication effect
The technique effect of rate.
Therefore, in embodiments of the present invention, the clock of unbound nucleus is realized in SC-FDE systems by algorithm improvement
Synchronized algorithm, when once realizing partially capture and when track partially, i.e., based on time difference information, different modes are respectively adopted and determine
The first sampled point sampled to user data in the first transmission frame, and pilot frequency sequence in the first data frame is sampled
Second sampled point, to realize clock synchronization, so as to can realize clock synchronization, the frequency domain that turn avoid destruction pilot frequency sequence is equal
Weighing apparatus characteristic, improves the efficiency of data transfer, and is implemented without sliding correlation method of sampling, so as to reduce shared by system
Hardware resource.
Fig. 6 is referred to, the embodiment of the present invention also provides a kind of first terminal, first terminal can include that first receives mould
Block 101, the first acquisition module 102, the first determining module 103, first realize module 104.
Wherein, the first receiver module 101, for receiving the first biography that the second terminal being connected with first terminal sends
Defeated frame, first transmission frame includes pilot frequency sequence and user data；Wherein, at least a portion data energy of the pilot frequency sequence
Enough as the Cyclic Prefix in first transmission frame, the Cyclic Prefix is used to eliminate first terminal with second end
The multi-path jamming of transmission channel between machine；First acquisition module 102, for based on first transmission frame, obtaining time error
Information, when the time difference information is used to indicate second terminal when first transmission frame is sent produced first
Phase difference between clock signal and first terminal second clock signal produced when first transmission frame is received；
First determining module 103, for based on the time difference information, it is determined that entering to user data described in first transmission frame
First sampled point of row sampling, and to the second sampled point that pilot frequency sequence described in first transmission frame is sampled；First
Module 104 is realized, for based on first sampled point and second sampled point, realizing first terminal and described second
Clock synchronization between terminal.
Optionally, first transmission frame also includes taking a Fast Fourier Transform (FFT) FFT of first transmission frame
The synchronizing sequence of symbol, the synchronizing sequence at least can be used to indicate that the pilot frequency sequence rising in first transmission frame
Beginning position.
Optionally, based on first transmission frame, time difference information is obtained, first terminal also includes：Second is true
Cover half block, for based on first transmission frame, determining the data message of first transmission frame, the data message includes width
Degree information and phase information；First computing module, for the data message based on first transmission frame, when calculating described first
Phase difference between clock signal and the second clock signal；Second acquisition module, for based on the phase difference, obtaining the time
Control information.
Optionally, based on the time difference information, it is determined that being adopted to user data described in first transmission frame
First sampled point of sample, first terminal also includes：3rd determining module, for based on the time difference information, passing through
Curve matching determines the first sampled point sampled to user data described in first transmission frame.
Optionally, based on the time difference information, it is determined that being adopted to pilot frequency sequence described in first transmission frame
Second sampled point of sample, first terminal also includes：4th determining module, for based on the synchronizing sequence, it is determined that described
Pilot frequency sequence location in first transmission frame；5th determining module, for based on the time difference information, really
The rising edge of the fixed second clock signal corresponding with the phase difference；6th determining module, for based on the pilot tone sequence
Location and the rising edge in first transmission frame are listed in, it is determined that to pilot frequency sequence described in first transmission frame
The second sampled point sampled.
Optionally, based on first sampled point and second sampled point, first terminal and described second is realized
Clock synchronization between terminal, first terminal also includes：First synchronization module, for based on first sampled point,
It is synchronized with second terminal in first terminal to sample the user data；And second synchronization module, for base
In second sampled point, second terminal is synchronized with first terminal pilot frequency sequence is sampled.
The above, all embodiments of the above are only used to the detailed introduction carried out to technical scheme, and
The explanation of above example is only only intended to help and understands the method for the present invention and its core concept, should not be construed to this
The restriction of invention.Those skilled in the art the invention discloses technical scope in, the change that can easily expect
Or replace, should all be included within the scope of the present invention.
Obviously, those skilled in the art can carry out various modification and variation without deviating from the utility model to the present invention
Spirit and scope.So, if these modifications of the invention and modification belong to the claims in the present invention and its equivalent technology
Within the scope of, then the present invention is also intended to comprising these changes and modification.
Claims (12)
1. a kind of clock synchronizing method, is applied to the first terminal, it is characterised in that including：
The first transmission frame that the second terminal that reception is connected with first terminal sends, first transmission frame includes pilot tone sequence
Row and user data；Wherein, at least a portion data of the pilot frequency sequence can be used as the circulation in first transmission frame
Prefix, the Cyclic Prefix is used to eliminate the multi-path jamming of transmission channel between first terminal and second terminal；
Based on first transmission frame, time difference information is obtained, the time difference information is used to indicate second terminal
When first transmission frame is sent, the first produced clock signal is receiving first transmission with first terminal
Phase difference between second clock signal produced during frame；
Based on the time difference information, it is determined that the first sampling sampled to user data described in first transmission frame
Point, and to the second sampled point that pilot frequency sequence described in first transmission frame is sampled；
Based on first sampled point and second sampled point, realize between first terminal and second terminal when
Clock synchronization.
2. clock synchronizing method as claimed in claim 1, it is characterised in that first transmission frame also includes taking described the
One synchronizing sequence of Fast Fourier Transform (FFT) FFT symbols of one transmission frame, the synchronizing sequence at least can be used to indicate that institute
State original position of the pilot frequency sequence in first transmission frame.
3. clock synchronizing method as claimed in claim 2, it is characterised in that based on first transmission frame, the time that obtains misses
Difference information, including：
Based on first transmission frame, the data message of first transmission frame is determined, the data message includes amplitude information
And phase information；
Based on the data message of first transmission frame, calculate between first clock signal and the second clock signal
Phase difference；
Based on the phase difference, time difference information is obtained.
4. clock synchronizing method as claimed in claim 2, it is characterised in that based on the time difference information, it is determined that to institute
The first sampled point that user data described in the first transmission frame is sampled is stated, including：
Based on the time difference information, determine to adopt user data described in first transmission frame by curve matching
First sampled point of sample.
5. clock synchronizing method as claimed in claim 4, it is characterised in that based on the time difference information, it is determined that to institute
The second sampled point that pilot frequency sequence described in the first transmission frame is sampled is stated, including：
Based on the synchronizing sequence, pilot frequency sequence location in first transmission frame is determined；
Based on the time difference information, it is determined that the rising edge of the second clock signal corresponding with the phase difference；
Based on the pilot frequency sequence the location of in first transmission frame and the rising edge, it is determined that being passed to described first
The second sampled point that pilot frequency sequence described in defeated frame is sampled.
6. clock synchronizing method as claimed in claim 1, it is characterised in that adopted with described second based on first sampled point
Sampling point, realizes that the clock between first terminal and second terminal is synchronous, including：
Based on first sampled point, second terminal is synchronized with first terminal user data is adopted
Sample；
And based on second sampled point, second terminal is synchronized with first terminal to be carried out to the pilot frequency sequence
Sampling.
7. a kind of first terminal, it is characterised in that including：
First receiver module, for receiving the first transmission frame that the second terminal for being connected with first terminal sends, described the
One transmission frame includes pilot frequency sequence and user data；Wherein, at least a portion data of the pilot frequency sequence can be used as described
Cyclic Prefix in first transmission frame, the Cyclic Prefix is used to eliminate transmission between first terminal and second terminal
The multi-path jamming of channel；
First acquisition module, for based on first transmission frame, obtaining time difference information, the time difference information is used for
The first clock signal for indicating second terminal produced when first transmission frame is sent is connecing with first terminal
Receive the phase difference between second clock signal produced during first transmission frame；
First determining module, for based on the time difference information, it is determined that to user data described in first transmission frame
The first sampled point sampled, and to the second sampled point that pilot frequency sequence described in first transmission frame is sampled；
First realizes module, for based on first sampled point and second sampled point, realizing first terminal and institute
State the clock synchronization between the second terminal.
8. the first terminal as claimed in claim 7, it is characterised in that first transmission frame also includes that taking described first passes
One synchronizing sequence of Fast Fourier Transform (FFT) FFT symbols of defeated frame, the synchronizing sequence at least can be used to indicate that described leading
Original position of the frequency sequence in first transmission frame.
9. the first terminal as claimed in claim 8, it is characterised in that based on first transmission frame, obtains time error letter
Breath, first terminal also includes：
Second determining module, for based on first transmission frame, determining the data message of first transmission frame, the data
Information includes amplitude information and phase information；
First computing module, for the data message based on first transmission frame, calculate first clock signal with it is described
Phase difference between second clock signal；
Second acquisition module, for based on the phase difference, obtaining time difference information.
10. the first terminal as claimed in claim 8, it is characterised in that based on the time difference information, it is determined that to described
The first sampled point that user data described in one transmission frame is sampled, first terminal also includes：
3rd determining module, for based on the time difference information, being determined in first transmission frame by curve matching
The first sampled point that the user data is sampled.
11. first terminals as claimed in claim 10, it is characterised in that based on the time difference information, it is determined that to described
The second sampled point that pilot frequency sequence described in first transmission frame is sampled, first terminal also includes：
4th determining module, for based on the synchronizing sequence, determining that the pilot frequency sequence is residing in first transmission frame
Position；
5th determining module, for based on the time difference information, it is determined that the second clock corresponding with the phase difference
The rising edge of signal；
6th determining module, for location and the rising in first transmission frame based on the pilot frequency sequence
Edge, it is determined that the second sampled point sampled to pilot frequency sequence described in first transmission frame.
12. first terminals as claimed in claim 7, it is characterised in that based on first sampled point and the described second sampling
Point, realizes that the clock between first terminal and second terminal is synchronous, and first terminal also includes：
First synchronization module, for based on first sampled point, second terminal pair being synchronized with first terminal
The user data is sampled；
And second synchronization module, for based on second sampled point, second terminal being synchronized with first terminal
The pilot frequency sequence is sampled.
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