CN102593158B - Flash memory unit structure and flash memory device - Google Patents
Flash memory unit structure and flash memory device Download PDFInfo
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- CN102593158B CN102593158B CN201210061965.2A CN201210061965A CN102593158B CN 102593158 B CN102593158 B CN 102593158B CN 201210061965 A CN201210061965 A CN 201210061965A CN 102593158 B CN102593158 B CN 102593158B
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Abstract
The invention provides flash memory unit structure and flash memory device.Included according to the flash memory unit structure of the present invention：L-shaped ONO structure, the control gate polysilicon being arranged on the inside of the right angle of L-shaped ONO structure, be arranged in control gate polysilicon the opposite side relative to the L-shaped ONO structure silicon dioxide region, be arranged in silicon dioxide region the opposite side relative to control gate polysilicon wordline polysilicon and be arranged in L-shaped ONO structure the opposite side relative to control gate polysilicon bit line.The present invention proposes a kind of new flash memory unit structure and flash memory device, makes full use of the size of silicon substrate vertical direction, realizes the raceway groove of L-shaped, by the use of ONO structure as storage material, can complete reading and writing, put the operation write on the skin.Compared with conventional flash memory device, the major part of device channel is located at silicon substrate vertical direction, can so be more beneficial for reducing device size, increase device integration density.
Description
Technical field
The present invention relates to semiconductor applications, it is more particularly related to a kind of flash memory unit structure and employ
The flash memory device of the flash memory unit structure.
Background technology
Flash memory is convenient with its, and storage density is high, as the focus studied in non-volatility memorizer the advantages that good reliability.
Since first flash memory products appearance of the 1980s, development and each electronic product with technology
To the demand of storage, flash memory is widely used in mobile phone, and notebook, palm PC and USB flash disk etc. are mobile with communication apparatus, and flash memory is
A kind of nonvolatile memory.
The operation principles of flash memory are to control opening for gate pole passage by changing the critical voltage of transistor or memory cell
Close to reach the purpose of data storage, the data of storage in memory is not disappeared because of power interruptions, and flash memory is electricity
A kind of erasable and programmable read-only memory special construction.
Nowadays flash memory has already taken up most of market share of non-volatile semiconductor memory, turns into fastest developing speed
Non-volatile semiconductor memory.
With the progress of consumption electronic product and commercial electronic product etc., in order to realize consumption electronic product and commercial electronic
The miniaturization of product and portability, it is desirable to which storage device therein can be minimized further, i.e., for flash memory device, it would be desirable to
Enough reduce device size, increase device integration density.
The content of the invention
The technical problems to be solved by the invention are to be directed to have drawbacks described above in the prior art, there is provided one kind is advantageous to contract
Subtract device size, increase the flash memory unit structure of device integration density and employ the flash memory device of the flash memory unit structure.
According to the first aspect of the invention, there is provided a kind of flash memory unit structure, it includes：L-shaped ONO structure, cloth
Put the control gate polysilicon on the inside of the right angle of the L-shaped ONO structure, be arranged in the control gate polysilicon relative to
The silicon dioxide region of the opposite side of the L-shaped ONO structure, be arranged in the silicon dioxide region relative to the control gate
The wordline polysilicon of the opposite side of pole polysilicon and be arranged in the L-shaped ONO structure relative to the control gate polycrystalline
The bit line of the opposite side of silicon.
Preferably, the flash memory unit structure and another flash memory unit structure common word line polycrystalline of wordline polysilicon side
Silicon.
Preferably, the flash memory unit structure and another flash memory unit structure are relative to the shared wordline polycrystalline
The symmetry axis of silicon is arranged symmetrically.
Preferably, when wiping the flash memory unit structure, bit line is made to suspend, control gate polysilicon is added-
8V voltage, 8V voltage is added to the substrate where the flash memory unit structure.
Preferably, when being programmed to the flash memory unit structure, to bit line plus 5V voltage, to control gate polycrystalline
Silicon adds 8V voltage, and 0V voltage is added to the substrate where the flash memory unit structure, and 1.5V voltage is added to wordline polysilicon.
Preferably, when being read out to the flash memory unit structure, to bit line plus 1V voltage, to control gate polycrystalline
Silicon adds 0V voltage, and 0V voltage is added to the substrate where the flash memory unit structure, and 3V voltage is added to wordline polysilicon.
Preferably, when being programmed to the flash memory unit structure, the bit line of another flash memory unit structure is added
Size is equal to Vdp voltage, the voltage of control gate polysilicon 2 plus 5V to another flash memory unit structure.
Preferably, when being read out to the flash memory unit structure, the bit line of another flash memory unit structure is added
0V voltage, 5V voltage is added to the control gate polysilicon of another flash memory unit structure.
According to the second aspect of the invention, there is provided a kind of to employ flash cell described according to a first aspect of the present invention
The flash memory device of structure.
The present invention proposes a kind of new flash memory unit structure and flash memory device, makes full use of silicon substrate vertical direction
Size, the raceway groove of " L " shape is realized, by the use of ONO structure as storage material, reading and writing can be completed, put the operation write on the skin.With tradition
Flush memory device is compared, and the major part of device channel is located at silicon substrate vertical direction, can so be more beneficial for reducing device chi
It is very little, increase device integration density.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And be more easily understood its with the advantages of and feature, wherein：
Fig. 1 schematically shows flash memory unit structure according to embodiments of the present invention.
Fig. 2 schematically shows flash memory unit structure according to another embodiment of the present invention.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Pay attention to, represent that the accompanying drawing of structure can
It can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 schematically shows flash memory unit structure according to embodiments of the present invention.
As shown in figure 1, flash memory unit structure according to embodiments of the present invention includes：L-shaped ONO (Oxide-Nitride-
Oxide, silicon dioxide/silicon nitride/silica) structure 1, the control gate that is arranged on the inside of the right angle of L-shaped ONO structure 1 be more
Crystal silicon 2, be arranged in control gate polysilicon 2 the opposite side relative to L-shaped ONO structure 1 silicon dioxide region 3, be arranged in
The wordline polysilicon 4 of the opposite side relative to control gate polysilicon 2 of silicon dioxide region 3 and be arranged in L-shaped ONO knot
The bit line 5 of the opposite side relative to control gate polysilicon 2 of structure 1.
Further, when wiping the flash memory unit structure according to embodiments of the present invention shown in Fig. 1, position is made
Line 5 is suspended, and -8V voltage is added to control gate polysilicon 2, and 8V voltage is added to the substrate where flash memory unit structure.
When being programmed to the flash memory unit structure according to embodiments of the present invention shown in Fig. 1, to bit line 5 plus 5V electricity
Pressure, 8V voltage is added to control gate polysilicon 2,0V voltage is added to the substrate where flash memory unit structure, to wordline polycrystalline
The voltage of silicon 4 plus 1.5V.
When being read out to the flash memory unit structure according to embodiments of the present invention shown in Fig. 1, to bit line 5 plus 1V electricity
Pressure, 0V voltage is added to control gate polysilicon 2,0V voltage is added to the substrate where flash memory unit structure, to wordline polycrystalline
The voltage of silicon 4 plus 3V.
Further, Fig. 2 schematically shows flash memory unit structure according to another embodiment of the present invention.Such as Fig. 2 institutes
Show, it is preferable that above-mentioned flash memory unit structure and another flash memory unit structure common word line polysilicon of wordline polysilicon side.
And, it is preferable that as shown in Fig. 2 the flash memory unit structure and another flash memory unit structure are relative to institute
The symmetry axis A-A for stating shared wordline polysilicon is arranged symmetrically.Thus, the symmetry axis A-A of the shared wordline polysilicon
It is the symmetry axis of the flash memory unit structure and another flash memory unit structure.
For the flash memory unit structure according to another embodiment of the present invention shown in Fig. 2, similarly, to shown in Fig. 2
When flash memory unit structure is wiped, the bit line 5 of the flash memory unit structure and another flash memory unit structure is set to suspend, it is right
The control gate polysilicon 2 of the flash memory unit structure and another flash memory unit structure all adds -8V voltage, to the sudden strain of a muscle
Substrate where deposit receipt meta structure and another flash memory unit structure all adds 8V voltage.
A flash memory unit structure in the flash memory unit structure according to another embodiment of the present invention shown in Fig. 2 enters
During row programming, for the flash memory unit structure of programming, to bit line 5 plus 5V voltage, to control gate polysilicon 2 plus 8V electricity
Pressure, 0V voltage is added to the substrate where flash memory unit structure, to wordline polysilicon 4 plus 1.5V voltage.And for programming
Flash memory unit structure adjacent flash memory unit structure, bit line is increased and small is equal to Vdp (constant currents when Vdp is to maintain programming
Bit line voltage, size can be automatically adjusted) voltage, 5V voltage is added to control gate polysilicon.
A flash memory unit structure in the flash memory unit structure according to another embodiment of the present invention shown in Fig. 2 enters
When row is read, for the flash memory unit structure read, to bit line 5 plus 1V voltage, to control gate polysilicon 2 plus 0V electricity
Pressure, 0V voltage is added to the substrate where flash memory unit structure, to wordline polysilicon 4 plus 3V voltage.And for being read
The adjacent flash memory unit structure of flash memory unit structure, to bit line plus 0V voltage, 5V voltage is added to control gate polysilicon.
According to another embodiment of the present invention, the present invention also provides a kind of sudden strain of a muscle employed shown in above-mentioned Fig. 1 or shown in Fig. 2
The flash memory device of deposit receipt meta structure.
It is understood that although the present invention is disclosed as above with preferred embodiment, but above-described embodiment and it is not used to
Limit the present invention.For any those skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications are all made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of change.Therefore, every content without departing from technical solution of the present invention, the technical spirit pair according to the present invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (9)
- A kind of 1. flash memory unit structure, it is characterised in that including：L-shaped ONO structure, it is arranged in the right angle of the L-shaped ONO structure The control gate polysilicon of side, be arranged in the control gate polysilicon the opposite side relative to the L-shaped ONO structure two Region of silicon oxide, be arranged in the silicon dioxide region the opposite side relative to the control gate polysilicon wordline polycrystalline Silicon and be arranged in the L-shaped ONO structure the opposite side relative to the control gate polysilicon bit line；In the L-shaped On the opposite side relative to the control gate polysilicon of ONO structure, L is formed along the borderline region of the L-shaped ONO structure Shape raceway groove.
- 2. flash memory unit structure according to claim 1, it is characterised in that the flash memory unit structure and wordline polysilicon Another flash memory unit structure common word line polysilicon of side.
- 3. flash memory unit structure according to claim 2, it is characterised in that the flash memory unit structure and another sudden strain of a muscle Deposit receipt meta structure is arranged symmetrically relative to the symmetry axis of the shared wordline polysilicon.
- 4. the flash memory unit structure according to one of claims 1 to 3, it is characterised in that to the flash memory unit structure When being wiped, bit line is suspended, -8V voltage is added to control gate polysilicon, to the lining where the flash memory unit structure Bottom adds 8V voltage.
- 5. the flash memory unit structure according to one of claims 1 to 3, it is characterised in that to the flash memory unit structure When being programmed, to bit line plus 5V voltage, 8V voltage is added to control gate polysilicon, to where the flash memory unit structure Substrate add 0V voltage, 1.5V voltage is added to wordline polysilicon.
- 6. the flash memory unit structure according to one of claims 1 to 3, it is characterised in that to the flash memory unit structure When being read out, to bit line plus 1V voltage, 0V voltage is added to control gate polysilicon, to where the flash memory unit structure Substrate add 0V voltage, 3V voltage is added to wordline polysilicon.
- 7. flash memory unit structure according to claim 3, it is characterised in that be programmed to the flash memory unit structure When, the small voltage equal to Vdp, the control to another flash memory unit structure are increased to the bit line of another flash memory unit structure The voltage of grid polycrystalline silicon 2 processed plus 5V.
- 8. flash memory unit structure according to claim 3, it is characterised in that be read out to the flash memory unit structure When, 0V voltage is added to the bit line of another flash memory unit structure, it is more to the control gate of another flash memory unit structure Crystal silicon adds 5V voltage.
- A kind of 9. flash memory device for employing the flash memory unit structure according to one of claim 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210061965.2A CN102593158B (en) | 2012-03-09 | 2012-03-09 | Flash memory unit structure and flash memory device |
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| CN201210061965.2A CN102593158B (en) | 2012-03-09 | 2012-03-09 | Flash memory unit structure and flash memory device |
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| CN102593158A CN102593158A (en) | 2012-07-18 |
| CN102593158B true CN102593158B (en) | 2017-12-08 |
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| CN111370420B (en) * | 2020-03-18 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Preparation method of SONOS memory device and SONOS memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
| CN1954433A (en) * | 2004-05-10 | 2007-04-25 | 微米技术股份有限公司 | NROM device |
| CN101419972A (en) * | 2008-11-13 | 2009-04-29 | 上海宏力半导体制造有限公司 | High-efficient erasing and writing flash memory in grating |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
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2012
- 2012-03-09 CN CN201210061965.2A patent/CN102593158B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
| CN1954433A (en) * | 2004-05-10 | 2007-04-25 | 微米技术股份有限公司 | NROM device |
| CN101419972A (en) * | 2008-11-13 | 2009-04-29 | 上海宏力半导体制造有限公司 | High-efficient erasing and writing flash memory in grating |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140504 |
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Effective date of registration: 20140504 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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