CN102592553B - Reset circuit - Google Patents
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- CN102592553B CN102592553B CN201110334615.4A CN201110334615A CN102592553B CN 102592553 B CN102592553 B CN 102592553B CN 201110334615 A CN201110334615 A CN 201110334615A CN 102592553 B CN102592553 B CN 102592553B
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Abstract
The invention discloses a reset circuit which is suitable for adjusting the potential of an output end of a shift register. The reset circuit driving module receives the enabling signal so as to output a control potential at the output end of the reset circuit driving module; the reset module is electrically coupled to the output end of the shift register and the output end of the reset circuit driving module, and the control potential of the output end of the reset circuit driving module controls whether the reset module conducts an electrical path between the output end of the shift register and the first preset potential.
Description
Technical field
The invention relates to the display technique field, and particularly relevant for a kind of structure of reset circuit of current potential of the output terminal that is suitable for adjusting offset buffer.
Background technology
Along with scientific and technological development, flat-panel screens (for example, liquid crystal display) because thering is high image quality, volume is little, lightweight and the advantage such as applied range, and be widely used in the various consumption electronic products such as mobile phone, mobile computer, desktop display device and TV, and little by little replaced traditional cathode-ray tube display and become the main flow of display.
At present for reducing the cost of flat-panel screens, therefore develop gate driver circuit (Gate-on-Array, GOA) and half source driving circuit (Half-source Driving, HSD) technology on array.Usually, a plurality of offset buffers that on array, gate driver circuit comprises mutual serial connection are sequentially to export a plurality of gate driving pulse, and Fig. 1 is the single-stage offset buffer SR (n) in a plurality of offset buffers that mutually are connected in series.Particularly, offset buffer SR (n) comprises transistor T 11, T12 and T21 and pull-down circuit 100.Wherein, the leakage of transistor T 12/source electrode receiving frequency signals CK (n-1), the grid reception control signal Q (n-1) of transistor T 12 is to determine the source whether tolerance frequency signal CK (n-1) is passed to transistor T 12/drain electrode; Leakage/the source electrode of transistor T 11 and grid all are electrically coupled to the source of transistor T 12/drain electrode so that frequency signal CK (n-1) is passed to the Q node; The grid of transistor T 21 is electrically coupled to the Q node and decides whether conducting of transistor T 21 with the control signal Q by the Q Nodes (n), leakage/the source electrode of transistor T 21 receives another frequency signal CK (n), and the source of transistor T 21/drain electrode is exported gate driving pulse G (n) as the output terminal of offset buffer SR (n) with the frequency signal CK (n) according to received; At this, the control signal of the Q Nodes that Q (n-1) is the upper level offset buffer.Pull-down circuit 100 is electrically coupled between Q node and grid shutdown signal level Vss, and is electrically coupled to the source of transistor T 21/drain electrode at specific time period, gate driving pulse G (n) is pulled to grid shutdown signal level Vss.
Fig. 2 shows the sequential chart of a plurality of signals that are relevant to the SR of offset buffer shown in Fig. 1 (n), the principle of work of offset buffer SR (n) is described below in conjunction with Fig. 1 and Fig. 2: when the gate driving pulse G of offset buffer SR (n) (n) exports, the transistor T 31 in pull-down circuit 100, T32, T41 and T42 cut-off; As the gate driving pulse G of offset buffer SR (n) (n), while closing, use the t period of control signal Q (n) to make gate driving pulse G (n) be released into grid shutdown signal level Vss.
Yet, when the transistor T 41 in pull-down circuit 100 is excessive with the process variation of T42, can cause control signal Q (n) to leak off to ahead of time grid shutdown signal level Vss but not as shown in the dotted line of period t in Fig. 2 at period t, gate driving pulse G (n) can't normally close and then cause gate driving pulse G (n) to have traction phenomena (as the waveform of G (n) in period t in Fig. 2), when towing is long, can cause the mistake of pixel information in picture to be filled, cause picture disply abnormal.
Summary of the invention
The purpose of this invention is to provide a kind of reset circuit, to improve the gate driving pulse traction phenomena.
The reset circuit that one embodiment of the invention proposes, be applicable to adjust the current potential of the output terminal of offset buffer.Reset circuit in the present embodiment comprises reset circuit driver module and replacement module; Wherein, the reset circuit driver module receives enable signal and controls current potential with the output of the output terminal by the reset circuit driver module; The replacement module is electrically coupled to the output terminal of offset buffer and the output terminal of reset circuit driver module, and whether the control control of Electric potentials replacement module of the output terminal of reset circuit driver module output the electrical path of conducting between output terminal to the first preset potential of offset buffer.
In one embodiment of this invention, above-mentioned reset circuit is in order to certain offset buffer in a plurality of offset buffers that mutually are connected in series of resetting, and the reset circuit driver module comprises the first transistor, this first transistor comprises control end, the first path terminal and alternate path end; Control end is electrically coupled to reset control signal so that reset control signal is controlled whether conducting of the first transistor by control end, and the first path terminal receives above-mentioned enable signal, and the alternate path end is electrically coupled to the output terminal of offset buffer.
Further, the offset buffer of the odd level in a plurality of offset buffers that offset buffer that reset circuit is reset is above-mentioned mutual serial connection, and whether reset control signal is provided the so far signal of the output terminal of the offset buffer of next odd level in order to control the corresponding frequency signal received in the offset buffer of the next odd level of the offset buffer of odd level for this reason.Now, replacement module can comprise transistor seconds; The control end of this transistor seconds is electrically coupled to the alternate path end of the first transistor, makes current potential on the alternate path end of the first transistor whether control the conducting transistor seconds by the control end of transistor seconds; The first path terminal of transistor seconds is electrically coupled to the output terminal of the offset buffer of odd level; The alternate path end of transistor seconds is electrically coupled to the first preset potential.
Or, the offset buffer of the even level in a plurality of offset buffers that offset buffer that reset circuit is reset is above-mentioned mutual serial connection, the reset control signal signal that the output terminal of the offset buffer of the next stage of the offset buffer of even level provides for this reason.Now, replacement module can comprise transistor seconds; At this, the control end of transistor seconds is electrically coupled to the alternate path end of the first transistor, makes the current potential of the alternate path end of the first transistor whether control the conducting transistor seconds by the control end of transistor seconds; The first path terminal electric property coupling of transistor seconds is the output terminal of the offset buffer of even level so far; The alternate path end of transistor seconds is electrically coupled to the first preset potential; Wherein, whether the offset buffer of this even level determine the frequency signal conducting output terminal of the offset buffer of even level so far according to the output signal of the offset buffer of previous stage, and the current potential of the first preset potential when frequency signal is transferred to the offset buffer of this even level for this reason.
In one embodiment of this invention, above-mentioned reset circuit more comprises and stops the module of resetting, be electrically coupled to the output terminal of offset buffer and the output terminal of reset circuit driver module, this module that stops resetting determines the electrical path between output terminal to the second preset potential of conducting reset circuit driver module whether according to the current potential of the output terminal of offset buffer.At this, the reset circuit driver module can comprise the first transistor and transistor seconds; The first transistor comprises control end, the first path terminal and alternate path end, and the control end of the first transistor and the first path terminal receive above-mentioned enable signal; Transistor seconds comprises control end, the first path terminal and alternate path end, the control end of transistor seconds is electrically coupled to the alternate path end of the first transistor, the first path terminal of transistor seconds receives above-mentioned enable signal, and the alternate path end of transistor seconds is as the output terminal of reset circuit driver module.
Moreover the module that stops resetting can comprise transistor; Transistorized control end is electrically coupled to the output terminal of offset buffer, so that whether the current potential of the output terminal of offset buffer controls this transistor of conducting by control end; The first path terminal is electrically coupled to the output terminal of reset circuit driver module; The alternate path end is electrically coupled to the second preset potential.In addition, replacement module can comprise transistor; This transistorized control end is electrically coupled to the output terminal of reset circuit driver module, makes the current potential of the output terminal of reset circuit driver module whether control this transistor of conducting by this transistorized control end; The first path terminal is electrically coupled to the output terminal of offset buffer; The alternate path end is electrically coupled to the first preset potential.At this, the first preset potential can be set to equal the second preset potential; Whether offset buffer determine the frequency signal conducting output terminal of offset buffer so far according to the output signal of the offset buffer of previous stage, and the current potential of the first preset potential when frequency signal is transferred to offset buffer for this reason.
In one embodiment of this invention, above-mentioned reset circuit driver module more receives the current potential of the output terminal of offset buffer, and reset circuit driver module and replacement module jointly form AND circuit and carry out the logical AND gate computing with the current potential of the output terminal to enable signal and offset buffer.Further, the reset circuit driver module for example comprises the first transistor, transistor seconds and the 3rd transistor; The control end of the first transistor is with the first path terminal phase electric property coupling and receive supply voltage, and the alternate path end of the first transistor is electrically coupled to the output terminal of reset circuit driver module; The control end of transistor seconds is electrically coupled to the output terminal of offset buffer, and the first path terminal of transistor seconds is electrically coupled to the output terminal of reset circuit driver module; The 3rd transistorized control end receives above-mentioned enable signal, and the 3rd transistorized the first path terminal is electrically coupled to the alternate path end of transistor seconds, and the 3rd transistorized alternate path termination is received the second preset potential.In addition, above-mentioned replacement module for example comprises the 4th transistor, and the 4th transistorized control end is electrically coupled to the output terminal of reset circuit driver module, the 4th transistorized the first path terminal is electrically coupled to the output terminal of offset buffer, and the 4th transistorized alternate path termination is received the first above-mentioned preset potential.
A kind of reset circuit that yet another embodiment of the invention proposes, be applicable to adjust the current potential of the output terminal of offset buffer.In this example, reset circuit comprises reset circuit driver module and replacement module; Wherein, the reset circuit driver module controls whether provide the output terminal of enable signal to the reset circuit driver module according to reset control signal; The replacement module is electrically coupled to the output terminal of offset buffer and the output terminal of reset circuit driver module, and whether the control of Electric potentials replacement module of the output terminal of reset circuit driver module the electrical path of conducting between output terminal to the first preset potential of offset buffer.Moreover, reset circuit is in order to an offset buffer in a plurality of offset buffers of the mutual serial connection reset, and the reset control signal of using during the offset buffer of the even level in a plurality of offset buffers that during offset buffer of the odd level in a plurality of offset buffers that offset buffer that reset circuit is reset is above-mentioned mutual serial connection, the reset control signal of using and the offset buffer of resetting when reset circuit are above-mentioned mutual serial connection is different.Further, when reset circuit reset for the offset buffer of odd level the time, whether reset control signal is provided the so far signal of the output terminal of the offset buffer of next odd level in order to control the corresponding frequency signal received in the offset buffer of the next odd level of the offset buffer of odd level for this reason; When reset circuit reset for the offset buffer of even level the time, the reset control signal signal that the output terminal of the offset buffer of the next stage of the offset buffer of even level provides for this reason.
Summarize it, the embodiment of the present invention for example, by the current potential (closing the output of offset buffer at specific time period) of setting up special reset circuit and adjust the output terminal of offset buffer, strengthen by this function of offset buffer, even while making offset buffer have process variation, the gate driving pulse of its output can normally be closed, do not have traction phenomena and produce.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
The accompanying drawing explanation
Fig. 1 shows the electrical block diagram of the single-stage offset buffer in a plurality of offset buffers of mutual serial connection;
Fig. 2 shows the sequential chart of a plurality of signals that are relevant to offset buffer shown in Fig. 1;
Fig. 3 A shows the structural representation of the reset circuit of first embodiment of the invention proposition;
Fig. 3 B shows another structural representation of the reset circuit of first embodiment of the invention proposition;
Fig. 4 shows the sequential chart of a plurality of signals of the offset buffer that is relevant to odd level shown in Fig. 3 A and reset circuit;
Fig. 5 A shows the structural representation of the reset circuit of second embodiment of the invention proposition;
Fig. 5 B shows another structural representation of the reset circuit of second embodiment of the invention proposition;
Fig. 6 shows the sequential chart of a plurality of signals of the offset buffer that is relevant to even level shown in Fig. 5 A and reset circuit;
Fig. 7 shows the structural representation of the reset circuit of adjacent two offset buffers that third embodiment of the invention proposes;
Fig. 8 A shows the structural representation of the reset circuit of adjacent two offset buffers that fourth embodiment of the invention proposes;
Fig. 8 B shows another structural representation of the reset circuit of adjacent two offset buffers that fourth embodiment of the invention proposes;
Fig. 9 shows the sequential chart of a plurality of signals that are relevant to adjacent two offset buffers shown in Fig. 8 A and reset circuit separately;
Figure 10 A shows the structural representation of the reset circuit of fifth embodiment of the invention proposition;
Figure 10 B shows the functional block diagram of reset circuit shown in Figure 10 A.
Wherein, Reference numeral:
SR (n), SR (n+1): offset buffer
Q (n-1), Q (n), Q (n+1): control signal
CK (n-1), CK (n), CK (n+1): frequency signal
G (n): gate driving pulse
Q (n+2), G (n+1), G (n+2): reset control signal
VGG: supply voltage
Vss: grid shutdown signal level
Q: node
T: period
T11, T12, T21, T31, T32, T41, T42, T61, T62, T71, T72, T73, T75, T91, T92, T93, T94: transistor
100: pull-down circuit
10,30,50a, 50b, 70a, 70b, 90: reset circuit
11,31,71,91: the reset circuit driver module
13,33,73,93: the replacement module
75: stop the module of resetting
O (n), E (n), OE (n): enable signal
OUT (n): the output potential of offset buffer
Embodiment
Refer to Fig. 3 A, it shows the structural representation of the reset circuit of first embodiment of the invention proposition.As shown in Figure 3A, reset circuit 10 is electrically coupled to the output terminal (for exporting gate driving pulse G (n)) of offset buffer SR (n), for the current potential of the output terminal of adjusting offset buffer SR (n); Offset buffer SR (n) in Fig. 3 A can have identical circuit structure with the offset buffer SR (n) in Fig. 1, but the present invention is not as limit; It should be noted that in addition, only in Fig. 3 A, reset circuit 10 is drawn on outside offset buffer SR (n) for ease of the difference of difference the present invention and prior art, not be used for limiting offset buffer SR (n) and whether comprise reset circuit 10.
Hold above-mentioned, the present embodiment adopts the offset buffer SR (n) of the single odd level in a plurality of offset buffers that mutually are connected in series to describe as an example, whether offset buffer SR (n) the receiving frequency signals CK (n-1) of odd level and CK (n) and control signal Q (n-1) (that is signal of the Q Nodes of the offset buffer of upper level) also determine frequency signal CK (n) conducting to its output terminal to export gate driving pulse G (n) according to control signal Q (n-1), and reset circuit 10 is electrically coupled to the output terminal of the offset buffer SR (n) of odd level.In the present embodiment, reset circuit 10 comprises reset circuit driver module 11 and replacement module 13.
Particularly, reset circuit driver module 11 receives enable signal O (n) and the output terminal of enable signal O (n) to reset circuit driver module 11 is provided; At this, reset circuit driver module 11 comprises transistor T 62, the grid of transistor T 62 (control end) is electrically coupled to reset control signal Q (n+2) so that reset control signal Q (n+2) controls whether conducting of transistor T 62 by grid, leakage/the source electrode of transistor T 62 (the first path terminal) receives enable signal O (n), and the source of transistor T 62/drain electrode (alternate path end) is as the output terminal of reset circuit driver module 11; At this, be used for controlling the signal of output terminal of the offset buffer SR (n+2) of this next one odd level in offset buffer SR (n+2) (not shown) of the next odd level that reset control signal Q (n+2) is the offset buffer SR (n) of odd level, that is the signal of the Q Nodes of the offset buffer SR (n+2) of this next one odd level.
Fig. 4 shows the sequential chart of the offset buffer SR (n) that is relevant to odd level shown in Fig. 3 A and a plurality of signals of reset circuit 10, and the course of work of the reset circuit 10 of the embodiment of the present invention is described below in conjunction with Fig. 3 A and Fig. 4.Particularly, when frequency signal CK (n) and control signal Q (n) are all as high levle, frequency signal CK (n) will be passed to the output terminal of offset buffer SR (n) of odd level as gate driving pulse G (n), and control signal Q (n) in now further by draw; After the falling edge of frequency signal CK (n), the level of control signal Q (n) (referring to the period t of Q in Fig. 4 (n)) also can be accordingly by drop-down, because reset control signal Q (n+2) now is high levle, transistor T 62 conductings in reset circuit driver module 11, the high levle of enable signal O (n) is transferred to the grid of the transistor T 61 in replacement module 13 so that transistor T 61 conductings, and the current potential of the output terminal of the offset buffer SR (n) of odd level is pulled down to grid shutdown signal level Vss fast; Even therefore the offset buffer SR (n) of odd level leaks off to grid shutdown signal level Vss ahead of time because process variation causes the level of control signal Q (n), gate driving pulse G (n), because the replacement effect of reset circuit 10 still can normally be released into grid shutdown signal level Vss, not there will be traction phenomena.At this, in offset buffer SR (n), be applied under the situation of display, the sequential of enable signal O (n) can be controlled by the time schedule controller (Timing Controller) of display, and the falling edge of the frequency signal CK (n) received at the offset buffer SR of odd level (n) is output as high levle; And the time programmable of the high levle of enable signal O (n) is adjusted, the falling edge that is not limited to CK (n) just can be exported afterwards.
Refer to Fig. 5 A, it shows the structural representation of the reset circuit of second embodiment of the invention proposition.As shown in Figure 5A, reset circuit 30 is electrically coupled to the output terminal of offset buffer SR (n+1), for the current potential of the output terminal of adjusting offset buffer SR (n+1); Offset buffer SR (n+1) in Fig. 5 A can have identical circuit structure with the offset buffer SR (n) in Fig. 1, but the present invention is not as limit; It should be noted that in addition, only in Fig. 5 A, reset circuit 30 is drawn on outside offset buffer SR (n+1) for ease of the difference of difference the present invention and prior art, not be used for limiting offset buffer SR (n+1) and whether comprise reset circuit 30.
Hold above-mentioned, the present embodiment adopts the offset buffer SR (n+1) of the single even level in a plurality of offset buffers that mutually are connected in series to describe as an example, whether offset buffer SR (n+1) the receiving frequency signals CK (n) of even level and CK (n+1) and control signal Q (n) also determine frequency signal CK (n+1) conducting to its output terminal with output gate driving pulse G (n+1) according to control signal Q (n), and reset circuit 30 is electrically coupled to the output terminal of the offset buffer SR (n+1) of even level.In the present embodiment, reset circuit 30 comprises reset circuit driver module 31 and replacement module 33.
Particularly, reset circuit driver module 31 receives enable signal E (n) and the output terminal of enable signal E (n) to reset circuit driver module 31 is provided; At this, reset circuit driver module 31 comprises transistor T 62, the grid of transistor T 62 (control end) is electrically coupled to reset control signal G (n+2) so that reset control signal G (n+2) controls whether conducting of transistor T 62 by grid, leakage/the source electrode of transistor T 62 (the first path terminal) receives enable signal E (n), and the source of transistor T 62/drain electrode (alternate path end) is as the output terminal of reset circuit driver module 31; At this, the gate driving pulse of the output terminal of the offset buffer of the next stage of the offset buffer SR (n+1) that reset control signal G (n+2) is even level output.
Fig. 6 shows the sequential chart of the offset buffer SR (n+1) that is relevant to even level shown in Fig. 5 A and a plurality of signals of reset circuit 30, and the course of work of the reset circuit 30 of the embodiment of the present invention is described below in conjunction with Fig. 5 A and Fig. 6.Particularly, as frequency signal CK (n+1) and control signal Q (n+1) while being all high levle, frequency signal CK (n+1) will be passed to the output terminal of offset buffer SR (n+1) of even level as gate driving pulse G (n+1), and now control signal Q (n+1) further by draw; After the falling edge of frequency signal CK (n+1), the level of control signal Q (n+1) (referring to the period t of Q in Fig. 6 (n+1)) also can be correspondingly by drop-down, because reset control signal G (n+2) now is high levle, transistor T 62 conductings in reset circuit driver module 31, the high levle of enable signal E (n) is transferred to the grid of the transistor T 61 in replacement module 33 so that transistor T 61 conductings, and the current potential of the output terminal of the offset buffer SR (n+1) of even level is pulled down to grid shutdown signal level Vss fast; Even therefore the offset buffer SR (n+1) of even level leaks off to grid shutdown signal level Vss ahead of time because process variation causes the level of control signal Q (n+1), gate driving pulse G (n+1), because the replacement effect of reset circuit 30 still can normally be released into grid shutdown signal level Vss, not there will be traction phenomena.At this, in offset buffer SR (n+1), be applied under the situation of display, the sequential of enable signal E (n) can be controlled by the time schedule controller of display, and the falling edge of the frequency signal CK (n+1) received at the offset buffer SR of even level (n+1) is output as high levle; And the time programmable of the high levle of enable signal E (n) is adjusted, the falling edge that is not limited to CK (n+1) just can be exported afterwards.
Refer to Fig. 7, it shows the structural representation of the reset circuit of adjacent two offset buffers that third embodiment of the invention proposes.In Fig. 7, its offset buffer with odd level SR (n) and the offset buffer SR (n+1) of adjacent even level describe as an example; Wherein, whether offset buffer SR (n) the receiving frequency signals CK (n-1) of odd level and CK (n) and control signal Q (n-1) also determine frequency signal CK (n) conducting to its output terminal with generation gate driving pulse G (n) according to control signal Q (n-1), and the reset circuit 50a of output terminal of offset buffer SR (n) that is electrically coupled to odd level is identical with the reset circuit 10 shown in Fig. 3 A, all the control signal of the Q Nodes of the offset buffer of employing next odd level separately is as reset control signal, therefore its circuit structure does not repeat them here.Whether offset buffer SR (n+1) the receiving frequency signals CK (n) of even level and CK (n+1) and control signal Q (n) also determine frequency signal CK (n+1) conducting to its output terminal with generation gate driving pulse G (n+1) according to control signal Q (n), and the reset circuit 50b of output terminal of offset buffer SR (n+1) that is electrically coupled to even level is identical with the reset circuit 30 shown in Fig. 5 A, all the gate driving pulse of the offset buffer output of employing next stage separately is as reset control signal, therefore its circuit structure does not repeat them here.In brief, in the 3rd embodiment, the reset control signal Q (n+2) that the reset circuit 50a of the offset buffer SR (n) of odd level is used is different from the reset control signal G (n+2) that the reset circuit 50b of the offset buffer SR (n+1) of even level is used, one is used the control signal of Q Nodes as reset control signal, and another one is used gate driving pulse as reset control signal.
Refer to Fig. 8 A, it shows the structural representation of the reset circuit of adjacent two offset buffers that fourth embodiment of the invention proposes.In Fig. 8 A, its offset buffer with odd level SR (n) and the offset buffer SR (n+1) of adjacent even level describe as an example, and offset buffer SR (n) and SR (n+1) can have identical circuit structure with the offset buffer SR (n) shown in Fig. 1, but the present invention is not as limit; Wherein, whether offset buffer SR (n) the receiving frequency signals CK (n-1) of odd level and CK (n) and control signal Q (n-1) also determines frequency signal CK (n) conducting to its output terminal to produce gate driving pulse G (n) according to control signal Q (n-1), and the reset circuit 70a of output terminal that is electrically coupled to the offset buffer SR (n) of odd level comprises reset circuit driver module 71, replacement module 73 and the module 75 that stops resetting.It should be noted that in addition, in Fig. 8 A, reset circuit 70a is drawn on outside the offset buffer SR (n) of odd level only for ease of the difference of difference the present invention and prior art, not is used for limiting the offset buffer SR (n) whether reset circuit 70a is contained in odd level.
Particularly, the reset circuit driver module in reset circuit 70a 71 receives enable signal Q (n) and the output terminal of enable signal Q (n) to reset circuit driver module 71 is provided; At this, reset circuit driver module 71 comprises transistor T 71 and T72, the grid of transistor T 72 (control end) receives enable signal O (n) with leakage/source electrode (the first path terminal), the grid of transistor T 71 (control end) is electrically coupled to the source of transistor T 72/drain electrode (alternate path end), leakage/the source electrode of transistor T 71 (the first path terminal) receives enable signal O (n), and the source of transistor T 71/drain electrode (alternate path end) is as the output terminal of reset circuit driver module 71.
Replacement module 73 in reset circuit 70a is electrically coupled to the output terminal of offset buffer SR (n) of odd level and the output terminal of reset circuit driver module 71, with the control of Electric potentials replacement module 73 of the output terminal by reset circuit driver module 71 whether conducting be positioned at the output terminal of offset buffer SR (n) of odd level to the electrical path between grid shutdown signal level Vss.Replacement module 73 comprises transistor T 75, and the grid of transistor T 75 (control end) is electrically coupled to the source of transistor T 71/drain electrode, makes current potential in the source/drain electrode of transistor T 71 whether control turn-on transistor T75 by the grid of transistor T 75; Leakage/the source electrode of transistor T 75 (the first path terminal) is electrically coupled to the output terminal of the offset buffer SR (n) of odd level; The source of transistor T 75/drain electrode (alternate path end) is electrically coupled to grid shutdown signal level Vss (the first preset potential).At this, it should be noted that, the source of transistor T 75/drain electrode is not limited to be electrically coupled to grid shutdown signal level Vss, also can be electrically coupled to as shown in Figure 8 B frequency signal CK (n), can obtain equally grid shutdown signal level.
The module 75 of resetting of stopping in reset circuit 70a is electrically coupled to the output terminal of offset buffer SR (n) of odd level and the output terminal of reset circuit driver module 71, and the current potential of the output terminal of its offset buffer according to odd level SR (n) determines that the output terminal of conducting reset circuit driver module 71 whether is to the electrical path between grid shutdown signal level Vss.Particularly, the module 75 that stops resetting comprises transistor T 73, the grid of transistor T 73 (control end) is electrically coupled to the output terminal of the offset buffer SR (n) of odd level, so that whether the current potential of the output terminal of the offset buffer SR (n) of odd level controls turn-on transistor T73 by grid; Leakage/the source electrode of transistor T 73 (the first path terminal) is electrically coupled to the output terminal of reset circuit driver module 71, and the source of transistor T 73/drain electrode (alternate path end) is electrically coupled to grid shutdown signal level Vss (the second preset potential).
In addition, whether offset buffer SR (n+1) the receiving frequency signals CK (n) of the even level in Fig. 8 A and CK (n+1) and control signal Q (n) also determine frequency signal CK (n+1) conducting to its output terminal with generation gate driving pulse G (n+1) according to control signal Q (n), and the reset circuit 70b of output terminal that is electrically coupled to the offset buffer SR (n+1) of even level has identical circuit structure with reset circuit 70a, all comprise reset circuit driver module 71, replacement module 73 and the module 75 that stops resetting, difference only is: reset circuit 70a is used enable signal O (n), and reset circuit 70b is used enable signal E (n).It should be noted that in addition, in Fig. 8 A, reset circuit 70b is drawn on outside the offset buffer SR (n+1) of even level only for ease of the difference of difference the present invention and prior art, whether the offset buffer SR (n+1) that not is used for limiting even level comprises reset circuit 70b.
Fig. 9 shows the sequential chart of a plurality of signals that are relevant to offset buffer SR shown in Fig. 8 A (n) and SR (n+1) and reset circuit 70a separately and 70b, below in conjunction with Fig. 8 A and Fig. 9, the reset circuit 70a of the embodiment of the present invention and the course of work of 70b is described.Particularly, when frequency signal CK (n) is high levle, its will be passed to odd level offset buffer SR (n) output terminal as gate driving pulse G (n) and control signal Q (n) further by draw, transistor T 73 conductings that now make to stop to reset in module 75 for high levle due to gate driving pulse G (n), and then transistor T 75 cut-offs in the module 73 that makes to reset and reach and stop the purpose of resetting; After the falling edge of frequency signal CK (n), the level of control signal Q (n) (referring to the t period of Q in Fig. 9 (n)) also can be accordingly by drop-down, because enable signal O (n) is high levle, transistor T 71 in reset circuit driver module 71 and all conductings of T72, the high levle of enable signal O (n) is transferred to the grid of the transistor T 75 in replacement module 73 so that transistor T 75 conductings, the current potential of the output terminal of the offset buffer SR (n) of odd level is pulled down to grid shutdown signal level Vss fast, and transistor T 73 cut-offs in the module 75 that now stops resetting; Even therefore the offset buffer SR (n) of odd level leaks off to grid shutdown signal level Vss ahead of time because process variation causes the level of control signal Q (n), gate driving pulse G (n), because the replacement effect of reset circuit 70a still can normally be released into grid shutdown signal level Vss, not there will be traction phenomena.The course of work for the reset circuit 70b of the offset buffer SR (n+1) of even level and reset circuit 70a is similar, therefore repeat no more.
In addition, in fourth embodiment of the invention, when offset buffer SR (n) and SR (n+1) are applied under the situation of display, the sequential of enable signal O (n) and E (n) can be controlled by the time schedule controller of display, and the frequency signal CK (n) received at offset buffer SR (n) separately and SR (n+1) or the falling edge of CK (n+1) are output as high levle; And the time programmable of the high levle of enable signal O (n) and E (n) is adjusted, the falling edge that is not limited to corresponding CK (n) or CK (n+1) just can be exported afterwards.
Refer to Figure 10 A, it shows the structural representation of the reset circuit of fifth embodiment of the invention proposition.As shown in Figure 10 A, reset circuit 90 is electrically coupled to the output terminal of offset buffer SR (n), for the current potential OUT (n) of the output terminal of adjusting offset buffer SR (n); Offset buffer SR (n) in Figure 10 A can have identical circuit structure with the offset buffer SR (n) in Fig. 1, but the present invention is not as limit; It should be noted that in addition, only in Figure 10 A, reset circuit 90 is drawn on outside offset buffer SR (n) for ease of the difference of difference the present invention and prior art, not be used for limiting offset buffer SR (n) and whether comprise reset circuit 90.
Hold above-mentioned, in a plurality of offset buffers that the present embodiment employing is connected in series mutually, the offset buffer SR (n) of arbitrary grade describes as an example, whether offset buffer SR (n) receiving frequency signals CK (n-1) and CK (n) and control signal Q (n-1) (that is signal of the Q Nodes of the offset buffer of upper level) also determine frequency signal CK (n) conducting to its output terminal to export OUT (n) according to control signal Q (n-1), and reset circuit 90 is electrically coupled to the output terminal of offset buffer SR (n).In the present embodiment, reset circuit 90 comprises reset circuit driver module 91 and replacement module 93.Reset circuit driver module 91 receives enable signal OE (n) to control current potential to the module 93 of resetting in its output terminal output by this.
Particularly, reset circuit driver module 91 is electrically coupled to for example grid shutdown signal level Vss (the second preset potential) of supply voltage VGG and preset potential, and receives the output potential OUT (n) of enable signal OE (n) and offset buffer SR (n).At this, reset circuit driver module 91 comprises transistor T 91, T92 and T93; The grid of transistor T 91 (control end) is with leakage/source electrode (the first path terminal) phase electric property coupling and receive supply voltage VGG, and the source of transistor T 91/drain electrode (alternate path end) is electrically coupled to the output terminal of reset circuit driver module 91; The output terminal that the grid of transistor T 92 (control end) is electrically coupled to offset buffer SR (n) to be to receive OUT (n), and the leakage/source electrode of transistor T 92 (the first path terminal) is electrically coupled to the source of transistor T 91/drain electrode; The grid of transistor T 93 (control end) receives enable signal OE (n), leakage/the source electrode of transistor T 93 (the first path terminal) is electrically coupled to the source of transistor T 92/drain electrode (alternate path end), and the source of transistor T 93/drain electrode (alternate path end) is electrically coupled to grid shutdown signal level Vss.
From Figure 10 A, in the course of work of reset circuit 90, as OUT (n) and OE (n) while being all high levle, transistor T 92 in reset circuit driver module 91, the T93 conducting, making the transistor T 94 in replacement module 93 is that low level ends because of the control current potential on its grid, and gate driving pulse G (n) is identical with OUT (n), also is high levle; Otherwise, when OUT (n) and OE (n) any one or both are all low level, transistor T 92 in reset circuit driver module 91, in T93, at least one is in cut-off state, making the transistor T 94 in replacement module 93 is the high levle conducting because of the control current potential on its grid, and OUT (n) is pulled to grid shutdown signal level Vss and gate driving pulse G (n) after making adjustment is rendered as low level; So gate driving pulse G (n), because the replacement effect of reset circuit 90 still can normally be released into grid shutdown signal level Vss, not there will be traction phenomena.At this, in offset buffer SR (n), be applied under the situation of display, the sequential of enable signal OE (n) can be controlled by the time schedule controller (Timing Controller) of display.
From the course of work of above-mentioned reset circuit 90, reset circuit 90 is played the part of the function of AND circuit, example functional block diagram as shown in Figure 10 B.In other words, fifth embodiment of the invention utilizes AND circuit to solve the traction phenomena in prior art as reset circuit, so it should be noted that, particular circuit configurations in reset circuit 90 shown in Figure 10 A is only a kind of enforcement kenel of AND circuit, not is used for limiting the particular circuit configurations of AND circuit.
In sum, the embodiment of the present invention for example, by the current potential (specific time period is closed the output of offset buffer) of setting up special reset circuit and adjust the output terminal of offset buffer, strengthen by this function of offset buffer, even while making offset buffer have process variation, the gate driving pulse of its output can normally be closed, do not have traction phenomena and produce.
Although the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when doing a little change and modification, so protection scope of the present invention is as the criterion when looking accompanying the claim scope of patent protection person of defining.
Claims (17)
1. a reset circuit, be applicable to adjust the current potential of the output terminal of an offset buffer, it is characterized in that, this reset circuit comprises:
One reset circuit driver module, receive an activation signal and control current potential to export one at the output terminal of this reset circuit driver module by this; And
One replacement module, be electrically coupled to the output terminal of this offset buffer and the output terminal of this reset circuit driver module, this of the output terminal of this reset circuit driver module output controlled the whether electrical path of conducting between output terminal to the first grid shutdown signal current potential of this offset buffer of this replacement module of control of Electric potentials;
This reset circuit driver module comprises:
One the first transistor comprises:
One control end, be electrically coupled to a reset control signal so that this reset control signal is controlled the whether conducting of this first transistor by this control end;
One first path terminal, receive this enable signal; And
One alternate path end, be electrically coupled to the output terminal of this offset buffer.
2. reset circuit as claimed in claim 1, it is characterized in that, the offset buffer of the odd level in those offset buffers that this offset buffer that this reset circuit is reset is mutual serial connection, and whether be provided to the signal of output terminal of the offset buffer of this next one odd level in the offset buffer of the next odd level of this reset control signal offset buffer that is this odd level in order to control the corresponding frequency signal received.
3. reset circuit as claimed in claim 2, is characterized in that, this replacement module comprises:
One transistor seconds comprises:
One control end, be electrically coupled to this alternate path end of this first transistor, makes current potential on this alternate path end of this first transistor whether control this transistor seconds of conducting by this control end of this transistor seconds;
One first path terminal, be electrically coupled to the output terminal of the offset buffer of this odd level; And
One alternate path end, be electrically coupled to this first grid shutdown signal current potential.
4. reset circuit as claimed in claim 1, it is characterized in that, the offset buffer of the even level in those offset buffers that this offset buffer that this reset circuit is reset is mutual serial connection, and the signal that provides of the output terminal of the offset buffer of the next stage of this reset control signal offset buffer that is this even level.
5. reset circuit as claimed in claim 4, is characterized in that, this replacement module comprises:
One transistor seconds comprises:
One control end, be electrically coupled to this alternate path end of this first transistor, makes current potential on this alternate path end of this first transistor whether control this transistor seconds of conducting by this control end of this transistor seconds;
One first path terminal, be electrically coupled to the output terminal of the offset buffer of this even level; And
One alternate path end, be electrically coupled to this first grid shutdown signal current potential,
Wherein, whether the offset buffer of this even level determines the output terminal to the offset buffer of this even level by a frequency signal conducting according to the output signal of the offset buffer of previous stage, and the current potential of this first grid shutdown signal current potential while for this frequency signal, being transferred to the offset buffer of this even level.
6. reset circuit as claimed in claim 1, is characterized in that, also comprises:
One stops the module of resetting, be electrically coupled to the output terminal of this offset buffer and the output terminal of this reset circuit driver module, this module that stops resetting determines the electrical path between output terminal to the second grid shutdown signal current potential of this reset circuit driver module of conducting whether according to the current potential of the output terminal of this offset buffer.
7. reset circuit as claimed in claim 6, is characterized in that, this reset circuit driver module comprises:
One the first transistor, comprise control end, the first path terminal and alternate path end, and the control end of this first transistor and the first path terminal receive this enable signal; And
One transistor seconds, comprise control end, the first path terminal and alternate path end, the control end of this transistor seconds is electrically coupled to the alternate path end of this first transistor, the first path terminal of this transistor seconds receives this enable signal, and the alternate path end of this transistor seconds is as the output terminal of this reset circuit driver module.
8. reset circuit as claimed in claim 6, is characterized in that, this module that stops resetting comprises:
One transistor comprises:
One control end, be electrically coupled to the output terminal of this offset buffer, so that whether the current potential of the output terminal of this offset buffer controls this transistor of conducting by this control end;
One first path terminal, be electrically coupled to the output terminal of this reset circuit driver module; And
One alternate path end, be electrically coupled to this second grid shutdown signal current potential.
9. reset circuit as claimed in claim 6, is characterized in that, this replacement module comprises:
One transistor comprises:
One control end, be electrically coupled to the output terminal of reset circuit driver module, makes the current potential of the output terminal of this reset circuit driver module whether control this transistor of conducting by this transistorized this control end;
One first path terminal, be electrically coupled to the output terminal of this offset buffer; And
One alternate path end, be electrically coupled to this first grid shutdown signal current potential.
10. reset circuit as claimed in claim 9, is characterized in that, this first grid shutdown signal current potential is equal to this second grid shutdown signal current potential.
11. reset circuit as claimed in claim 9, it is characterized in that, whether this offset buffer determines the output terminal to this offset buffer by a frequency signal conducting according to a prime output signal, and the current potential of this first grid shutdown signal current potential while for this frequency signal, being transferred to this offset buffer.
12. reset circuit as claimed in claim 1, it is characterized in that, this reset circuit driver module more receives the current potential of this output terminal of this offset buffer, and this reset circuit driver module and this replacement module are common forms an AND circuit and carry out the logical AND gate computing with the current potential of this output terminal to this enable signal and this offset buffer.
13. reset circuit as claimed in claim 1, is characterized in that, this reset circuit driver module comprises:
One the first transistor, the control end of this first transistor is with the first path terminal phase electric property coupling and receive a supply voltage, and the alternate path end of this first transistor is electrically coupled to this output terminal of this reset circuit driver module;
One transistor seconds, the control end of this transistor seconds is electrically coupled to this output terminal of this offset buffer, and the first path terminal of this transistor seconds is electrically coupled to this output terminal of this reset circuit driver module; And
One the 3rd transistor, the 3rd transistorized control end receives this enable signal, the 3rd transistorized the first path terminal is electrically coupled to the alternate path end of this transistor seconds, and the 3rd transistorized alternate path termination is received a second grid shutdown signal current potential.
14. reset circuit as claimed in claim 13, is characterized in that, this replacement module comprises:
One the 4th transistor, the 4th transistorized control end is electrically coupled to this output terminal of this reset circuit driver module, the 4th transistorized the first path terminal is electrically coupled to this output terminal of this offset buffer, and the 4th transistorized alternate path termination is received this first grid shutdown signal current potential.
15. a reset circuit, be applicable to adjust the current potential of the output terminal of an offset buffer, this reset circuit comprises:
One reset circuit driver module, control whether provide the output terminal of an activation signal to this reset circuit driver module according to a reset control signal; And
One replacement module, be electrically coupled to the output terminal of this offset buffer and the output terminal of this reset circuit driver module, whether this replacement module of the control of Electric potentials of the output terminal of this reset circuit driver module the electrical path of conducting between output terminal to the first grid shutdown signal current potential of this offset buffer
Wherein, this reset circuit is in order to an offset buffer in a plurality of offset buffers of the mutual serial connection reset,
The reset control signal of using during offset buffer that wherein, the reset control signal of using and this offset buffer of resetting when this reset circuit are the even level in mutual those offset buffers that are connected in series during the offset buffer of the odd level in those offset buffers that this offset buffer that this reset circuit is reset is serial connection mutually is different;
This reset circuit driver module comprises:
One the first transistor comprises:
One control end, be electrically coupled to this reset control signal so that this reset control signal is controlled the whether conducting of this first transistor by this control end;
One first path terminal, receive this enable signal; And
One alternate path end, be electrically coupled to the output terminal of this offset buffer.
16. reset circuit as claimed in claim 15, it is characterized in that, when this reset circuit reset for the offset buffer of this odd level the time, whether be provided to the signal of output terminal of the offset buffer of this next one odd level in the offset buffer of the next odd level of the offset buffer that this reset control signal is this odd level in order to control the corresponding frequency signal received.
17. reset circuit as claimed in claim 15, it is characterized in that, when this reset circuit reset for the offset buffer of this even level the time, the signal that the output terminal of the offset buffer of the next stage of the offset buffer that this reset control signal is this even level provides.
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| TW099147034 | 2010-12-30 | ||
| TW99147034 | 2010-12-30 |
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| CN2011101037620A Pending CN102184699A (en) | 2010-12-30 | 2011-04-20 | Reset circuit |
| CN201110334615.4A Active CN102592553B (en) | 2010-12-30 | 2011-10-26 | Reset circuit |
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| CN102184699A (en) * | 2010-12-30 | 2011-09-14 | 友达光电股份有限公司 | Reset circuit |
| TWI493871B (en) | 2012-06-05 | 2015-07-21 | Au Optronics Corp | Shift register circuitry, display and shift register |
| CN102915698B (en) * | 2012-10-18 | 2016-02-17 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| TWI537912B (en) * | 2014-07-21 | 2016-06-11 | 友達光電股份有限公司 | Shift register and flat panel display using the same |
| CN105913822B (en) * | 2016-06-23 | 2018-07-17 | 京东方科技集团股份有限公司 | GOA signal judging circuits and judgment method, gate driving circuit and display device |
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| CN101567219A (en) * | 2008-04-25 | 2009-10-28 | 北京京东方光电科技有限公司 | Shift register and grid drive circuit for liquid crystal display |
| CN101752006A (en) * | 2009-12-25 | 2010-06-23 | 友达光电股份有限公司 | Shift register |
| CN102184699A (en) * | 2010-12-30 | 2011-09-14 | 友达光电股份有限公司 | Reset circuit |
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| JP4310939B2 (en) * | 2001-06-29 | 2009-08-12 | カシオ計算機株式会社 | Shift register and electronic device |
| KR20060020324A (en) * | 2004-08-31 | 2006-03-06 | 엘지.필립스 엘시디 주식회사 | Built-in gate driver and display device having the same |
| JP4990034B2 (en) * | 2006-10-03 | 2012-08-01 | 三菱電機株式会社 | Shift register circuit and image display apparatus including the same |
| CN101546607B (en) * | 2008-03-26 | 2012-02-29 | 北京京东方光电科技有限公司 | Shift register and grid driving device for liquid crystal display |
| CN101699552B (en) * | 2009-11-16 | 2012-04-18 | 友达光电股份有限公司 | Grid output control method and corresponding grid pulse modulator |
| CN201567219U (en) * | 2009-12-21 | 2010-09-01 | 安丘市鼎正机械设备有限公司 | Filling device for filling machine |
| CN101826315B (en) * | 2010-05-06 | 2012-06-27 | 友达光电股份有限公司 | Liquid crystal display device |
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| CN101567219A (en) * | 2008-04-25 | 2009-10-28 | 北京京东方光电科技有限公司 | Shift register and grid drive circuit for liquid crystal display |
| CN101533622A (en) * | 2009-02-26 | 2009-09-16 | 深圳华映显示科技有限公司 | Source driver and drive method for liquid crystal display |
| CN101752006A (en) * | 2009-12-25 | 2010-06-23 | 友达光电股份有限公司 | Shift register |
| CN102184699A (en) * | 2010-12-30 | 2011-09-14 | 友达光电股份有限公司 | Reset circuit |
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| CN102592553A (en) | 2012-07-18 |
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