CN102571316A - Closed-loop timing adjustment method for wireless communication system - Google Patents
Closed-loop timing adjustment method for wireless communication system Download PDFInfo
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- CN102571316A CN102571316A CN2011104599418A CN201110459941A CN102571316A CN 102571316 A CN102571316 A CN 102571316A CN 2011104599418 A CN2011104599418 A CN 2011104599418A CN 201110459941 A CN201110459941 A CN 201110459941A CN 102571316 A CN102571316 A CN 102571316A
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Abstract
A closed-loop timing adjustment method for a wireless communication system comprises the following steps: input discrete series with high sampling rate are subjected to down-sampling to obtain discrete series with low sampling rate; the series subjected to down-sampling are synchronized to obtain a synchronous head; the position of the synchronous head obtained at the first time is taken as a target position; subtraction is carried out between the positions of synchronous head output by the synchronous module thereafter and the target position; the difference value is subjected to treatment of a proportional integrator to obtain a proportional integral quantity, and vice versa, the down-sampling rate is readjusted; the series subjected to down-sampling are input into a buffering RAM for caching; and when encountering the synchronous heads, the series jump to the head part of the RAM for continuous cyclic writing, so as to achieve similar cyclic data reading, as well as zero adding at the frame end or frame end removal for making up the whole frame. The method provided by the invention can overcome sampling distortion at the receiving end in a self-adapting manner, adjust the received data frames into fixed-length frames with the same lengths as the sending end, and effectively solve the self-excitation problem caused by a closed loop while ensuring the tracking performance.
Description
Technical field
The invention belongs to the mobile wireless data transmission technique field, relate to a kind of wireless communication system closed loop timing adjusting method.
Background technology
In wireless communication system, regularly adjust most important.Because problems such as manufacture craft restriction; The not strict coupling of transmitting terminal and receiving terminal clock rate; Cause receiving terminal to carry out over-sampling or owe sampling in the air for the analog signal that sends over; And make the discrete data frame that receives and be not equal to the frame length that sends Frame, but demonstrated certain randomness.The redundancy that this has just caused losing of information or has increased information.
For fear of the generation of this phenomenon, carry out rising sample rate at transmitting terminal, sample rate is fallen at receiving terminal.When falling sampling, carry out the timing adjustment, just can guarantee that receiving terminal receives the fixed length frame isometric with transmitting terminal.
Traditional timing adjusting method or capture range are lost tracking inadequately easily, or self-excitation easily.
Summary of the invention
In order to overcome the deficiency of above-mentioned prior art; The object of the present invention is to provide a kind of wireless communication system closed loop timing adjusting method; To regularly adjusting error carries out proportional integral; As close-loop feedback, can when guaranteeing tracking performance, effectively solve the caused self-excitation problem of closed loop with the proportional integral result.
To achieve these goals, the technical scheme of the present invention's employing is:
A kind of wireless communication system closed loop timing adjusting method, said method realizes successively according to the following steps:
Step 1: fall sampling with falling the high sampling rate discrete series of the controlled closed-loop feedback manner of sampling ratio self adaptation, obtain the low sampling rate discrete series, realize according to the following steps successively to input:
Step 1.1: with the ratio of the low sampling rate exact value of the high sampling rate exact value of the list entries of system default and output sequence, sample rate falls in initialization;
Step 1.2: the sampling ratio that falls that obtains according to last self adaptation adjustment falls sampling to the high sampling rate discrete series of importing, output low sampling rate discrete series;
Step 1.3: the sequence to falling after the sampling obtains synchronous head synchronously;
Step 1.4: as the target location, it is poor that do respectively the synchronous head position of synchronization module output afterwards and target location the synchronous head position that obtains for the first time, and difference obtains proportional integral value through the proportional integral device;
Step 1.5: readjust conversely with proportional integral value and to fall the sampling ratio;
Step 2: the low sampling rate discrete series to step 1 output is adjusted according to the following steps, obtains the receiving terminal Frame that equates with the transmitting terminal frame length, realization according to the following steps successively:
Step 2.1: fall sequence after the sampling and be input to buffer RAM and carry out buffer memory; Jump to the RAM first address at every turn when writing RAM tail address and continue write data; The write data that so circulates, the synchronous head that at every turn arrives jumps to the circulation write operation that the RAM first address restarts new frame data;
Step 2.2: reading of data obtains adjusting later receiving terminal Frame from buffer RAM; The read data address lags behind the write data address; Jump to the RAM first address at every turn when reading RAM tail address and continue read data; The read data that so circulates, frame end in reading buffer RAM and when not exporting current frame data fully, continue the full present frame of the several spot patch of output again; When not reading the frame end in the buffer RAM, jump to the RAM first address and continue output next frame data and give up the data of not reading when the data of having exported a whole frame.
Describedly fall sampling and be meant the high sampling rate discrete series is extracted according to falling sample rate, obtain the method for low sampling rate discrete series; Described fall the sampling ratio be the data transfer rate ratio of high sampling rate sequence and low sampling rate sequence.
Thereby described is to mark the data frame head to obtain synchronous head synchronously.
In the said step 1.3, all differences are added up, current synchronous error multiply by after the fixed proportion coefficient r, on the accumulated value that is added to, as the output of proportional integral.
In the said step 2.2, in the frame structure design, added protection at interval, made that the postamble data are zero.
The present invention is a kind of closed loop configuration, can self adaptation be adjusted into the fixed length frame isometric with transmitting terminal to the Frame that receives.Closed loop timing adjusting method of the present invention can self adaptation overcome because the receiving terminal sampling distortion that the transceiver clock rate does not match and causes is adjusted into the fixed length frame isometric with transmitting terminal to the Frame that receives.It is poor that do each synchronous head position and target location, falls the sampling ratio with difference through the proportional integral value adjustment that the proportional integral device obtains, and can when guaranteeing tracking performance, effectively solve the caused self-excitation problem of closed loop.
Description of drawings
Fig. 1 is a wireless communication system closed loop timing adjusting method flow chart according to the invention.
Fig. 2 is that wireless communication system closed loop timing adjusting method hardware according to the invention is realized block diagram.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is explained further details.
As shown in Figure 1, be timing adjusting method flow chart of the present invention, step is following:
At first, sampling falls in the discrete series with high sampling rate, obtains the low sampling rate discrete series, and implementation method is following: with the ratio of the low sampling rate exact value of the high sampling rate exact value of the list entries of system default and output sequence, sample rate falls in initialization; The sampling ratio that falls that obtains according to last self adaptation adjustment falls sampling to the high sampling rate discrete series of importing, output low sampling rate discrete series; Sequence to falling after the sampling obtains synchronous head synchronously; As the target location, it is poor that do respectively the synchronous head position of synchronization module output afterwards and target location the synchronous head position that obtains for the first time, and difference obtains proportional integral value through the proportional integral device; Readjust conversely with proportional integral value and to fall the sampling ratio;
Secondly; Need adjust according to the following steps the low sampling rate discrete series of output; With the receiving terminal Frame that obtains equating with the transmitting terminal frame length: fall sequence after the sampling and be input to buffer RAM and carry out buffer memory, jump to the RAM first address at every turn when writing RAM tail address and continue write data, write data so circulates; Each synchronous head that arrives jumps to the circulation write operation that the RAM first address restarts new frame data; Reading of data obtains adjusting later receiving terminal Frame from buffer RAM then; The read data address lags behind the write data address; Jump to the RAM first address at every turn when reading RAM tail address and continue read data; The read data that so circulates, frame end in reading buffer RAM and when not exporting current frame data fully, continue the full present frame of the several spot patch of output again; When not reading the frame end in the buffer RAM, jump to the RAM first address and continue output next frame data and give up the data of not reading when the data of having exported a whole frame.
In order to further specify implementation method of the present invention, we have provided a kind of hardware implementations, suppose that high sampling rate discrete series frame length is about 2457600, and target low sampling rate frame length is 1228800, and concrete performing step is:
The sample rate module falls in step 1:DEC, and inside comprises a NCO that can join (digital controlled oscillator) module, can shake the digit pulse that produces assigned frequency.Low sampling rate pulse through controlling inner NCO generation is extracted as the discrete series of enable signal to high sampling rate; Just can obtain the discrete series of low sampling rate, what the data transfer rate ratio of high sampling rate sequence and low sampling rate sequence was referred to as DEC falls the sampling ratio.Fall the sampling ratio to what thereby DEC fed back input control DEC, constitute closed loop configuration, the frame length of self adaptation adjustment receiving terminal Frame is about 1228800.Realize according to the following steps successively:
Step 1.1: it is 2457600 that the sampling ratio falls in initialization: 1228800=2.
Step 1.2: adjustment obtains according to last self adaptation falls the sampling ratio, and the high sampling rate discrete series to input in DEC extracts and interpolation, and output frame length is about 1228800 low sampling rate discrete series.
Step 1.3: transmitting terminal inserts known array at the data frame head, and receiving terminal obtains synchronous head synchronously to the sequence of falling after the sampling.
Step 1.4: the synchronous head position that obtains for the first time as the target location; It is poor that do respectively the synchronous head position of synchronization module output afterwards and target location, and difference is added up, and current synchronous error multiply by after the fixed proportion coefficient r; Be added on the accumulated value, as the output of proportional integral.
Step 1.5: with the input of proportional integral value as DEC, the sampling ratio falls in adjustment DEC.
Step 2: it is 1228800 fixed length frame that the low sampling rate discrete series of step 1 output is adjusted into length according to the following steps:
Step 2.1: fall sequence after the sampling and be input to buffer RAM and carry out buffer memory, jump to the RAM first address at every turn when writing RAM tail address and continue write data, write data so circulates.Each synchronous head that arrives jumps to the circulation write operation that the RAM first address restarts new frame data.
Step 2.2: the read data address lags behind the write data address, the read data that similarly circulates operation, and here we set backward write data address, read data address 100.Safeguard a counter, the count range of counter is greater than 1228799, when the RAM first address begins to read in first data of present frame, is changed to 0 to counter at every turn, after this whenever reads in a data counter and adds one.When frame end in reading buffer RAM and counter no show 1228799, continue to read several again and zero make counter reach 1228799; When counter has arrived 1228799 and when not reading the frame end in the buffer RAM, jump to the RAM first address and continue output next frame data and give up the data of not reading.
More than the said hardware of invention realizes that block diagram is as shown in Figure 2.
The foregoing description just is used to specify wireless communication system closed loop timing adjusting method of the present invention; Concrete data wherein just arbitrarily are provided with for explanation; Can not be in order to limit protection scope of the present invention; Promptly as long as implement by the described step of this claim, wherein any variation of data all should belong to protection category of the present invention.
Claims (5)
1. a wireless communication system closed loop timing adjusting method is characterized in that, realizes according to the following steps successively:
Step 1: fall sampling with falling the high sampling rate discrete series of the controlled closed-loop feedback manner of sampling ratio self adaptation, obtain the low sampling rate discrete series, realize according to the following steps successively to input:
Step 1.1: with the ratio of the low sampling rate exact value of the high sampling rate exact value of the list entries of system default and output sequence, sample rate falls in initialization;
Step 1.2: the sampling ratio that falls that obtains according to last self adaptation adjustment falls sampling to the high sampling rate discrete series of importing, output low sampling rate discrete series;
Step 1.3: the sequence to falling after the sampling obtains synchronous head synchronously;
Step 1.4: as the target location, it is poor that do respectively the synchronous head position of synchronization module output afterwards and target location the synchronous head position that obtains for the first time, and difference obtains proportional integral value through the proportional integral device;
Step 1.5: readjust conversely with proportional integral value and to fall the sampling ratio;
Step 2: the low sampling rate discrete series to step 1 output is adjusted according to the following steps, obtains the receiving terminal Frame that equates with the transmitting terminal frame length, realization according to the following steps successively:
Step 2.1: fall sequence after the sampling and be input to buffer RAM and carry out buffer memory; Jump to the RAM first address at every turn when writing RAM tail address and continue write data; The write data that so circulates, the synchronous head that at every turn arrives jumps to the circulation write operation that the RAM first address restarts new frame data;
Step 2.2: reading of data obtains adjusting later receiving terminal Frame from buffer RAM; The read data address lags behind the write data address; Jump to the RAM first address at every turn when reading RAM tail address and continue read data; The read data that so circulates, frame end in reading buffer RAM and when not exporting current frame data fully, continue the full present frame of the several spot patch of output again; When not reading the frame end in the buffer RAM, jump to the RAM first address and continue output next frame data and give up the data of not reading when the data of having exported a whole frame.
2. wireless communication system closed loop timing adjusting method according to claim 1 is characterized in that, describedly falls sampling and is meant the high sampling rate discrete series is extracted according to falling sample rate, obtains the method for low sampling rate discrete series; Described fall the sampling ratio be the data transfer rate ratio of high sampling rate sequence and low sampling rate sequence.
3. wireless communication system closed loop timing adjusting method according to claim 1 is characterized in that, thus described be to mark the data frame head to obtain synchronous head synchronously.
4. wireless communication system closed loop timing adjusting method according to claim 1 is characterized in that, in the said step 1.3; All differences are added up; Current synchronous error multiply by after the fixed proportion coefficient r, on the accumulated value that is added to, as the output of proportional integral.
5. wireless communication system closed loop timing adjusting method according to claim 1 is characterized in that, in the said step 2.2, in the frame structure design, has added protection at interval, makes that the postamble data are zero.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105676222A (en) * | 2015-10-30 | 2016-06-15 | 中国人民解放军空军工程大学 | Synthetic aperture radar data adaptive compression and fast reconstruction method |
| CN114280977A (en) * | 2021-11-29 | 2022-04-05 | 苏州浪潮智能科技有限公司 | Large-scale timing method and device based on FPGA |
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| CN101427227A (en) * | 2006-02-03 | 2009-05-06 | L&L工程公司 | Systems and methods for digital control |
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| CN101427227A (en) * | 2006-02-03 | 2009-05-06 | L&L工程公司 | Systems and methods for digital control |
Non-Patent Citations (2)
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| 李亚斌等: ""自采样比例积分控制全数字锁相环的性能分析和实现"", 《中国电机工程学报》 * |
| 王磊等: ""Gardner算法在OFDM采样率同步中的应用"", 《电子与信息学报》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676222A (en) * | 2015-10-30 | 2016-06-15 | 中国人民解放军空军工程大学 | Synthetic aperture radar data adaptive compression and fast reconstruction method |
| CN105676222B (en) * | 2015-10-30 | 2018-09-21 | 中国人民解放军空军工程大学 | A kind of data of synthetic aperture radar self-adapting compressing and method for fast reconstruction |
| CN114280977A (en) * | 2021-11-29 | 2022-04-05 | 苏州浪潮智能科技有限公司 | Large-scale timing method and device based on FPGA |
| CN114280977B (en) * | 2021-11-29 | 2024-02-02 | 苏州浪潮智能科技有限公司 | FPGA-based large-scale timing method and device |
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