CN203166916U - Aggregate burst narrowband-signal continuous-demodulation bit synchronization structure - Google Patents
Aggregate burst narrowband-signal continuous-demodulation bit synchronization structure Download PDFInfo
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- CN203166916U CN203166916U CN 201320043163 CN201320043163U CN203166916U CN 203166916 U CN203166916 U CN 203166916U CN 201320043163 CN201320043163 CN 201320043163 CN 201320043163 U CN201320043163 U CN 201320043163U CN 203166916 U CN203166916 U CN 203166916U
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Abstract
The utility model relates to an aggregate burst narrowband-signal continuous-demodulation bit synchronization structure and belongs to the satellite communication technology field. The synchronization structure comprises an AD chip, a digital shunt circuit, a coupling filter and a bit synchronization processing unit, wherein the bit synchronization processing unit comprises a shunt-data receiving buffering RAM, a bit-timing data buffering RAM, an interpolation filter, a square-filtering timing-error estimation circuit, a bit-timing error estimation value buffering RAM and a bit-timing adjusting control circuit. The structure provided by the utility model is relatively short in synchronous time, independent of carrier wave synchronization, suitable for bit synchronization of aggregate relatively-long burst-frame narrowband signals and provides a perfect solution scheme for an application direction of long burst frames of a modulation and demodulation technique of the spaceborne aggregate narrowband signals.
Description
Technical field
The utility model relates to population road burst narrow band signal continuous solution positioning synchronization structure, belongs to technical field of satellite communication.
Background technology
The bit synchronization structure that is based on filtering interpolation that extensively adopts in the digital demodulation process, mainly formed by two parts, timing error is estimated and timing error is proofreaied and correct, at first adopt a kind of detection algorithm of phase error to estimate timing offset, with the error amount that estimates interpolation filter is controlled, realized the optimum sampling of symbol by the digital interpolation mode.
Whether constitute closed loop according to interpolation filter and Timing Error Detector, digital bit synchronization structure can be divided into two classes: reaction type structure and feed forward type structure.
The bit synchronization of reaction type structure is similar to phase-locked loop (PLL), and the timing information that interpolation filter provides with control module is eliminated the timing error of input signal, and structure as shown in Figure 1.The method for synchronous of typical closed-loop structure is the Gardner algorithm, this algorithm is not need decision-feedback also to need not the blind bit timing recovery algorithm of training sequence, this effective error detection mechanisms cooperates interpolation filtering, can progressively realize error correction and bit synchronization, and be independent of carrier synchronization, all need in the self synchronous digital receiver at clock and carrier wave, the Gardner algorithm has good applicability.
The feed forward type structure does not comprise any feedback circuit, and all signals all flow forward.Based on the bit-synchronization algorithm of this structure, direct estimation goes out timing offset from receive signal, and interpolation goes out optimum sampling point then, and typical feed forward type sign synchronization structure as shown in Figure 2.
Adopt the bit synchronization of reaction type structure that tracking performance is preferably arranged, even under the bigger situation of sampling frequency deviation, preferable performance is arranged still, but capture time is longer, and inevitably there is (hang-up) phenomenon of phase-locked loop intrinsic " outstanding putting ", therefore, be not suitable for the bit synchronization of burst
The bit synchronization of feed forward type structure requires the bit timing estimator can estimate the absolute size of bit clock deviation directly and accurately, rather than estimates its direction that should adjust and trend.Owing to there is not feedback control loop to carry out self adaptation adjustment and tracking, phase jitter is often big than closed-loop structure.
The bit synchronization of feed forward type structure relatively is applicable to burst communication system, in the burst communication system, because burst frame is shorter usually, requires capture time short, and phase jitter can be ignored its influence.
But, when the burst frame duration is longer, with regard to the contraposition synchronization performance very big influence has been arranged based on the shortcoming that phase jitter is big in the bit synchronization of feed forward type structure, the bit synchronization structure that proposes in this patent can well solve the influence that greatly the bit synchronous performance of long burst frame is caused based on the bit synchronous phase jitter of feed forward type structure.
At present, reach the information of recognizing on the open channel from open publication, all do not have special bit synchronous solution at the long burst in group road narrow band signal frame.
The utility model content
The purpose of this utility model is in order to propose population road burst narrow band signal continuous solution positioning synchronization structure.
The purpose of this utility model is achieved through the following technical solutions.
Population road burst narrow band signal continuous solution positioning synchronization structure of the present utility model, as shown in Figure 3, this synchronization structure comprises AD chip, digital demultiplexing circuit, matched filter and bit synchronization processing unit; Wherein, the bit synchronization processing unit comprises that the branch circuit-switched data receives buffer RAM, bit timing is adjusted control circuit with data buffering RAM, interpolation filter, square filtering timing error estimating circuit, bit timing error estimate buffer RAM and bit timing;
Group road narrow band signal is converted to digital signal by the AD chip, carry out digital demultiplexing by the digital demultiplexing circuit afterwards, be divided into n road signal (n 〉=1), every road signal in the signal of n road carries out matched filtering with matched filter to be handled, then this n road signal is carried out the bit synchronization processing in the synchronous processing unit in place respectively, every road signal processing wherein is identical, among Fig. 3, is that example is described this unit with one road signal wherein.
At first, the data of the signal that will handle through filtering write the branch circuit-switched data and receive among the RAM and carry out buffer memory, then from this minute circuit-switched data read data receiving buffer RAM and write bit timing and carry out buffer memory with data buffering RAM, utilize 4 sampled datas of current time, adopt square filtering timing error estimating circuit to obtain the timing error estimated value of current time, and the timing error estimated value that obtains write in the bit timing error estimate buffer RAM carry out buffer memory, simultaneously, the timing error estimated value control interpolation filter that utilizes current time to obtain carries out interpolation filtering, obtains the optimum sampling point of current sign;
Wherein, the digital square filtering timing algorithm of using in the square filtering timing error estimating circuit is a kind of The timing-error estimation that was put forward by M.Oerder and H.Meyr in 1988, this algorithm directly extracts timing error from receive signal, and fast convergence rate, be specially adapted to the bit synchronous realization of digital burst, when adopting digital square filtering timing algorithm, each symbol that receives signal carries out 4 samplings, here, we are made as the timing error value that obtains by digital square filtering timing algorithm
This value be positioned at (π, π) between.
In addition, also need to judge according to the current time in the bit timing error estimate buffer RAM and historical juncture data, adjust control circuit by bit timing and carry out bit timing adjustment work, make that the clock phase of the clock of receiving terminal and transmitting terminal can be synchronous, and simultaneously the timing error estimated value is adjusted accordingly.
It is as follows that bit timing is adjusted the bit timing adjustment Policy description of using in the control circuit:
When the value in the bit timing error estimate buffer RAM during all greater than pi/2, think that receiving end clock and clock originator compared in advance a pi/2 phase place, as shown in Figure 5, then need the receiving end clock is adjusted a pi/2 phase place backward, estimate the bit timing error estimate that obtains as 4 new after the adjustment of receiving end clock sampled points after needing simultaneously the bit timing error amount deducted pi/2;
When the value in the bit timing error estimate buffer RAM during all less than-pi/2, think that the receiving end clock compares the pi/2 phase place that lagged behind with clock originator, as shown in Figure 6, then need the receiving end clock is adjusted a pi/2 phase place forward, need simultaneously the bit timing error amount added behind the pi/2 and estimate as 4 new after the adjustment of receiving end clock sampled points and to obtain the bit timing error estimate;
Other situation, thinking as shown in Figure 7, does not need receiving end clock and clock originator Phase synchronization receiving end clock phase and bit timing error amount are adjusted.
Mainly buffer RAM and bit timing control to realize with the read-write of the data among the data buffering RAM by minute circuit-switched data is received in the adjustment of above-mentioned receiving end clock phase.
Beneficial effect
Structure of the present utility model is that lock in time is shorter, is independent of carrier synchronization, and is applicable to the bit synchronization of the longer burst frame narrow band signal in group road, provides perfect solution for the application direction of the long burst frame of spaceborne group road narrow band signal modulation-demodulation technique.
Description of drawings
Fig. 1 is reaction type interpolation filtering bit synchronization structure;
Fig. 2 is feed forward type interpolation filtering bit synchronization structure;
Fig. 3 is the composition schematic diagram of group of the present utility model road burst narrow band signal continuous solution positioning synchronization structure;
Fig. 4 is the digital demultiplexing circuit structure
Fig. 5 is that the receiving end clock is than the leading pi/2 timing error of clock originator phase place estimated value convergence process;
Fig. 6 is receiving end clock timing error estimated value convergence process during than clock originator phase place hysteresis pi/2;
Timing error estimated value convergence process when Fig. 7 is receiving end end clock and clock originator Phase synchronization;
Fig. 8 receives the buffer RAM structure for dividing circuit-switched data;
Fig. 9 is bit timing buffer RAM structure;
Figure 10 is bit timing error estimate buffer RAM structure.
Embodiment
The utility model is described in further detail below in conjunction with drawings and Examples.
One population road burst narrow band signal continuous solution positioning synchronization structure, as shown in Figure 3, this synchronization structure comprises AD chip, digital demultiplexing circuit, matched filter and bit synchronization processing unit; Wherein, the bit synchronization processing unit comprises that the branch circuit-switched data receives buffer RAM, bit timing is adjusted control circuit with data buffering RAM, interpolation filter, square filtering timing error estimating circuit, bit timing error estimate buffer RAM and bit timing;
5 road FDMA narrow band signal r (t) are converted to digital signal r (kT by the AD chip
s), wherein k=(0,1,2...), T
sThe expression digital sample cycle, carry out digital demultiplexing by the digital demultiplexing circuit afterwards, be divided into 5 tunnel digital signals independently, be respectively r
1(kT
s), r
2(kT
s), r
3(kT
s), r
4(kT
s), r
5(kT
s), wherein the digital demultiplexing circuit adopts Direct Digital to divide path method, namely carries out down-conversion and filtering according to the carrier frequency of every road signal respectively and handles and obtain baseband signal, and structure as shown in Figure 4, again the every roadbed band data after the shunt are carried out matched filtering with matched filter respectively and handle, obtain x
1(kT
s), x
2(kT
s), x
3(kT
s), x
4(kT
s), x
5(kT
s), then, 5 road signals after matched filtering is handled carry out bit synchronization in the synchronous processing unit in place respectively to be handled, and every road signal processing wherein is identical, among Fig. 3, is that example is described this bit synchronization processing unit with the 3 road signal wherein.
At first, the data of the signal that will handle through matched filtering write the branch circuit-switched data and receive in the buffer RAM and carry out buffer memory, from this minute circuit-switched data reception buffer RAM, read 4 sampling numbers then and carry out buffer memory according to writing bit timing with data buffering RAM, utilize 4 sampling number certificates of current time, obtain the timing error estimated value of current time by square filtering timing error estimating circuit
And the timing error estimated value that obtains write in the bit timing error estimate buffer RAM carry out buffer memory, simultaneously, the timing error estimated value of utilizing current time to obtain
Reach bit timing and carry out interpolation filtering with the Data Control interpolation filter among the data buffering RAM, obtain the optimum sampling point of current sign, interpolation filter adopts the filter of heterogeneous structure;
Wherein, the digital square filtering timing algorithm that square filtering timing error estimating circuit adopts is a kind of The timing-error estimation that was put forward by M.Oerder and H.Meyr in 1988, this algorithm directly extracts timing error from receive signal, and fast convergence rate, be specially adapted to the bit synchronous realization of digital burst, when adopting digital square filtering timing algorithm, each symbol that receives signal carries out 4 samplings, here, we are made as the timing error value that obtains by digital square filtering timing algorithm
This value be positioned at (π, π) between.
In addition, also need to judge according to the current time in the bit timing error estimate buffer RAM and historical juncture data, adjust control circuit by bit timing and carry out bit timing adjustment work, make that the clock phase of the clock of receiving terminal and transmitting terminal can be synchronous, and simultaneously the timing error estimated value is adjusted accordingly.
The embodiment that group road burst narrow band signal continuous solution positioning synchronization structure is realized is as follows:
1, the loop buffer RAM that a degree of depth is set is n, circuit-switched data received buffer RAM in namely above-mentioned minute, and the size of n value determines that according to the requirement of system's time delay and the frame length of burst frame, it is 526 that the n value is fixed tentatively here, and structure is as shown in Figure 8.
This minute, circuit-switched data received the 1 tunnel information data of buffer RAM in being used for receiving behind the digital demultiplexing, and every receiving end symbol clock cycle writes the data of 4 sampled points.Initial write address is 0,1,2,3, secondly is 4,5,6,7, and the like, the initial read address is 288,289,290,291, secondly is 292,293,294,295, and the like.
2, will receive the data of reading the buffer RAM from minute circuit-switched data and write the bit timing buffer RAM successively, this buffer RAM degree of depth is 16, as shown in Figure 9.
Write address is respectively 12,13, and 14,15, every receiving symbol clock writes 4 data, before writing, with 4 addresses of legacy data right shift successively, the data in the address 3 is preserved, this is worth in the bit timing adjustment in the back and needs to use, and abandons the data in the address 0,1,2.
After writing data, 4 sampled points that newly write are tried to achieve the timing error estimated value by square filtering timing error estimating circuit, select interpolation filter according to resulting timing error estimated value afterwards, go out the optimum sampling point of current sign with 16 common interpolations of sampled point.
Simultaneously, the timing error estimated value that at every turn obtains be carried out buffer memory, the buffer memory RAM degree of depth of Cai Yonging is made as 6 here, structure as shown in figure 10:
When adjusting, bit timing need use 6 bit timing error estimates keeping among this RAMz.
3, carry out the bit timing adjustment according to the size of bit timing error estimate, adjustment process is as follows:
The bit timing error estimate of 6 symbols of current preservation is during all greater than pi/2, a pi/2 phase place that the receiving end symbol clock of this moment and the symbol clock of making a start are leading, therefore the phase place of receiving end symbol clock need be adjusted a pi/2 phase place backward, be equivalent to adjust backward 1 sampled point, then bit timing shown in Figure 9 is that 4～14 data are to moving to left 1 with address in the buffer RAM, the address is 4 data by the address of keeping in advance is that 3 data are filled, next symbol clock branch circuit-switched data receive buffer RAM sampled point read the address successively clockwise direction (left) adjust 1, illustrate, if the address of reading of next symbol clock sampled point is respectively 288 before not adjusting, 289,290,291, the address of reading after adjusting so then is 287,288,289,290.Like this, receiving end symbol clock just with make a start the symbol clock again synchronously on.
In addition because present phase error estimation and phase error value is known, the net synchronization capability that convergence process when calculating the phase error estimation and phase error value later on for fear of the adjustment of receiving end symbol clock causes descends, need simultaneously the phase error estimation and phase error value is adjusted accordingly, the phase error estimation and phase error value of this moment deducts pi/2 and is current time phase error estimation and phase error value.
The bit timing error estimate of 6 symbols of current preservation is during all less than-pi/2, the receiving end symbol clock of this moment is compared the pi/2 phase place that lagged behind with the symbol clock of making a start, therefore the phase place of receiving end symbol clock need be adjusted a pi/2 phase place forward, be equivalent to adjust forward 1 sampled point, bit timing then shown in Figure 9 moves right 1 with the data in the address in the buffer RAM 5～15, data in the 15th address are replaced by the number that the address adds in 1 the address of reading that the current minute circuit-switched data of preserving receives last 1 sampled point in the buffer RAM, next symbol clock branch circuit-switched data receive sampled point in the buffer RAM read the address successively counterclockwise (to the right) adjust 1.
The net synchronization capability that convergence process when calculating the phase error estimation and phase error value later on for fear of the adjustment of receiving end symbol clock equally causes descends, need simultaneously the phase error estimation and phase error value is adjusted accordingly, the phase error estimation and phase error value of this moment adds pi/2 and is current time phase error estimation and phase error value.
Other situation does not then adjust.
Based on the realization of bit synchronization structure described above, can well solve group bit synchronization problem of the long-term burst frame signal in arrowband, road.
Claims (2)
1. population road burst narrow band signal continuous solution positioning synchronization structure, it is characterized in that: this synchronization structure comprises AD chip, digital demultiplexing circuit, matched filter and bit synchronization processing unit;
Group road narrow band signal is converted to digital signal by the AD chip, carry out digital demultiplexing by the digital demultiplexing circuit afterwards, be divided into n road signal, n ≧ 1, every road signal in the signal of n road carries out matched filtering with matched filter to be handled, then this n road signal is carried out the bit synchronization processing in the synchronous processing unit in place respectively, every road signal processing wherein is identical.
2. a population road according to claim 1 burst narrow band signal continuous solution positioning synchronization structure, it is characterized in that: the bit synchronization processing unit comprises that the branch circuit-switched data receives buffer RAM, bit timing is adjusted control circuit with data buffering RAM, interpolation filter, square filtering timing error estimating circuit, bit timing error estimate buffer RAM and bit timing;
The data of the signal that process filtering is handled write among the branch circuit-switched data reception RAM carries out buffer memory, then from this minute circuit-switched data read data receiving buffer RAM and write bit timing and carry out buffer memory with data buffering RAM, utilize 4 sampled datas of current time, adopt square filtering timing error estimating circuit to obtain the timing error estimated value of current time, and the timing error estimated value that obtains write in the bit timing error estimate buffer RAM carry out buffer memory, simultaneously, the timing error estimated value control interpolation filter that utilizes current time to obtain carries out interpolation filtering, obtains the optimum sampling point of current sign.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842481A (en) * | 2017-11-24 | 2019-06-04 | 成都鼎桥通信技术有限公司 | Receive signal synchronizing method and receiving device |
| CN110401609A (en) * | 2018-11-07 | 2019-11-01 | 西安电子科技大学 | It is a kind of to accelerate convergent Gardner symbol timing recovery method and apparatus |
| CN110830229A (en) * | 2019-09-27 | 2020-02-21 | 中国电子科技集团公司第二十九研究所 | Multi-carrier symbol synchronization method facing MF-TDMA |
-
2013
- 2013-01-25 CN CN 201320043163 patent/CN203166916U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109842481A (en) * | 2017-11-24 | 2019-06-04 | 成都鼎桥通信技术有限公司 | Receive signal synchronizing method and receiving device |
| CN109842481B (en) * | 2017-11-24 | 2022-02-18 | 成都鼎桥通信技术有限公司 | Received signal synchronization method and receiving device |
| CN110401609A (en) * | 2018-11-07 | 2019-11-01 | 西安电子科技大学 | It is a kind of to accelerate convergent Gardner symbol timing recovery method and apparatus |
| CN110830229A (en) * | 2019-09-27 | 2020-02-21 | 中国电子科技集团公司第二十九研究所 | Multi-carrier symbol synchronization method facing MF-TDMA |
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