CN101427227A - Systems and methods for digital control - Google Patents
Systems and methods for digital control Download PDFInfo
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- CN101427227A CN101427227A CNA2006800534356A CN200680053435A CN101427227A CN 101427227 A CN101427227 A CN 101427227A CN A2006800534356 A CNA2006800534356 A CN A2006800534356A CN 200680053435 A CN200680053435 A CN 200680053435A CN 101427227 A CN101427227 A CN 101427227A
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Abstract
Methods and systems for digital control utilizing oversampling.
Description
Background technology
The Applied Digital method can produce new feature, improves performance, reach the higher adaptation of product and lower cost in system's control.Come the system operation feature of appointment can save cost and space and can also produce the real-time adaptability of above-mentioned feature, the more high precision of control algolithm and the ability of the valuable real-time function type data of generation, storage and memory by program stored rather than by the parameter of a cover discrete component.
Yet digital feedback control requires high resolving power and high-speed.These require to have limited numerically controlled employing in a lot of fields.The appearance of low-cost logic makes the field that digital control technology is applied to cost sensitivity become possibility.Along with the cost attenuating of Digital Logic, new chance has occurred.
Typical digital control feedback system has analog to digital converter, digital loop compensator, electric device driver and controlled external system.The example that Applied Digital is controlled the system that can improve performance or reduce cost is Switching Power Supply or DC-DC converter.Yet (, many other systems also will be benefited from numerically controlled application.)
For low power applications, for example be used for for example rechargeable battery and the electric battery of the portable consumer of entertainment device, personal digital assistant and mobile phone, active demand reduces cost, size and the power consumption of low-cost off-line switching power supply.
The pulse-width modulation type Switching Power Supply needs turnable pulse width, and this turnable pulse width is by controlling with the error signal that accurate reference voltage obtains by comparing actual output voltage.The pulsewidth of switch gap also must be limited within the minimum and maximum duration.Applying these limits and proofreaies and correct the operation of pulse-width modulation type power supply or motor driver.
An example of digital control system as shown in Figure 1.In the example depicted in fig. 1, system is simple decompression DC-DC converter.For any DC-DC converter, base components all is identical.Example system shown in Figure 1 comprises three main elements: A-D converter (ADC) compensator, pulse width modulator and power switch and Passive LC net before.
Typically, width modulation resolution requirement is high more a lot of than A-D converter resolution.Talk about if not so, the encoded radio of the output of width modulation must be beated repeatedly to satisfy concrete input adc code.Usually the frequency of beating repeatedly that is considered to the limit cycle is dynamically determined by control system.The frequency and the size of result's pulsation may be strengthened.Typical solution to this problem is to increase width modulation resolution.This method can cause obviously complicated in the width modulation design.May need the technology of multi-phase clock for example or analogy method in order to reach required resolution.This point is particularly correct for the high-speed power of the pulse width modulation frequency that requires hypervelocity.
Need to satisfy the digitial controller of high resolving power and high speed requirement.
The digitial controller that also needs great computing just can carry out.
Further need have above-mentioned feature and can have the digitial controller of any control coefrficient.
Simple, the cost effective method of the width modulation resolution that also needs to provide quite high and system.
Summary of the invention
In one embodiment, the digitial controller of the present invention's instruction comprises modulator element, the compensating filter that can receive oversampled signals, the output that can receive compensating filter that can receive simulating signal and oversampled signals is provided and the low-pass filter of low-pass filter output can be provided and can receive the sub sampling element that low-pass filter output also can provide sub sampling output that this sub sampling output has the sub sampling rate lower than the speed of oversampled signals.
In another embodiment, the digitial controller of the present invention instruction comprises and can receive the input signal with resolution input time and the dither generating device that has than the dither output signal of the lower temporal resolution of resolution input time can be provided; The mean value of dither output signal equals input signal in fact, can receive the digital pulse-width modulator that the dither output signal also can provide a plurality of gating pulse; The dither output signal is determined at least one feature of gating pulse.
Other embodiment are also in the protection domain of the present invention's instruction.
The embodiment of this method is also in the protection domain of the present invention instruction and be disclosed.
In order to understand the present invention and other and further needs better, please refer to accompanying drawing and detailed explanation, protection scope of the present invention will be pointed out in the claims.
Description of drawings
Fig. 1 represents traditional single-phase step down voltage redulator;
Fig. 2 represents to represent the block scheme of an embodiment of the digitial controller that comprises over-sampling A-D converter and compensating filter;
Fig. 3 represents to represent the block scheme of an embodiment of the digitial controller that the present invention instructs;
Fig. 4 represents to represent the block scheme of a specific embodiment of the digitial controller that the present invention instructs;
Fig. 5 represents to represent the block scheme of another specific embodiment of the digitial controller that the present invention instructs;
Fig. 6 represents to represent the block scheme of another embodiment of the digitial controller that the present invention instructs;
Fig. 7 represents to represent the block scheme of traditional second order es-Delta modulator;
Fig. 8 represents to represent the block scheme of an embodiment of the element of the digitial controller that the present invention instructs;
Fig. 9 represents to represent the block scheme of another embodiment of the element of the digitial controller that the present invention instructs;
Figure 10 represents to represent the block scheme of another embodiment of the element of the digitial controller that the present invention instructs;
Figure 11 represents to represent the block scheme of another embodiment of the digitial controller that the present invention instructs;
Figure 12 represents to represent the block scheme of another embodiment of the digitial controller that the present invention instructs;
Figure 13 a and 13b represent to represent the synoptic diagram of the simulation result of the embodiment that the present invention instructs;
Figure 14 represents to represent the block scheme that is used for from an embodiment of the system that the present invention of digital power managent component collection real-time performance data instructs;
Figure 15 represents to represent the block scheme of the element of embodiment shown in Figure 14;
Figure 16 represents to represent the block scheme of an embodiment of the element of system shown in Figure 14;
Figure 17 represents to represent and utilizes embodiment shown in Figure 16 to carry out the timing synoptic diagram of data transmission;
Figure 18 represents to represent the block scheme of another embodiment of the element of the digitial controller that the present invention instructs; And
Figure 19 represents to represent the synoptic diagram of the simulation result of the embodiment among Figure 18.
Embodiment
Although these instructions of the present invention are described as the specific embodiments that is used for controlled system, many digital control system also can use the digitial controller of the one side that the present invention instructs-the present invention's instruction, and any variable duration impulse system second aspect-width modulation dither system that can use the present invention to instruct.
Although should be noted that the exemplary power embodiment of the present invention's instruction is described by a kind of exemplary types, other electric source structures, for example booster type, buck-boost type, positive activation type, inverse-excitation type etc. are also all in the scope of the present invention's instruction.
Fig. 1 represents an example of traditional digital control system.In this example, system is simple buck DC to dc converter.Base components is identical for any DC-DC converter.Conventional digital control system 10 among Fig. 1 comprises: the feedback compensator 15, pulse width modulator 20, power switch 25 and the Passive LC net 30 that comprise A-D converter and compensating filter.
Fig. 2 represents to represent the block scheme of an embodiment of digitial controller, and wherein the feedback compensator among Fig. 1 15 comprises over-sampling A-D converter 35 and compensating filter 55.Over-sampling A-D converter 35 comprises modulator element 40, reception over-sampling (low resolution, the High Data Rate) signal that receives simulating signal and over-sampling (low resolution, High Data Rate) signal is provided and the low-pass filter 45 of low-pass filter output is provided and receives the sub sampling element 50 that sub sampling output (high resolving power, low data rate) was exported and provided to low-pass filter that the speed that this sub sampling is exported is lower than the speed of oversampled signals.This sub sampling output is provided for compensator 55 (compensating filter).The embodiment of the compensator 55 shown in Fig. 2 comprises first wave filter 60, and the molecule that it comprises compensating filter 55 is expressed as the Z conversion N (Z-1) and second wave filter 65, and the denominator that it comprises compensating filter 55 is expressed as Z conversion D (Z-1).The output of compensating filter 55 is provided for the pulse width modulator 70 that a plurality of gating pulse are provided.
Fig. 3 represents to represent the block scheme of an embodiment of the digitial controller that the present invention instructs.In the embodiment shown in fig. 3, receive simulating signal and, be expressed as the Z conversion of high sampling rate for first compensating filter 75 provides the modulator element 40 of over-sampling (low resolution, High Data Rate) signal.The output of first compensating filter 75 is provided for low-pass filter 80.The output of low-pass filter 80 is provided for subsampler 85, and this subsampler 85 provides sub sampling output (high resolving power, low data rate).Sub sampling output is provided for second compensating filter 90, is expressed as the Z conversion of low sampling rate.Compensating signal (output of second compensating filter 90) is provided for pulse width modulator (PWM) 70.By rearrangement makes first compensating filter 75 among Fig. 3 comprise the molecule of the compensating filter 55 among Fig. 2 to the compensating filter among Fig. 2 55, by first compensating filter 75 is placed between modulator 40 and the low-pass filter 80, make compensator enjoy the low bit stream width data of over-sampling.As a result, logic complexity is lower, but logical timer speed is higher and can obtain to reduce the embodiment that uses multiplier.
In an example, low pass 80 and subsampler 85 can be in conjunction with forming low pass/decimation filter.In one embodiment, low pass 80 or subsampler 85 or low pass/decimation filter can be included in the comb filter that is essentially null value on pulse width modulation frequency and the harmonic wave thereof.
Should be noted that all embodiment that only uses first compensating filter 75 as shown in Figure 3 also fall in the scope of the present invention's instruction.Be to be further noted that the embodiment that compensation output is provided for control device rather than pulse width modulator also falls in the protection domain of the present invention's instruction.
In the operating process of the embodiment of Fig. 3, the signal of coming in is an over-sampling, causes the signal of low resolution high data rate.This oversampled signals is compensated by compensating filter, and the oversampled signals through compensating is low pass filtering and sub sampling, causes high resolving power low data rate signal.In one embodiment, high resolution low data rate compensated signal is used as input and offers pulse width modulator.In another embodiment, high resolution low data rate compensated signal is further compensated, and in variable duration impulse system, the low data rate signal that is further compensated is provided for pulse width modulator.
Fig. 4 represents an embodiment of the system that the present invention instructs, and this embodiment implements with the compensator that is equal to traditional PID compensator but enjoys the advantage that the present invention's instruction provides.In the embodiment shown in fig. 4, first compensating filter 105 is corresponding to the molecule of traditional PID compensator, and second compensating filter 110 comprises the discrete integrator and the digitial controller of the present invention's instruction, corresponding to traditional PID compensator.
Fig. 5 represents an embodiment of the system that the present invention instructs, wherein only use first compensating filter 115 and first compensating filter 115 to comprise a plurality of subfilters 120, the output of each subfilter 120 is multiplied by the weight 125 from a plurality of weights, and the output of compensating filter 115 is summations of weighting output.
Fig. 6 represents an embodiment of the system that the present invention instructs, and wherein first compensating filter comprises two subfilters 130,135.First subfilter 130 comprises the molecule of the compensating filter 55 among Fig. 2.Second subfilter 135 can comprise the denominator of the compensating filter 55 among Fig. 2 in one embodiment, can include only the high frequency utmost point of the denominator of the compensating filter 55 among Fig. 2 in another embodiment.In a second embodiment, second compensating filter can comprise the low-frequency pole of the denominator of the compensating filter 55 among Fig. 2.
In one embodiment, the modulator among Fig. 3 40 is sigma-delta modulators 140.Shown in Fig. 7 is traditional second order sigma-delta modulator.Should be noted that the single order sigma-delta modulator also can be used as the modulator 40 among Fig. 3.
In another embodiment as shown in Figure 8, modulator 40 among Fig. 3 comprises sampling and the holding element 145 that receives simulating signal, repeat ramp generator 150, the output of sampling and holding element 145 will deduct the output of repetition ramp generator 150, and the comparer 155 of the difference of the output of the output of reception sampling and holding element 145 and repetition ramp generator 150.In one embodiment, repeat ramp generator 150 and comprise voltage-controlled oscillator (VCO), it can be the voltage-controlled oscillator that can reset.In such an embodiment, modulator 40 comprises the replacement element that modulator can be refitted in low resolution.
In another embodiment shown in Figure 9, the modulator 40 among Fig. 3 comprises high-speed figure control analogue loop.As shown in Figure 9, modulator 40 among Fig. 3 comprises the analog to digital conversion element 160 of low resolution, the output of low resolution analog to digital conversion element 160 is oversampled signals, discrete integrator 165 receives the output of low resolution analog to digital conversion element 160, high resolving power digital to analog conversion element 170 receives the output of discrete integrator 165, and the input of low resolution analog to digital conversion element 160 is the difference of importing between the output of simulating signal and high resolving power digital to analog conversion element 170.The sampling rate of high-speed figure control analogue loop is selected as being enough to allowing input tracked.In the embodiment shown in fig. 9, discrete integrator 175 comprises low-pass filter and compensating filter.
In another embodiment shown in Figure 10, adjustable gain element 177 receives the output of low resolution analog to digital conversion element 160, and the output of adjustable gain element 177 is oversampled signals.Discrete integrator 165 receives the output of adjustable gain element 175.In the operational process of embodiment shown in Figure 10, cycle of pulse width modulator begin to locate to utilize high in fact gain, and reduce in the gain of the end in pulse width modulator cycle.
Should be noted that, in the embodiment shown in fig. 10, when discrete integrator 175 and subsampler comprise low-pass filter/withdrawal device, when constituting an A-D converter, the sampling delay of quick clock still is provided, wherein this A-D converter allows the Fast transforms of input signal, promptly with the iterative approximation method conversion of the speed of (～X2 slows down), but the input of change at a slow speed that also allows not have sampling and keep.
Figure 11 represents another embodiment of the digitial controller that the present invention instructs.Embodiment shown in Figure 11 comprises can receiving inputted signal and can provide and have than the dither generating device 180 of the dither output signal of the lower temporal resolution of resolution input time and can receive the digital pulse-width modulator 70 of dither output signal, and this dither output signal is determined at least one feature of gating pulse.In the embodiment shown in fig. 11, dither generating device 180 comprises digital quantizer 195 elements that produce the dither output signal, receives the dither output signal and the dither output delay of output signal element 190 (delay element 190 is represented with the form of the Z conversion that postpones) of delay is provided and receives the difference between the dither output signal of sub-sampled signals and delay and be the discrete integrator element 185 that digital quantizer 195 provides discrete integrator output.
Figure 12 represents to represent the block scheme of another embodiment of the digitial controller that the present invention instructs.In the embodiment shown in fig. 12, dither generating device 180 comprises digital quantizer 195 elements that produce the dither output signal, receive the dither output signal and the dither output delay of output signal element 190 (delay element 190 is represented with the form of the Z conversion that postpones) of delay is provided, can receive the difference between the dither output signal of sub-sampled signals and delay and the first discrete integrator element 205 of first discrete integrator output can be provided and can receive the output of first discrete integrator and the dither output signal that postpones between difference and second discrete integrator 215 of second discrete integrator output can be provided for digital quantizer 195.
Should be noted that although single order dither system is shown among Figure 11, second order dither system is shown among Figure 12, the present invention's instruction is not limited only to these embodiment, and the embodiment of high-order dither system is also in the protection domain of the present invention's instruction.Carry out among the embodiment of loop element in digital hardware, component value comes down to accurately, and the output of modulator comes down to stable.
In the operational process of Figure 11 or embodiment shown in Figure 12, digital quantizer 195 is removed least significant bit (LSB) from input data path (sub-sampled signals).Feedback control loop (feeding back to the loop of the difference between digital quantizer output that delay is provided and the sub-sampled signals of importing from the output of digital quantizer 195) provides the average output that equals the full resolution input signal.Since shown in the pole location of feedback control loop, the limit cycle very high speed.
Figure 13 a and 13b represent the simulation result of the embodiment of the present invention's instruction shown in Figure 12.Figure 13 a represents to comprise the simulation result of the closed-loop control buck converter system of the dither generating device among Figure 12.Figure 13 b represents not comprise the result of the closed loop controlled buck converter system of the dither generating device 180 among Figure 12.7 pulse width modulators in two embodiment, have all been used.If the dither generating device is not included in the system, the result who obtains among Figure 13 a will need 10 pulse width modulators.
Should be noted that the embodiment that is combined with the present invention's instruction of dither generating device in Figure 11 or 12 and the digitial controller among Fig. 3 to 10 is in the scope of the present invention.
Figure 14 represents to represent that the present invention instructs is used for collecting from the digital power managent component block scheme of an embodiment of the system of real-time performance data. embodiment shown in Figure 14 comprises the serial data transfer component that can receive/send from/a plurality of positions to the digital power managent component 225 real time data, comprises the controller component 230 of (as shown in figure 15) one or more processors 235 and have the computer available media 240 that is embodied as computer-readable code at this that this computer-readable code can impel one or more processors at least one position from the digital power managent component in digital power managent component running to collect real time data and/or at least one other position in the digital power managent component provide real time data. (in one embodiment, one or more processors 235 and computing machine available media 240 are operably connected by Connection Element 237.This Connection Element 237 can be for example computer bus or carrier wave.)
In the operational process of embodiment shown in Figure 14, in that provide can be after the serial data transfer component 220 of/a plurality of position reception/transmission real time datas to digital power managent component 225, collect from the real time data of at least one position of digital power managent component and provide it to controller component 230.In another embodiment, real time data is provided at least one position in the digital power managent component 225.
In an embodiment shown in Figure 16, serial data transfer component 220 comprises the parallel shift register 242 that is written into, is responsible for being written into and carrying out the status switch generator 245 of data to shift register.Serial data transfer component 220 comprise clock terminal (serial time clock line, SCL) and data terminal (serial data line, SDA).In the operational process of embodiment shown in Figure 16, reception/transmitting element 230 and serial data transfer component 220 synchronously and interface be point-to-point.In the embodiment shown in Figure 16, this is to reach as the clock synchronization source of reception/transmitting element 230 by the pin that utilizes serial time clock line.Operation by serial time clock line by high level to low transition and serial data line to be high level start (opposite with traditional I2C interface start).The internal reference clock of selecting serial time clock line rather than reception/transmitting element 230 is as serial port clock source.Transmission comprises 16 order of the bit words of desired data layout, especially by the field of reception/transmitting element 230 transmissions and the field that is received by reception/transmitting element 230.After finishing, the serial port of reception/transmitting element 230 receives its first data field, changes the direction of bus and sends its first data field.This will last till and take place till the hardware reset, and Figure 17 represents timing (the present invention's instruction is not limited thereto embodiment) that an exemplary operation is carried out.
In another embodiment of operation shown in Figure 16, in traditional I2C interface modes, initial state by serial data line by high level to low transition and serial time clock line is a high level shows.Traditional I2C interface protocol is handled for residue and is carried out, this residue processing comprise serial data line by low level to the high level saltus step and serial time clock line is the halted state of high level.The open collector that the three-state output of serial data wire pin is used to define in the emulation conventional I 2C interface specification is failed.Senior serial port modes is selected as having the sequence of traditional I2C interface command.
In another embodiment of operation shown in Figure 16, in the monofilar mode based on the I2C data layout, the digital coding of making zero is used to eliminate the demand (being equivalent to utilize internal clocking as the reference clock) to clock recovery.This operational mode is inclined to the product that is used for pins limits but requires simple internal to adjust.The status switch generator module comprises return-to-zero coding device/demoder, and is the combination selection in the silicon.This is designed to can drive high or low real cmos driver with regard to one, and this will cause higher data transfer rate.
Figure 18 represents to represent the block scheme of further embodiment of the element of the digitial controller that the present invention instructs.Embodiment shown in Figure 16 comprises the compensating filter element 250 of the digital signal that can receive digital input signals and can afford redress, and this compensating filter element 250 has at least one adjustable parameter; Can receive digital input signals also can provide the error performance wave filter 255 of performance indicator signal; With can the receptivity indicator signal and the disturbance generating device 260 of one or more adjustable parameter values can be provided to compensating filter element 250.In one embodiment, the value that is provided only is in fact to the little adjustment of known value (for example value formerly).In one embodiment, error performance wave filter 255 is the wave filters that obtain the variance absolute value.In another embodiment, error performance wave filter 255 is the wave filters that produce the indication power loss signal.Should be noted that the present invention's instruction is not limited to the embodiment of above-mentioned disclosed error performance wave filter 255.In another embodiment, the value that is provided utilizes random perturbation to obtain.In another embodiment, the value that is provided obtains by pre-defined algorithm (for example gradient search algorithm, but be not limited thereto).
In the embodiment shown in Figure 18, system also comprises the pulse width modulator 270 with at least one adjustable parameter.Pulse width modulator 270 receives the value of one or more adjustable parameters of disturbance generating device 260.System shown in Figure 18 also comprises A-D converter 275.Figure 19 represents to represent the synoptic diagram of the simulation result of the embodiment among Figure 18.
Should be noted that the pulse width modulator in the foregoing description can comprise, but be not limited to by Syed, A.Ahmed, E., Maksimovic, D., Alarcon, E. be published in that " PESC 04,2004 IEEE 35thAnnual Power Electronics Specialists Conference " the 6th volume 4689-4695 page or leaf of 20-25 day in June, 2004 in " Digital pulse width modulator architectures " literary composition and O ' Malley, E., Rinne, K. be published in the pulse width modulator described in " the programmable digital pulse width modulator providing versatilepulse patterns and supporting switching frequencies beyond 15 MHz " literary composition in the 1st volume 53-59 page or leaf in " APEC ' 04, Nineteenth Annual IEEEApplied Power Electronics Conference and Exposition " 2004.These two pieces of documents are this combined quoting, and list in list of references.The foregoing description can be implemented with traditional digital element (or the traditional numeral " unit " in comprehensive embodiment) and traditional A-D converter and digital-to-analog converter (DAC), but is not limited thereto.
Although the foregoing description is illustrated in the mode of special controlled member, should be noted that the foregoing description also can be applicable to more other controlled members of wide region.
The common form of computer-readable (computing machine can with) media comprises: for example disk, floppy disk, hard disk, tape or any other magnetic media; Any other optical medium such as CD-ROM; Any other has the hole or the physical media of other patterns card punch, paper tape etc.; Random access memory, programmable read-only memory, can eliminate any other memory chips such as programmable read only memory, nonvolatile memory; Or magnetic tape cassette, carrier wave, for example be electromagnetic radiation or electric signal or any other computer-readable media.
Although the present invention is described at various embodiment, should be appreciated that the present invention can also have wide in range further and other embodiment be included in the thought and scope of appended claim.
Claims (50)
1. digitial controller comprises:
Can receive simulating signal and the modulator element of oversampled signals is provided;
Can receive the compensating filter of oversampled signals;
The output and can providing that can receive described compensating filter has the amplitude that reduces in fact and greater than the low-pass filter of the low-pass filter output of the frequency of preset frequency; And
The sub sampling element that can receive low-pass filter output and can provide sub sampling to export, this sub sampling output has the sub sampling rate that is lower than the oversampled signals rate.
2. digitial controller according to claim 1 is characterized in that also comprising:
Can receive sub sampling output also can provide another compensating filter of the compensator output of sub sampling rate;
The wave filter that is equal to described compensating filter in fact, another compensating filter of described sub sampling rate is the compensating filter of being scheduled to.
3. digitial controller according to claim 2 is characterized in that also comprising:
The compensator output that can receive the sub sampling rate also can provide the digital pulse-width modulator of a plurality of pulse gating pulse.
4. digitial controller according to claim 2 is characterized in that described compensating filter obtains from the molecule of predetermined compensating filter.
5. digitial controller according to claim 4 is characterized in that described another compensating filter comes down to discrete integrator; And described predetermined backoff wave filter comes down to the PID compensating filter.
6. digitial controller according to claim 1 is characterized in that also comprising:
The compensator output that can receive the sub sampling rate also can provide the digital pulse-width modulator of a plurality of pulse gating pulse.
7. controller according to claim 1 is characterized in that described compensating filter comprises:
A plurality of subfilters; A value in a plurality of values is multiply by in each output of each subfilter of described a plurality of subfilters, and it is a weighting output in a plurality of weightings outputs that each output of each subfilter be multiply by after the described value; And
The output of described compensating filter is the summation of described a plurality of weighting outputs.
8. digitial controller according to claim 1 is characterized in that described modulator element is a sigma-delta modulator.
9. digitial controller according to claim 1 is characterized in that described modulator element comprises:
Receive the sampling and the holding element of simulating signal;
Repeat ramp generator; The output of described sampling and holding element will deduct the output of described repetition ramp generator; And
The output that receives described sampling and holding element deducts the output gained result's of described repetition ramp generator the comparer of signal;
The output of described comparer is described oversampled signals.
10. digitial controller according to claim 9 is characterized in that described repetition ramp generator comprises voltage-controlled oscillator.
11. digitial controller according to claim 10 is characterized in that described voltage-controlled oscillator is the oscillator that can reset.
12. digitial controller according to claim 9 is characterized in that described modulator element comprises the replacement element that described modulator element can be refitted in low resolution.
13. digitial controller according to claim 1 is characterized in that described modulator element comprises:
Low resolution analog to digital conversion element; The output of described low resolution analog to digital conversion element is oversampled signals;
Receive the discrete integrator of this oversampled signals; And
High resolving power digital to analog conversion element; Described high resolving power digital to analog conversion system receives the output of described discrete integrator;
Described low resolution analog to digital conversion element received signal, this signal comprise the difference between the output of simulating signal and described high resolving power digital to analog conversion element.
14. digitial controller according to claim 13 is characterized in that described compensating filter and described low-pass filter comprise discrete integrator.
15. digitial controller according to claim 1 is characterized in that described modulator element comprises:
Low resolution analog to digital conversion element;
The adjustable gain element that can receive the output of described low resolution analog to digital conversion element and can provide the adjustable gain element to export, the output of this adjustable gain element equals the output that adjustable multiplication factor multiply by described low resolution analog to digital conversion element in fact;
Described adjustable gain element can also the receiving gain setting signal and can be responded described gain setting signal and change described adjustable multiplication factor; Described adjustable gain element output is oversampled signals;
Receive the discrete integrator of this adjustable gain element output; And
High resolving power digital to analog conversion system; Described high resolving power digital to analog conversion system receives the output of described discrete integrator;
Described low resolution analog to digital conversion system received signal, this signal comprise the difference between the output of simulating signal and described high resolving power digital to analog conversion system.
16. digitial controller according to claim 15 is characterized in that described compensating filter and described low-pass filter comprise discrete integrator.
17. a controller comprises:
Can receive input signal and the dither generating device that has than the dither output signal of the lower temporal resolution of resolution input time can be provided with resolution input time; The mean value of dither output signal equals input signal in fact; And
Can receive the dither output signal also can provide the digital pulse-width modulator of a plurality of pulse gating pulse; Described dither output signal is determined at least one feature of described a plurality of pulse gating pulse.
18. controller according to claim 17 is characterized in that described dither generating device comprises:
Can produce the digital quantizer element of dither output signal;
Can receive the dither output signal also can provide the dither output delay of output signal element of delay; And
Can receiving inputted signal and the dither output signal of delay between difference and the discrete integrator element of discrete integrator output can also be provided to described digital quantizer.
19. controller according to claim 17 is characterized in that described dither generating device comprises:
Can produce the digital quantizer element of dither output signal;
Can receive the dither output signal also can provide the dither output delay of output signal element of delay; And
Can receiving inputted signal and the dither output signal of delay between difference and the first discrete integrator element of first discrete integrator output can also be provided; And
Difference between the dither output signal that can receive the output of first discrete integrator and postpone also can also provide second discrete integrator of second discrete integrator output to described digital quantizer.
20. digitial controller according to claim 1 is characterized in that also comprising:
Can receive sub-sampled signals also can provide the dither generating device of the dither output signal with temporal resolution lower than sub-sampled signals resolution; There is the mean value of dither output signal to equal sub-sampled signals in fact; And
Can receive the dither output signal also can provide the digital pulse-width modulator of a plurality of pulse gating pulse; Described dither output signal is determined at least one feature of described a plurality of pulse gating pulse.
21. controller according to claim 20 is characterized in that described dither generating device comprises:
Can produce the digital quantizer element of dither output signal;
Can receive the dither output signal also can provide the dither output delay of output signal element of delay; And
Can receive the difference between the dither output signal of sub-sampled signals and delay and the discrete integrator element of discrete integrator output can also be provided to described digital quantizer.
22. controller according to claim 20 is characterized in that described dither generating device comprises:
Can produce the digital quantizer element of dither output signal;
Can receive the dither output signal also can provide the dither output delay of output signal element of delay; And
Can receive the difference between the dither output signal of sub-sampled signals and delay and the first discrete integrator element of first discrete integrator output can also be provided; And
Difference between the dither output signal that can receive the output of first discrete integrator and postpone also can also provide second discrete integrator of second discrete integrator output to described digital quantizer.
23. a controller comprises:
The compensating filter element of the digital signal that can receive digital input signals and can afford redress; Described compensating filter element comprises at least one predetermined parameters;
Can receive digital input signals also can provide the error performance wave filter of performance indicator signal; And
Can the receptivity indicator signal and the disturbance generating device of described at least one preset parameter value can be provided to described compensating filter element;
Difference between the preceding value of described value and described at least one preset parameter is littler than described preceding value in fact.
24. controller according to claim 23 is characterized in that also comprising:
Can receive analog input signal also can provide the analog to digital conversion element of digital input signals.
25. according to the controller of claim 23, it is characterized in that described error performance wave filter comprises the wave filter that the performance indicator signal is provided, described performance indicator signal is the indication of variance absolute value.
26. controller according to claim 23 is characterized in that described error performance wave filter comprises the wave filter that the performance indicator signal is provided, described performance indicator signal is the indication of power consumption.
27. controller according to claim 23 is characterized in that also comprising:
The digital signal that can receive compensation also can provide the digital pulse-width modulator of a plurality of pulse gating pulse.
28. controller according to claim 27 is characterized in that described digital pulse-width modulator comprises at least one width modulation preset parameter; Wherein, described disturbance generating device can provide the value of described at least one width modulation preset parameter to described digital pulse-width modulator.
29. controller according to claim 23 is characterized in that described disturbance generating device utilizes random perturbation to produce described value.
30. controller according to claim 23 is characterized in that described disturbance generating device utilizes pre-defined algorithm to produce described value.
31. controller according to claim 30 is characterized in that described pre-defined algorithm is a gradient search algorithm.
32. controller according to claim 23 is characterized in that also comprising the error injection element that can add error signal to the digital signal of compensation.
33. the method from digital power managent component collection real-time performance data, this method comprises the following step:
Provide can from/to the serial data transfer component of a plurality of position reception/transmission real time datas of digital power managent component;
In the operational process of digital power managent component, real time data is collected at least one position from a plurality of positions of digital power managent component; And
The real time data of collecting from least one position is provided to controller component.
34. method according to claim 33 is characterized in that providing the step of real time data to include and utilizes serial data transfer component clock source to make controller component and the synchronous step of serial data transfer component as the reference clock.
35. method according to claim 33 is characterized in that also including step:
Provide real time data by controller component at least one other position in a plurality of positions of digital power managent component.
36. method according to claim 35 is characterized in that providing the step of real time data to include and utilizes serial data transfer component clock source to make controller component and the synchronous step of serial data transfer component as the reference clock.
37. the system from digital power managent component collection real-time performance data, this system comprises:
Can from/to the serial data transfer component of a plurality of position reception/transmission real time datas of digital power managent component; And
Be operably connected to the controller component in the described territory of data transmission element, described controller comprises:
At least one processor;
Have at least one computing machine available media of the computer-readable code that is included in wherein, described computer-readable code can be impelled described at least one processor:
In digital power managent component operational process, real time data is collected at least one position from described a plurality of positions of digital power managent component.
38., it is characterized in that described computer-readable code can also impel described at least one processor according to the described system of claim 37:
At least one other position in described a plurality of positions of digital power managent component provide real time data.
39., it is characterized in that described serial data transfer component comprises according to the described system of claim 37:
Shift register; And
Data can be written into and carry out the status switch generator of shift register.
40., it is characterized in that described status switch generator comprises according to the described system of claim 39:
Clock terminal; And
Data terminal;
Described status switch generator can utilize serial data transfer component clock source to make described controller component and described serial data transfer component synchronous as the reference clock.
41., it is characterized in that described status switch generator comprises according to the described system of claim 39:
Clock terminal; And
Data terminal;
Described status switch generator can utilize internal clocking to make described controller component and described serial data transfer component synchronous as the reference clock.
42. digitial controller according to claim 1 is characterized in that also comprising:
Can be from the serial data transfer component of/a plurality of position reception/transmission real time datas to digitial controller; And
The data collector element, it comprises:
At least one processor;
Have at least one computing machine available media of the computer-readable code that is included in wherein, described computer-readable code can be impelled described at least one processor:
In the digitial controller operational process, real time data is collected at least one position from described a plurality of positions of digitial controller.
43., it is characterized in that described calculating readable code can also impel described at least one processor according to the described system of claim 42:
At least one other position in described a plurality of positions in the digital power managent component provide real time data.
44., it is characterized in that described serial data transfer component comprises according to the described system of claim 42:
Shift register; And
Data can be written into and carry out the status switch generator of shift register.
45., it is characterized in that described status switch generator comprises according to the described system of claim 42:
Clock terminal; And
Data terminal;
Described status switch generator can utilize serial data transfer component clock source to make described controller component and described serial data transfer component synchronous as the reference clock.
46., it is characterized in that described status switch generator comprises according to the described system of claim 42:
Clock terminal; And
Data terminal;
Described status switch generator can utilize internal clocking to make described controller component and described serial data transfer component synchronous as the reference clock.
47. a numerically controlled method, this method comprises the following step:
The over-sampling simulating signal;
Utilize compensating filter that oversampled signals is carried out filtering; And
After compensating filter filtering, carry out low-pass filtering again and extract oversampled signals, extract and form the signal that is extracted.
48., it is characterized in that also including step according to the described method of claim 47:
After extracting, the signal that is extracted is carried out filtering with another compensating filter.
49. an A-D converter comprises:
Modulator element, it comprises:
Low resolution analog to digital conversion element;
Adjustable gain element, this adjustable gain element can receive the output of described low resolution analog to digital conversion element and can provide and equal the adjustable gain element output that adjustable multiplication factor multiply by the output of described low resolution analog to digital conversion element in fact; Described adjustable gain element can also the receiving gain setting signal and can be responded described gain setting signal and change described adjustable multiplication factor; Described adjustable gain element output is oversampled signals;
Receive the discrete integrator of adjustable gain element output; And
High resolving power digital to analog conversion system; Described high resolving power digital to analog conversion system receives the output of described discrete integrator;
Described low resolution analog to digital conversion system receives the signal that comprises difference between simulating signal and the output of described high resolving power digital to analog conversion system.
50., it is characterized in that also comprising withdrawal device according to the described A-D converter of claim 49.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US76509906P | 2006-02-03 | 2006-02-03 | |
| US60/765,099 | 2006-02-03 | ||
| US11/550,893 | 2006-10-19 |
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| CN101427227A true CN101427227A (en) | 2009-05-06 |
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| CNA2006800534356A Pending CN101427227A (en) | 2006-02-03 | 2006-11-14 | Systems and methods for digital control |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571316A (en) * | 2011-12-31 | 2012-07-11 | 清华大学 | Closed-loop timing adjustment method for wireless communication system |
| CN113032015A (en) * | 2019-12-24 | 2021-06-25 | 中国科学院沈阳自动化研究所 | Communication method for precision motion control |
-
2006
- 2006-11-14 CN CNA2006800534356A patent/CN101427227A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571316A (en) * | 2011-12-31 | 2012-07-11 | 清华大学 | Closed-loop timing adjustment method for wireless communication system |
| CN102571316B (en) * | 2011-12-31 | 2014-06-11 | 清华大学 | Closed-loop timing adjustment method for wireless communication system |
| CN113032015A (en) * | 2019-12-24 | 2021-06-25 | 中国科学院沈阳自动化研究所 | Communication method for precision motion control |
| CN113032015B (en) * | 2019-12-24 | 2022-02-18 | 中国科学院沈阳自动化研究所 | Communication method for precision motion control |
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